TW201642403A - 扇出晶圓級封裝及其製作方法 - Google Patents

扇出晶圓級封裝及其製作方法 Download PDF

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TW201642403A
TW201642403A TW104119904A TW104119904A TW201642403A TW 201642403 A TW201642403 A TW 201642403A TW 104119904 A TW104119904 A TW 104119904A TW 104119904 A TW104119904 A TW 104119904A TW 201642403 A TW201642403 A TW 201642403A
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cut
molding die
wafer
semiconductor package
semiconductor wafer
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TWI571984B (zh
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管式凡
施能泰
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華亞科技股份有限公司
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Abstract

本發明披露一半導體封裝，包含一半導體晶片，具有一主動面，其中至少一接墊設置於該半導體晶片的該主動面上；一成型模料，覆蓋住除了該主動面的該半導體晶片其他部分，其中該成型模料具有一與該半導體晶片的該主動面等高的一頂面；一重佈線層，直接位於該成型模料的該頂面與該半導體晶片的該主動面上；以及一翹曲控制切痕，切入該成型模料中，且靠近該半導體晶片。

Description

扇出晶圓級封裝及其製作方法
本發明概括而言係關於晶片封裝領域，特別是關於扇出(fan out)晶圓級封裝(wafer level packaging)技術。
已知，在晶片封裝製程中，常見將積體電路(IC)上的接墊重新佈線分配進一步扇出(fan out)的作法。一般，是藉由重佈線製程製作一重佈層(RDL)，將積體電路周圍區域的接墊再次佈線分配，轉換為間距較寬的焊接凸塊陣列。
上述方法得到所謂的扇出晶圓級封裝，其焊接凸塊陣列的凸塊間距較積體電路上的接墊間距寬，故容易整合到電子裝置及較大的晶片封裝中。
該領域技術人員所熟知的晶圓級封裝製程中，積體電路背面通常會覆蓋一層相對較厚的成型模料。此成型模料其熱膨脹係數(CTE)與積體電路和基底不同，除了容易導致封裝翹曲變形，也使得封裝整體的厚度增加。
上述翹曲問題在大尺寸的晶圓上更是嚴重，影響到晶圓級封裝製程良率。因此，業界仍需一個改良的晶圓級封裝方法，可以解決上述先前技術面臨的問題。
本發明的主旨在於提供一半導體封裝，可以減少或抑制晶圓或封裝發生翹曲的情況，因而具有更好的可靠度。
根據本發明所提供的半導體封裝，包含一半導體晶片，具有一主動面，其中至少一接墊設置於該半導體晶片的該主動面上；一成型模料，覆蓋住除了該主動面的該半導體晶片其他部分，其中該成型模料具有一與該半導體晶片的該主動面等高的一頂面；一重佈線層，直接位於該成型模料的該頂面與該半導體晶片的該主動面上；以及一翹曲控制切痕，切入該成型模料中，且靠近該半導體晶片。
根據本發明一實施例，該重佈線層將該接墊重新佈設至一位於該半導體晶片面積邊緣外的扇出接墊。該重佈線層包含至少一介電層。該介電層填入翹曲控制切痕中。
根據本發明另一實施例，該翹曲控制切痕切入該成型模料相對於該頂面的一底面。該翹曲控制切痕並未使該半導體晶片暴露出來。
無庸置疑的，該領域的技術人士讀完接下來本發明較佳實施例的詳細描述與圖式後，均可了解本發明的目的。
接下來的詳細敘述須參照相關圖式所示內容，用來說明可依據本發明具體實行的實施例。這些實施例提供足夠的細節，可使此領域中的技術人員充分了解並具體實行本發明。在不悖離本發明的範圍內，可做結構、邏輯和電性上的修改應用在其他實施例上。
因此，接下來的詳細描述並非用來對本發明加以限制。本發明涵蓋的範圍由其權利要求界定。與本發明權利要求具同等意義者，也應屬本發明涵蓋的範圍。
本發實施例所參照的附圖為示意圖，並未按比例繪製，且相同或類似的特徵通常以相同的附圖標記描述。
在本說明書中，“晶粒(die)”、“半導體晶片(semiconductor chip)”與“半導體晶粒(semiconductor die)”具相同含意，可交替使用
第1圖至第5圖為根據本發明一實施例的示意性剖面圖，以優先安裝晶片(chip-first method)的工序步驟，製作一扇出晶圓級封裝的方法。
如第1圖所示，半導體晶片10以主動面11朝下面對載體4的方式，分別安裝於載體4上。每一主動面11包含輸入/輸出(I/O)接墊120。重新排列好的半導體晶片10可以藉由黏合帶6固定在載體4上，但並不限於此。
如第2圖所示，接著在半導體晶片10上形成成型模料110，然後進行成型模料110的固化製程。成型模料110的材質類似一般半導體封裝製程中廣泛使用的環氧樹脂材料。
如第3圖所示，固化製程完成後，移除載體4與黏合帶6。成型模料110的頂面12被暴露出來。至目前階段，晶片10被嵌入在成型模料110中，且晶片10的主動面11自成型模料的頂面12暴露出來，主動面11上的輸入/輸出(I/O)接墊120也暴露出來供後續連接使用。根據所述實施例，成形模料110的頂面12大致上與晶片10的主動面11等高齊平。
接著，如第4A圖所示，進行一預切割製程，在成型模料110的頂面12中形成複數個翹曲控制切痕112。根據所述實施例，可用刀片、鋸子或雷射切割形成翹曲控制切痕112，但並不限於此。最佳者，翹曲控制切痕112的深度小於成型模料110的厚度。
翹曲控制切痕112可釋放由於熱膨脹係數(CTE)不同而產生的應力，因此可減少或抑制晶圓或封裝發生翹曲的情況，因而使扇出晶圓級封裝具有更好的可靠度。
根據所述實施例，翹曲控制切痕112僅位於晶片與晶片之間的切割道區域內且僅位於成型模料110的頂面12。須了解的是，翹曲控制切痕112可以是沿著切割路徑連續或不連續的切痕。
如第6A圖所示，晶片10之間包含第一方向(參考x-軸方向)的切割道區域50a~50d，與第二方向(參考y-軸方向)的切割道區域60a~60c。根據所述實施例，成型模料110的頂面12上的翹曲控制切痕112不一定形成在每一個切割道區域內。例如，第6A圖中，僅切割道區域50a、50b、50d和60a、60c具有翹曲控制切痕112。
如第6B圖所示的另一實施例中，晶圓具有一周圍環型結構80。周圍環型結構80是成型模料110位於晶圓邊緣的連續環形部分，形成翹曲控制切痕112時會避開周圍環型結構80區域，因此周圍環型結構80並不具有翹曲控制切痕112，可以提供晶圓較好的支撐力。
根據本發明另一實施例，如第4B圖所示，進行另一預切割製程，在成型模料110的底面13切割出複數個翹曲控制切痕114。值得注意的是，翹曲控制切痕114可位於晶片10下方區域的成型模料110中，只要不讓晶片10暴露出來。雖然並未在本說明書中特別強調，但應可了解翹曲控制切痕114可以是沿著切割路徑連續或不連續的切痕。
根據本發明又另一實施例，如第4C圖所示，僅預切割成型模料110的底面13，在底面13形成複數個翹曲控制切痕114。
第7A圖至第7C圖為平面圖，例示一些成型模料110底面13的翹曲控制切痕114圖形。例如，第7A圖中翹曲控制切痕114為同心圓形狀；第7B圖中翹曲控制切痕114為矩形交會形狀；第7C圖中翹曲控制切痕114形成非矩形交會。上述切痕圖案僅為例示說明。
回到第5圖，翹曲控制切痕112或/及114完成後，在成型模料110上製作重佈線層116。首先，在成型模料110的頂面12上沉積介電層118，然後進行圖案化製程，使晶片10原本的輸入/輸出(I/O)接墊120暴露出來。根據本發明實施例，介電層118會填入翹曲控制切痕112中。
接著，在介電層118上沉積導電層並進行圖案化製程，形成電性連接線122。然後重複與上述類似的步驟，沉積第二介電層124並圖案化，再沉積另一導電層並圖案化，形成重佈線接墊128，在重佈線接墊128上形成焊接凸塊130。最後，沿著切割道區域切割成型模料110，得到個別的扇出晶圓級封裝100。
須了解的是，本發明也可應用在習稱優先製作重佈線層(RDL-first process) 的封裝製程。第8圖至第10圖說明本發明另一實施例，為優先製作重佈線層(RDL-first process)的扇出晶圓級封裝製程方法，其中仍沿用相同的附圖標記表示相似的區域、材料層或元件。
如第8圖所示，在一可卸基底4上形成重佈線層(RDL)216。重佈線層216包含介電層218和224、介電層218和224中的金屬繞線222和接觸墊228，以及接觸墊228上的凸塊(或銅柱)230。須了解的是所述介電層與金屬繞線層數不拘，圖中所示僅為例示說明。
接著，如第9圖所示，將覆晶晶片10以主動面向朝重佈線層216的方式，藉由個別的凸塊230安裝至重佈線層216上。然後，在重佈線層216上形成成型模料110包覆住晶片10。此外，可選擇性地在重佈線層216與晶片10之間填入底膠(圖未示)。
如第10圖所示，成型模料110固化後，進行一預切割製程，在成型模料110的上表面形成複數個翹曲控制切痕214。接著移除基底4，使重佈線層216的底面暴露出來提供後續連接使用。須了解的是在其他實施例中，預切割製程可在移除基底4後才進行。
同樣地，翹曲控制切痕214的深度可小於成型模料110的厚度。值得注意的是翹曲控制切痕214可直接位於晶片10上方的成型模料110中，但不可使晶片10暴露出來。雖然並未在此特別強調，但應了解翹曲控制切痕214可為為沿著切割路徑連續或者不連續的切痕。
翹曲控制切痕214可釋放由於熱膨脹係數(CTE)不同而產生的應力，因此可減少或抑制晶圓或封裝發生翹曲的情況，改善該扇出晶圓級封裝的可靠度。 該領域中的技術人士可輕易知道在本發明的教示範圍內，依然可做許多修改。以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
4‧‧‧載體 6‧‧‧黏合帶 10‧‧‧半導體晶片 11‧‧‧主動面 12‧‧‧頂面 13‧‧‧底面 80‧‧‧周圍環型結構 100‧‧‧扇出晶圓級封裝 110‧‧‧成型模料 116‧‧‧重佈線層 118‧‧‧介電層 120‧‧‧輸入/輸出接墊 122‧‧‧電性連接線 124‧‧‧第二介電層 128‧‧‧重佈層接觸墊 130‧‧‧焊接凸塊 216‧‧‧重佈層 222‧‧‧金屬繞線 228‧‧‧接觸墊 230‧‧‧凸塊(或銅柱凸塊) 112/114/214‧‧‧翹曲控制切痕 218/224‧‧‧介電層 50a~50d‧‧‧第一方向切割道區域 60a~60c‧‧‧第二方向切割道區域
所附圖式提供對於此實施例更深入的了解，並納入此說明書成為其中一部分。這些圖式與描述，用來說明一些實施例的原理。 第1圖至第5圖為一實施例的示意性剖面圖，說明製作一扇出晶圓級封裝的方法，其中：第4A圖說明翹曲控制切痕僅位於成型模料的頂面；第4B圖說明翹曲控制切痕位於成型模料的頂面和底面；第4C圖說明翹曲控制切痕僅位於成型模料的底面。 第6A圖說明本發明一實施例的切割道區域和成型模料中的翹曲控制切痕。 第6B圖說明本發明另一實施例的切割道區域、成型模料的外圍環型結構和翹曲控制切痕。 第7A圖至第7C圖為平面圖，例示一些成型模料底面的翹曲控制切痕圖形。 第8圖至第10圖說明本發明另一實施例，為優先製作重佈線層(RDL-first process)的扇出晶圓級封裝製程方法。
10‧‧‧半導體晶片
11‧‧‧主動面
12‧‧‧頂面
13‧‧‧底面
100‧‧‧扇出晶圓級封裝
110‧‧‧成型模料
120‧‧‧輸入/輸出接墊
112/114‧‧‧翹曲控制切痕

Claims (10)

  1. 一種半導體封裝，包含: 一半導體晶片，具有一主動面，其中至少一接墊設置於該半導體晶片的該主動面上； 一成型模料，覆蓋住除了該主動面的該半導體晶片其他部分，其中該成型模料具有一與該半導體晶片的該主動面等高的一頂面； 一重佈線層，直接位於該成型模料的該頂面與該半導體晶片的該主動面上；以及 一翹曲控制切痕，切入該成型模料中，且靠近該半導體晶片。
  2. 如申請專利範圍第1項所述的半導體封裝，其中該接墊包含一輸入/輸出(I/O)接墊。
  3. 如申請專利範圍第1項所述的半導體封裝，其中該重佈線層該接墊重新設佈至一位於該半導體晶片邊緣外的扇出接墊。
  4. 如申請專利範圍第1項所述的半導體封裝，其中該重佈線層包含至少一介電層。
  5. 如申請專利範圍第4項所述的半導體封裝，其中該介電層填入該翹曲控制切痕中。
  6. 如申請專利範圍第1項所述的半導體封裝，其中該翹曲控制切痕切入該成型模料的該頂面。
  7. 如申請專利範圍第1項所述的半導體封裝，其中該翹曲控制切痕切入該成型模料相對於該頂面的一底面。
  8. 如申請專利範圍第7項所述的半導體封裝，其中該翹曲控制切痕並未使該半導體晶片暴露出來。
  9. 如申請專利範圍第1項所述的半導體封裝，其中該翹曲控制切痕為沿著其切割路徑的一連續切痕。
  10. 如申請專利範圍第1項所述的半導體封裝，其中該翹曲控制切痕為沿著其切割路徑的一不連續切痕。
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