CN106206457A - 半导体封装 - Google Patents

半导体封装 Download PDF

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CN106206457A
CN106206457A CN201510507385.5A CN201510507385A CN106206457A CN 106206457 A CN106206457 A CN 106206457A CN 201510507385 A CN201510507385 A CN 201510507385A CN 106206457 A CN106206457 A CN 106206457A
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semiconductor chip
cut channel
warpage
shaping mould
mould material
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CN106206457B (zh
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管式凡
施能泰
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Micron Technology Inc
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Inotera Memories Inc
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Abstract

本发明公开了一半导体封装，包括一半导体芯片，具有一主动面，其中至少一接垫设置在所述半导体芯片的所述主动面上；一成型模料，覆盖住所述半导体芯片的除了所述主动面的其他部分，其中所述成型模料具有一与所述半导体芯片的所述主动面等高的一上表面；一重布线层，直接位于所述成型模料的所述上表面与所述半导体芯片的所述主动面上；以及一翘曲控制切痕，切入所述成型模料中，并且靠近所述半导体芯片。

Description

半导体封装
技术领域
本发明概括而言是涉及芯片封装领域，特别是涉及扇出(fan out)晶圆级封装(wafer level packaging)技术。
背景技术
目前，在芯片封装工艺中，常见将集成电路(IC)上的接垫重新布线分配进一步扇出(fan out)的作法。一般而言，是通过重布线工艺制作一重布层(RDL)，将集成电路周围区域的接垫再次布线分配，转换为间距较宽的焊接凸块阵列。
上述方法得到所谓的扇出晶圆级封装，其焊接凸块阵列的凸块间距较集成电路上的接垫间距宽，因此容易整合到电子装置及较大的芯片封装中。
本领域技术人员所熟知的晶圆级封装工艺中，集成电路背面通常会覆盖一层相对较厚的成型模料。此成型模料的热膨胀系数(CTE)与集成电路和基底不同，除了容易导致封装翘曲变形，也使得封装整体的厚度增加。
上述翘曲问题在大尺寸的晶圆上更是严重，影响到晶圆级封装工艺良率。有鉴于此，业界仍需一个改良的晶圆级封装方法，可以解决上述先前技术面临的问题。
发明内容
本发明的目的在于提供一半导体封装，可以减少或抑制晶圆或封装发生翘曲的情况，因而具有更好的可靠度。
根据本发明所提供的半导体封装，包括一半导体芯片，具有一主动面，其中至少一接垫设置在所述半导体芯片的所述主动面上；一成型模料，覆盖住所述半导体芯片的除了所述主动面的其他部分，其中所述成型模料具有一与所述半导体芯片的所述主动面等高的一上表面；一重布线层，直接位于所述成型模料的所述上表面与所述半导体芯片的所述主动面上；以及一翘曲控制切痕，切入所述成型模料中，并且靠近所述半导体芯片。
根据本发明一实施例，所述重布线层将所述接垫重新布设到一位于所述半导体芯片面积边缘外的扇出接垫。所述重布线层包括至少一介电层。所述介电层填入翘曲控制切痕中。
根据本发明另一实施例，所述翘曲控制切痕切入所述成型模料相对于所述上表面的一下表面。所述翘曲控制切痕并未使所述半导体芯片暴露出来。
毋庸置疑的，所述领域的技术人士读完接下来本发明优选实施例的详细描述与附图后，均可了解本发明的目的。
附图说明
图1到图5为实施例一的示意性剖面图，说明制作一扇出晶圆级封装的方法，其中：图4A说明翘曲控制切痕仅位于成型模料的上表面；图4B说明翘曲控制切痕位于成型模料的上表面和下表面；图4C说明翘曲控制切痕仅位于成型模料的下表面。
图6A说明本发明实施例二的切割道区域和成型模料中的翘曲控制切痕。
图6B说明本发明实施例三的切割道区域、成型模料的外围环型结构和翘曲控制切痕。
图7A到图7C为平面图，例示一些成型模料下表面的翘曲控制切痕图形。
图8到图10说明本发明实施例四，为优先制作重布线层(RDL-first process)的扇出晶圆级封装工艺方法。
其中，附图标记说明如下：
4 载体
6 黏合带
10 半导体芯片
11 主动面
12 上表面
13 下表面
80 周围环型结构
100 扇出晶圆级封装
110 成型模料
116 重布线层
118 介电层
120 输入/输出接垫
122 电性连接线
124 第二介电层
128 重布层接触垫
130 焊接凸块
216 重布层
222 金属绕线
228 接触垫
230 凸块(或铜柱凸块)
112/114/214 翘曲控制切痕
218/224 介电层
50a～50d 第一方向切割道区域
60a～60c 第二方向切割道区域
具体实施方式
接下来的详细说明须参考相关附图所示内容，用来说明可依据本发明具体实施的实施例。这些实施例提供足够的细节，可使本领域中的技术人员充分了解并具体实施本发明。在不悖离本发明的范围内，可做结构、逻辑和电性上的修改应用在其他实施例上。
因此，接下来的详细描述并非用来对本发明加以限制。本发明涵盖的范围由其权利要求界定。与本发明权利要求具同等意义者，也应属本发明涵盖的范围。
本发明实施例所参照的附图为示意图，并未按比例绘制，而且相同或类似的特征通常以相同的附图标记描述。
在本说明书中，“晶粒(die)”、“半导体芯片(semiconductor chip)”与“半导体晶粒(semiconductor die)”具有相同含意，可以交替使用。
图1到图5为根据本发明实施例一的示意性剖面图，以优先安装芯片(chip-first method)的工序步骤，制作一扇出晶圆级封装的方法。
如图1所示，半导体芯片10以主动面11朝下面对载体4的方式，分别安装到载体4上。每一主动面11包括输入/输出(I/O)接垫120。重新排列好的半导体芯片10可以通过黏合带6固定在载体4上，但并不限于此。
如图2所示，接着在半导体芯片10上形成成型模料110，然后进行成型模料110的固化工艺。成型模料110的材料可以选用一般半导体封装工艺中广泛使用的环氧树脂材料。
如图3所示，固化工艺完成后，移除载体4与黏合带6。成型模料110的上表面12被暴露出来。到目前阶段，半导体芯片10被嵌入在成型模料110中，而且半导体芯片10的主动面11自成型模料的上表面12暴露出来，主动面11上的输入/输出(I/O)接垫120也暴露出来提供后续连接使用。根据所述实施例，成形模料110的上表面12大致上与半导体芯片10的主动面11等高齐平。
接着，如图4A所示，进行一预切割工艺，在成型模料110的上表面12中形成多个翘曲控制切痕112。根据所述实施例，可用刀片、锯子或雷射切割形成翘曲控制切痕112，但并不限于此。最佳实施例中，翘曲控制切痕112的深度小于成型模料110的厚度。
翘曲控制切痕112可释放由于热膨胀系数(CTE)不同而产生的应力，因此可减少或抑制晶圆或封装发生翘曲的情况，因而使扇出晶圆级封装具有更好的可靠度。
根据所述实施例，翘曲控制切痕112仅位于芯片与芯片之间的切割道区域内而且仅位于成型模料110的上表面12。须了解的是，翘曲控制切痕112可以是沿着切割路径连续或不连续的切痕。
如图6A所示的实施例二中，半导体芯片10之间包括第一方向(参考x-轴方向)的切割道区域50a～50d，与第二方向(参考y-轴方向)的切割道区域60a～60c。根据所述实施例，成型模料110的上表面12上的翘曲控制切痕112不一定形成在每一个切割道区域内。例如，图6A中，仅切割道区域50a、50b、50d和60a、60c具有翘曲控制切痕112。
如图6B所示的实施例三中，晶圆具有一周围环型结构80。周围环型结构80是成型模料110位于晶圆边缘的连续环形部分，形成翘曲控制切痕112时会避开周围环型结构80区域，因此周围环型结构80并不具有翘曲控制切痕112，可以提供晶圆较好的支撑力。
根据本发明另一实施例，如图4B所示，进行另一预切割工艺，在成型模料110的下表面13切割出多个翘曲控制切痕114。值得注意的是，翘曲控制切痕114可位于半导体芯片10下方区域的成型模料110中，只要不让半导体芯片10暴露出来。虽然并未在本说明书中特别强调，但应可了解翘曲控制切痕114可以是沿着切割路径连续或不连续的切痕。
根据本发明又另一实施例，如图4C所示，仅预切割成型模料110的下表面13，在下表面13形成多个翘曲控制切痕114。
图7A到图7C为平面图，例示一些成型模料110下表面13的翘曲控制切痕114图形。例如，图7A中翘曲控制切痕114为同心圆形状；图7B中翘曲控制切痕114为矩形交会形状；图7C中翘曲控制切痕114形成非矩形交会。上述切痕图案仅为例示说明。
回到图5，翘曲控制切痕112或/及翘曲控制切痕114完成后，接着在成型模料110上制作重布线层116。首先，在成型模料110的上表面12上沉积介电层118，然后进行图案化工艺，使半导体芯片10原本的输入/输出(I/O)接垫120暴露出来。根据本发明实施例，介电层118会填入翘曲控制切痕112中。
接着，在介电层118上沉积导电层并进行图案化工艺，形成电性连接线122。然后重复与上述类似的步骤，沉积第二介电层124并图案化，再沉积另一导电层并图案化，形成重布线接垫128，在重布线接垫128上形成焊接凸块130。最后，沿着切割道区域切割成型模料110，得到个别的扇出晶圆级封装100。
须了解的是，本发明也可应用在优先制作重布线层(RDL-first process)的封装工艺。图8到图10说明本发明实施例四，为优先制作重布线层(RDL-firstprocess)的扇出晶圆级封装工艺方法，其中仍沿用相同的附图标记表示相似的区域、材料层或器件。
如图8所示，在一可卸基底4上形成重布线层(RDL)216。重布线层216包括介电层218和224、介电层218和224中的金属绕线222和接触垫228、以及接触垫228上的凸块230，凸块230可以是铜柱凸块。须了解的是所述介电层与金属绕线层数不限制为本实施例所示，图中所示仅为例示说明。
接着，如图9所示，将覆晶半导体芯片10以主动面朝向重布线层216的方式，通过个别的凸块230安装到重布线层216上。然后，在重布线层216上形成成型模料110包覆住半导体芯片10。此外，可选择性的在重布线层216与半导体芯片10之间填入底胶(图未示)。
如图10所示，成型模料110固化后，进行一预切割工艺，在成型模料110的上表面形成多个翘曲控制切痕214。接着移除基底4，使重布线层216的下表面暴露出来提供后续连接使用。须了解的是在其他实施例中，预切割工艺可在移除基底4后才进行。
同样的，翘曲控制切痕214的深度可小于成型模料110的厚度。值得注意的是翘曲控制切痕214可直接位于半导体芯片10上方的成型模料110中，但不可使半导体芯片10暴露出来。虽然并未在此特别强调，但应了解翘曲控制切痕214可为为沿着切割路径连续或者不连续的切痕。
翘曲控制切痕214可释放由于热膨胀系数(CTE)不同而产生的应力，因此可减少或抑制晶圆或封装发生翘曲的情况，改善所述扇出晶圆级封装的可靠度。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (10)

1.一种半导体封装，其特征在于，包括:
一半导体芯片，具有一主动面，其中至少一接垫设置在所述半导体芯片的所述主动面上；
一成型模料，覆盖住所述半导体芯片的除了所述主动面的其他部分，其中所述成型模料具有与所述半导体芯片的所述主动面等高的一上表面；
一重布线层，直接位于所述成型模料的所述上表面与所述半导体芯片的所述主动面上；以及
一翘曲控制切痕，切入所述成型模料中，并且靠近所述半导体芯片。
2.根据权利要求1所述的半导体封装，其特征在于，所述接垫包括一输入/输出接垫。
3.根据权利要求1所述的半导体封装，其特征在于，所述重布线层将所述接垫重新设布至一位于所述半导体芯片边缘外的扇出接垫。
4.根据权利要求1所述的半导体封装，其特征在于，所述重布线层包括至少一介电层。
5.根据权利要求4所述的半导体封装，其特征在于，所述介电层填入所述翘曲控制切痕中。
6.根据权利要求1所述的半导体封装，其特征在于，所述翘曲控制切痕切入所述成型模料的所述上表面。
7.根据权利要求1所述的半导体封装，其特征在于，所述翘曲控制切痕切入所述成型模料相对于所述上表面的一下表面。
8.根据权利要求7所述的半导体封装，其特征在于，所述翘曲控制切痕并未使所述半导体芯片暴露出来。
9.根据权利要求1所述的半导体封装，其特征在于，所述翘曲控制切痕为沿着其切割路径的一连续切痕。
10.根据权利要求1所述的半导体封装，其特征在于，所述翘曲控制切痕为沿着其切割路径的一不连续切痕。
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