TW201630141A - 晶片封裝 - Google Patents

晶片封裝 Download PDF

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TW201630141A
TW201630141A TW105104856A TW105104856A TW201630141A TW 201630141 A TW201630141 A TW 201630141A TW 105104856 A TW105104856 A TW 105104856A TW 105104856 A TW105104856 A TW 105104856A TW 201630141 A TW201630141 A TW 201630141A
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core substrate
thinned
glass substrate
circuit layer
chip package
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胡迪群
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胡迪群
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
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    • H—ELECTRICITY
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    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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    • H05K1/02—Details
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    • H05K1/111—Pads for surface mounting, e.g. lay-out
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    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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Abstract

本技藝的實施例一顯示一種晶片封裝，包含有一個核心基材；至少一根導通金屬穿過核心基材；上層金屬電路層設置於核心基材的上方；至少一片晶片設置於上層金屬電路層上方。核心基材的周邊呈現削薄的邊緣狀，這種結構係基於本技藝製作了一個「預先切口」於核心基材的切割線上下，使得切割時核心基材的破損率降低而提高生產良率。核心基材可以是玻璃基材、陶瓷基材、石英基材、環氧樹脂玻璃纖維、或是填充材料聚合物基材。

Description

晶片封裝
本發明係有關於電子元件的封裝，尤其是IC晶片的封裝。
電子元件的封裝尤其是消費性與工業應用的IC晶片的封裝，需要配合智慧手機、平板電腦、以及其他攜帶式電子產品的快速成長的需求。用以保護脆弱的IC晶片的封裝基材或是晶片載體，除了提供機械穩固性以外，也需要提升電性連接的密集度。
晶片與晶片承載器(carrier)之間的熱膨脹係數(Coefficient of Thermal Expansion,CTE)的匹配，需要新的印刷電路板(Printed Circuit Board,PCB)設計技術，特別是以玻璃基材當作核心基材的狀況。當電路密度愈高時，板翹、晶片破裂以及其他封裝缺陷亦會逐漸浮現。當玻璃基材的厚度愈來愈薄時，金屬電路層(build-up layer)的介電材料與玻璃基材之間的CTE的匹配愈形重要。
另外一個問題是晶片的切割(singulation)，因為玻璃基材比較不像聚合物基材(polymer substrate)那樣容易切割，玻璃基材在切割時可能破裂，尤其是以機械切割的方式去切割玻璃時，破裂問題愈形顯著。
到目前為止，發展CTE匹配的玻璃基材且不易破裂的基材作為晶片封裝一直未能有效率執行，開發一種CTE匹配的玻璃基材作為晶片封 裝，可以有效率執行且提升良率的製程產品，是下一代的晶片封裝很重要的技藝。
基於先前技藝中，玻璃基材被切割時，容易破裂的缺陷，本發明提供一種創新技藝，晶片封裝製程中，製作「預先切口」於核心玻璃基材，切割以產出元件單元時，可以降低破裂的機率；本發明提供一個方便有效率且良率提高的封裝技藝。金屬電路層(Bulid-up layer)製作於玻璃基材上面，提高電路密度也提高整體的機械穩固性。
玻璃基材核心上方與下方，分別製作有電路層。至少一根「縱向導通金屬」(through via)設置於玻璃基材核心中，導通核心基材上方與下方的金屬電路層；玻璃基材核心周圍設置有削薄的邊緣，介電材料設置於削薄的邊緣上方。
本發明實施例一，顯示一個晶片封裝，包含有玻璃基材作為核心基材，具有至少一根「縱向導通金屬」，核心基材上方的金屬電路層與下方的金屬電路層，藉由該「縱向導通金屬」做電性耦合。玻璃基材周邊設置成「逐漸削薄」(tapered)的形狀。介電材料設置於「逐漸削薄」區的玻璃基材的上方，介電材料下方順應形狀填滿「逐漸削薄」的上方。介電材料與「逐漸削薄」的核心基材的外邊為一致的垂直切割面。
本發明另一實施例，顯示一個晶片封裝，包含玻璃基材作為核心基材，具有至少一根「縱向導通金屬」設置於玻璃基材中，玻璃基材核心上方的金屬電路層與下方的金屬電路層，藉由該「縱向導通金屬」做電性耦合。玻璃基材周邊設置成「逐漸削薄」(tapered)的形狀，封裝 材料設置於「逐漸削薄」區的玻璃基材的周邊外環，使得晶片封裝外圍具有圓滑邊緣，避免尖銳邊緣刮傷其他元件。
100,200‧‧‧封裝基材
110,210‧‧‧玻璃基材(核心基材)
112,212‧‧‧切割線
115,215‧‧‧縱向導通金屬
120a,120b‧‧‧光阻層
122‧‧‧削薄的邊緣
125,125R,225,225R‧‧‧預先切口
130,230‧‧‧金屬電路層
131‧‧‧介電材料
132,232‧‧‧銲墊
135,235‧‧‧金屬
140,240‧‧‧抗銲材料層
142,242‧‧‧銲墊
145,245‧‧‧開口
149‧‧‧溝槽
155‧‧‧切面
180‧‧‧電路板
250‧‧‧銲錫球
260‧‧‧封裝膠體
圖1A~1F是本發明實施例一的剖面圖的製程示意圖
圖2A~2E是本發明實施例二的剖面圖的製程示意圖
圖1A~1F是本發明實施例一的剖面圖的製程示意圖
圖1A顯示玻璃基材110，例如一片20"x20"(平方英寸)的玻璃基材作為核心基材，其他可用的基材包含陶瓷基材、石英基材、環氧樹脂玻璃纖維、或是填充材料聚合物基材。玻璃基材110具有至少一根穿過玻璃基材的「縱向導通金屬」115(through glass via,TGV)；銲墊132、以及後續製成會將金屬電路層形成於玻璃基材110上面與下面。其中的穿過玻璃的通孔(via)，可以用機械穿孔、雷射穿孔、電漿蝕刻等方式進行，然後填充金屬，產生「縱向導通金屬」115。量產時，玻璃基材110包含有多個單元，沿著切割線(kerf line)112切割，便可以獲得個別單元。
圖1B顯示光阻層120a,120b分別形成於玻璃基材的上面與下面。然後，光阻層120a,120b被圖案化，製作溝槽149於切割線(kerf line)112位置。然後，在切割線位置，製作預先切口125,125R於核心基材表面上方與下方。
圖1C顯示在切割線112位置，移除光阻層120a形成溝槽149，溝槽底部製作出「預先切口」125；下方對應位置也製作出「預先切口」125R；這些預先切口125,125R，使得切割線(kerf line)位置的玻璃基材110變薄，便於後續的切割製程可以降低玻璃基材的破裂機率。「預先切口」125,125R的形狀，可以是彎曲、階梯、或是楔型。
圖1D顯示上層金屬電路層130製作於玻璃基材110的上面，其中上層金屬電路層130包含電路與介電材料交互安置，製程中包含盲孔金屬135以及銲墊132的設置，這些金屬電路層，係依據習知技藝製成。抗銲材料層140具有開口145使得銲墊142裸露出來，便於後續的電性連接。
金屬132、135、142，分別製作於玻璃基材上下兩邊。銲墊142的材料是可銲接的金屬材料，例如鎳/金(Ni/Au)、鎳/鈀(Ni/Pd)、鎳/鈀/金(Ni/Pd/Au)等。
圖1E顯示依據「切割線」對封裝基材做「切割」以後，可以獲得產品的個別單元。本發明的溝槽125,125R是預先製作於切割線上下，方便後續正式切割時，玻璃基材較薄而較不易破裂，使得切割良率提高。這個預先製作的溝槽，可以經由機械切割、化學蝕刻、雷射蝕刻、或是上述方法的結合執行而獲得。
本發明實施例一顯示，一個切割出來的封裝基材100，包含玻璃基材110為核心基材，玻璃基材110具有至少一條「縱向導通金屬」 115用以導通玻璃基材110上方與下方的金屬電路層。玻璃基材110具有一個周邊，該周邊呈現出削薄的邊緣122，介電材料131安置於玻璃基材削薄的邊緣122周邊上方；介電材料131的上方為平面狀，下方沿著削薄的邊緣122的外型凹凸，覆蓋著玻璃基材削薄的邊緣122；玻璃基材削薄的邊緣122外部與上下金屬墊路層一致為切割後的陡峭的切面155。
圖1F顯示封裝基材100具有銲墊142以及錫鉛球150，提供晶片170自上方安置於封裝基材100的上面。封裝基材100下方適合於安置於電路板180。封裝基材100可以容納一個以上的晶片安置於上方，構成多晶片封裝(multi-chip module,MCM)。本發明的封裝，可以結合MCM、薄膜電路層、被動元件等，構成「系統級封裝」(system in package,SiP)。
圖2A~2E是本發明實施例二的剖面圖的製程示意圖
圖2A顯示玻璃基材210具有穿過玻璃基材的縱向導通金屬215，縱向導通金屬215連接基材210上方與下方的金屬電路層。銲墊232設置於縱向導通金屬215上端與下端，分別提供上下層金屬連接用。然後，沿著切割線212切割，便可以獲得多個產品單元。
電路層230包含有銲墊232與金屬235，分別製作於玻璃基材210上方與下方。抗銲材料層240設置於金屬電路層230的外層，具有開口245使銲錫墊242裸露，便於後續電性連接用。
金屬化製程包含製作銲墊232、電路235、銲錫球250等結構於玻璃基材的上方與下方。其他實施例中的銲墊242係以銲錫材料製成，例如：鎳/金(Ni/Au)、鎳/鈀(Ni/Pd)、鎳/鈀/金(Ni/Pd/Au)等。其他實施例中，錫膏被設置於銲墊上。
圖2B顯示在切割線212位置，移除介電材料形成溝槽249。圖2C顯示在溝槽249底部製作出「預先切口」225，這個預先切口可以採用雷射蝕刻、或是機械切割。在預先切口225另外一面的對應位置，也製作出預先切口225R；圖2C顯示預先切口225,225R被製作於溝槽249下方的玻璃基材210表面，使玻璃基材210上下厚度變薄，這個預先切口225,225R使得後續切割玻璃基材210時，可以減少玻璃基材破裂機會，而提高切割後的產品良率。預先切口225,225R的形狀，可以是弧狀、階梯狀、或是楔形狀。
圖2D顯示將圖2C沿著切割線212切割，得到一個封裝單元，周邊以封裝膠體260封裝單元周邊。切割的方式可以是機械切割；化學蝕刻、雷射切割、或是前述方法的混合式切割。
圖2E顯示封裝基材200包含銲墊242以及銲錫球250設置於單元外層，提供晶片以表面黏著方式固著於封裝基材200之用。
前述描述揭示了本發明之較佳實施例以及設計圖式，惟，較佳實施例以及設計圖式僅是舉例說明，並非用於限制本發明之權利範圍於此，凡是以均等之技藝手段實施本發明者、或是以下述之「申請專利範 圍」所涵蓋之權利範圍而實施者，均不脫離本發明之精神而為申請人之權利範圍。
170‧‧‧晶片
150‧‧‧錫鉛球
100‧‧‧晶片封裝單元
180‧‧‧電路板

Claims (8)

  1. 一種晶片封裝，包含：核心基材；至少一根縱向導通金屬，穿過所述之核心基材；上層金屬電路層埋藏於上層介電材料中，其中所述之上層金屬電路層以及上層介電材料設置於所述之核心基材的上方；複數個上層銲墊，設置於所述之上層金屬電路層的上方；以及削薄的邊緣，設置於核心基材的周邊；其中所述之核心基材的材料，係選自於下述材料族群中的一種：玻璃、陶瓷、石英、環氧樹脂玻璃纖維、填充材料聚合物。
  2. 如申請專利範圍第1項所述之一種晶片封裝，其中所述之上層金屬電路層與所述之核心基材的對應邊緣，係呈切齊狀。
  3. 如申請專利範圍第2項所述之一種晶片封裝，其中所述之核心基材的邊緣削薄狀，其削薄的剖面形狀，係呈現下述形狀族群中的一種：弧狀、階梯狀、或是楔形狀。
  4. 如申請專利範圍第1項所述之一種晶片封裝，更包含：晶片，安置於所述之上層銲墊的上方。
  5. 如申請專利範圍第1項所述之一種晶片封裝，其中所述之削薄的邊緣，係向著周邊凸出於所述之上層金屬電路層邊緣。
  6. 如申請專利範圍第5項所述之一種晶片封裝，其中所述之核心基材的削薄狀，其削薄狀的剖面，係呈現下述形狀族群中的一種：弧狀、階梯狀、或是楔形狀。
  7. 如申請專利範圍第6項所述之一種晶片封裝，更包含一種封裝材料，包裹所述之削薄的邊緣。
  8. 如申請專利範圍第5項所述之一種晶片封裝，更包含：晶片，安置於所述之上層銲墊的上方。
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