TW200820410A - Semiconductor packaging structure - Google Patents

Semiconductor packaging structure Download PDF

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Publication number
TW200820410A
TW200820410A TW096110958A TW96110958A TW200820410A TW 200820410 A TW200820410 A TW 200820410A TW 096110958 A TW096110958 A TW 096110958A TW 96110958 A TW96110958 A TW 96110958A TW 200820410 A TW200820410 A TW 200820410A
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TW
Taiwan
Prior art keywords
layer
substrate
substrate layer
die
semiconductor package
Prior art date
Application number
TW096110958A
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English (en)
Inventor
Gene Wu
Original Assignee
Taiwan Semiconductor Mfg
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Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg filed Critical Taiwan Semiconductor Mfg
Publication of TW200820410A publication Critical patent/TW200820410A/zh

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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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Description

200820410 九、發明說明： 【發明所屬之技術領域】 本發明有關於一種半導體晶片之封奘， 於一種嵌入半導體晶片至封裝體之結構及方法。、別有關 【先前技術】 在半導體工業中’積體電路_般係形成於上，
其中，在同-片晶圓上之多個半導體晶片可同時形成， 因此，这些半導體晶片隨後可從晶圓上切割出來， =這^導體晶片體積既小且易碎，因此在使料些 曰曰片之刖必須先予以封裝。 — 第1圖顯示一傳統的封裝體，其包括 (晶粒)2 ’其可透過凸塊(SQlder bumps)6附著於封餘曰二4 上，封裝基底4包括—核心層8及多個建構在核心層8 土：兩，内連線層，晶粒2和核心層"皮内連線層曰所 刀隔。日曰粒2附著在核心層8之一侧，而在其相 側電性連接至另 一侧，則形成賴陣列(BGA)之錫球1G以連接封裝基底 至八他的電子兀件，例如主機板(咖Inboard)，晶粒2 和球間陣狀錫球1G係透過㈣線層之金屬線和插塞進 行電性•接。插塞12則形成於核心層8中以從核心層8 側 '一 ^fSil Φ iW- ^ ΎΖ rJ » . ★傳統封裝體的問題如下。首先，形成凸塊的成本很 Γ.’, f如果凸塊連接失敗也容易使封裝製程遭遇到高的 (率損失。其次，晶粒2_般具有的熱膨脹係數(CTE)大 〇503-A32702TWF；chadchou 5 200820410 約為2.3至4·2，另一方面，核心層8由於一般係由雙馬 末亞 二氮雜苯樹脂（Bismaleimide-Triazine; BT)形 成，其熱膨脹係數大約為15,因此，在熱循環製程之下， 不匹配的熱膨脹係數所導致施加在晶粒2和凸塊6上的 應力胃使得晶粒2產生麵曲，及/或使得凸塊連接失敗。 第三，由於使用核心層8，封裝體的厚度會有所增加，其 中包括BGA錫球1〇、封裝基底4、晶粒2在内之整個封 參裝體的總厚度可S 2.3mm，此種過厚的厚度並不符未來 的規格需求’因此需要_種新穎的封裝結構來改善上述 【發明内容】 有=此，树明之—實施例揭露—種半導體封裝 、、“冓，包括：一基板層’其成份包括合金42材料；一曰 二=基板層之一第一側面上；及-内連線結構:θ 線。中内連線結構包括插塞及連接晶粒之導 本發明之另一實施例揭露一種半導體 :厂第:基板層’其成份包括合金42材料二= 板層’附㈣第-基板層之_第—侧面上；基 :第二基板層中；-晶粒，位於開口中，且附：位 ::層之第一側面上；一第一絕緣層，位 及：- 基板層上，·複數個第—插塞，位*日日，及弟二 觸晶粒；及一内連後社 、、、’ k中且貫體性接 連線結構，位於第-絕緣層上，其中， 〇503-A327〇2TWF;chadchou 6 200820410 内連線結構包括··—第二絕緣層’複數個第二插塞及導 位於第二絕緣層中，其中至少有部分之第二插塞及 導線連接到該些第—插塞；及複數個球閘陣列錫球，位 於内連線結構之上表面。 本發明實施例之優點在於合金42材料和半導體晶 熱膨脹係數’因此由封裝體施加予晶粒之= 力可以減少。
為了讓本發明之上述和其他目的、特徵、和優點 更明顯易懂，下女牲與 & # —。 ”、 作詳細說明如2舉—te佳貫施例’並配合所附圖示， L貫施方式】 有關各實施例之製造和使时式係如以下 然而’值得注意的是，本發明所提供之各種可應 明概念係依具體内文的各種變化據以實施， ^ =不實僅是用來顯示具體使用和製造本發明: 方法而不疋用於限定本發明之範圍。 方法本為—種軸㈣μ構及其形成 /、衣每過％係顯不於第2圖至第1〇圖。此 本發明之各種實_㈣示t， 3 同或類似元件。 竹現係用从’日不相 第2圖顯示一起始製程的結構，其包括 20,基板層24以及黏著材料22。在—實施财 j 2〇的成分包括一含有合金42材料⑽〇y42)_心; 0503-A32702TWF;chadchou 7 200820410 2(h，此材料為一鎳鐵合金，在以下段落中會予以詳述。 此外，兩核心層202的成分包含有銅材料，其可電鍍在核 心層2〇ι的兩侧，同樣地，基板層24包括一含有合金42 材料（alloy 42)的核心層24!，此外，兩核心層242包含有 銅材料，其可電鍍在核心層24:的兩侧。 合金42材料大約包括42%之重量百分比的鎳以及 58%之重量百分比的鐵，而編號42係指鎳所佔的百分 比。合金42材料之彈性係數約為每平方英吋（PSI) 20.7E6 磅，熱膨脹係數（CTE)約為4.0E-06/K至4.7E-06/K，導熱 率約為16W/mk，以及電阻值約為70μ-Ω·(；ηι。基板層20 之厚度大體可為4密爾（mil)，同時，基板層24之厚度大 鉍可為12密爾（mil)。基板層20和基板層24不僅可以對 後續製程所附著的晶粒提供保護，也可以提供結構性的 支撐。基板層20和基板層24可以隨著層壓（laminating press)的方式而藉由黏著材料22黏接，例如是半固化片 (prepreg ; preimpregTiflieii 。雖然，基板層 20 和 基板層24可視為合金42材料，然而，其也允許有些微 不同的組成，但須和合金42材料有相同的熱膨脹係數。 請參考第3圖，開口 26和28係藉由除去部分的基 板層24和黏著材料22而形成，開口 26係設定用於放置 晶粒，因此開口 26的大小係決定於晶粒的尺寸。開口 28 則可選擇性的形成以放置可整合到封裝體的電子元件， 例如電容或電阻等被動元件。在另一實施例中，開口 26 和28也可以在貼附基板層24至基板層20之前預先形成。 0503-A32702TWF;chadchou 8 200820410 在第4圖中，晶粒30被放置在開口 26内且附著於 基板層20上，較佳的做法是以例如銀漿作為黏著材料。 電子元件32也可被放置在開口 28内且附著於基板層2〇 請參考第5圖，絕緣層34被形成在先前的結構上， 絕緣層34包括一有機材料’例如曰本Ajinomot〇公司所 供應的增層膜材料（ABF ; Ajinomoto buildup film)，然而， φ 其他一般材料例如半固化片（prepreg)或是背膠銅箔 (RCC ; resin coated copper)亦可使用，在本例中，絕緣層 34疋以ABF材料形成，此ABF材料可被層壓在第4圖 的結構上，熱和壓力可以施加在此層上而軟化以形成平 坦的上表面。此熱和壓力也可以協助絕緣層34填入晶粒 3〇(或是電子元件32)和基板層24間的空間，結果，在晶 粒30之上表面和絕緣層34之上表面間之厚度T1較佳為 大約25μηι至35μπι，最佳值則約為30μιη。 ϋ 隨後形成開口 38以暴露出在晶粒30上表面的接觸 墊4〇(也稱為凸塊底金屬層（under bump metallurgy);或簡 稱UBM)。較佳者，開口 38係藉由雷射鑽孔形成，其中 覆蓋UBM 40的絕緣層34被予以燒除。此外，也可形成 開口 42以暴露出在電子元件32上表面的接觸墊（未顯 示）。 第6圖顯示藉由選擇性填充導電材料至開口 38和 42以形成插塞44(by_vias)的方式。此導電材料可以是一 般常用的材料，例如在一實施例中，此導電材料包括銅 〇5〇3-A32702TWF;chadchou 200820410 或銅合金，然而，其他如銀或鋁亦可使用。此填充方法 包括無電鍍或.電鍍製程，插塞44係直接連接UBM 40以 及在後續步驟形成於插塞44上的内連線結構，因此凸塊 (solder bumps)是不需要的。此外，插塞44也連接内連線 結構和電子元件32,較佳者，插塞44之上表面係實質上 和絕緣層34的上表面等高，或者，插塞44之上表面係 稍微低於絕緣層34的上表面。 請參考第7圖，一薄的種晶層46，較佳者包括銅材 ⑩ 料，可形成於絕緣層34和插塞44之表面上，其中，無 電鍍製程是較佳的實施方法，此薄的種晶層46之較佳厚 度約為小於0.8μιη。乾膜（dry film) 48接著形成於種晶層 46上，隨後進行一圖案化製程以形成開口，以由後續形 成之金屬線填入其中。乾膜48的厚度較佳值是依據後續 所形成之導線的厚度來決定，例如在一實施例中，乾膜 48的厚度T2是介於約20μπι和25μηι之間，更佳者是約 20μηι 〇 ® 請參閱第8圖，導電圖案50係形成在種晶層46中 未被乾膜48覆蓋的部分上，其可包括導線和導電墊，形 成方式例如為選擇性電鍍法。導電圖案50之較佳形成厚 度是實質接近乾膜48的厚度，導電圖案50之較佳材料 是銅或銅合金，然而，其他一般常用金屬材料例如銀、 鋁、及鎳等亦可使用。導電圖案50之上表面較佳者係實 質上和乾膜48的上表面等高，或者，導電圖案50之上 表面亦可稍微低於乾膜48的上表面。在形成導電圖案50 0503-A32702TWF;chadchoii 10 200820410 之後，乾膜48和種晶層46中位於乾膜48之下的部分被 併去除，例如在一實施例中，乾膜48可以鹼性溶液去 除’而種晶層46中位於乾膜48之下的部分則可以快速 餘刻製程（flash etching)去除。由於側面效應（_他叫 的關係’在快速餘刻製程中，導電圖案50也會被去除掉
明芩考第9圖，接著坦覆式形成絕緣層52，i可選 擇使用^絕緣層34之實質相同方法和實質相同材料形 成攸導電圖案50之上表面到絕緣層52之上表面的厚 度T3較，者為逼近厚度们，例如是大約卿心 接績製程則是形成更多的内連線層，包括插塞和導 笔圖案，其最終結構顯示於第1〇圖中。對每一内連線層 二 步驟土可以和插塞44及導電圖案50之形： 括由二二目5 乂佳者’可以形成3到5層之内連線層（包 括由插I 44和導電圖案5〇構成之内連線層），其中每一 固内連線層包括-層導電圖案及其下方之插塞。 程亦二^二广例中，其他已知的方法，例如鑲嵌製 用於:成内連線層’-般而言，侧程包括如 成絕緣層’然後形成開口於絕緣層中，再 以銅或銅合金箄導帝UT 丹 制A/、 材科填入開口，執行化學機械研磨 衣私以去除多餘的導電材料， 則形成插塞和㈣圖案。 线狀繼# 請再參考第10圖， 成於上層的内連線層寸 凸塊接點（bump Pads)6〇也可形 >接著形成防焊護臈62(s〇]der 〇503>A327〇2TWF;chadchou 11 200820410 mask ’也稱作阻焊劑：solder resist)，其厚度可為20μιη， 之後形成阻焊劑開口（SRO: solder resist opening)以暴露 底下之凸塊接點60，球閘陣列錫球(BGAballs)64隨後則 形成於凸塊接點60上。而有關凸塊接點60、防焊護膜 62、和球閘陣列錫球64由於是既有技術，因此在此不予 詳述。具有嵌合之晶粒的封裝基底則隨之透過球閘陣列 錫球64附著於主機板上。 使用合金42作為基板層的優點是其具有介於 ⑩ 4·0Ε./Κ至4.7E-06/K的熱膨脹係數，因此可和晶粒之 熱膨脹係數（介於2.3Ε-06/Κ至4.2Ε-06/Κ)良好匹配。在 熱循環(thermal cycle)製程時，藉基板層20和24施加給 晶粒之應力因此可減到最小，相較之下，傳統的核心層 材料一般係包括雙馬來亞醯胺-三氮雜苯樹脂 (Bismaleimide-Triazine; BT )，其熱膨脹係數為 15E-06/K，因此高應力會被施加到具有BT樹脂核心層之 ⑩ 封裝基底的晶粒上。模擬結果顯示，具有傳統BT樹脂核 心層（厚度約為ΙΟΟμιη)之封裝基底，將導致層壓板 (laminate)，如ABF增層模材料翹曲約125μιη，而本發明 之實施例則只有翹曲約40μπι。此封裝體的可靠度因此獲 得改善。 本發明貫施例另具有其他一些優點，例如由於從封 裝基底中移除了核心層，電子信號繞經内連線層會更有 效率’且内連線層的空間浪費較少。據此，内連線層的 數量可以從傳統封裝基板的8層減少到本發明的5層甚 0503-A32702TWF；chadchou 12 200820410 或3層。整個封裝基板的厚度也據此可減少到例如約26 密爾至30密爾之間。此外，從内連線層的中間部分移除 核心層可以減少封裝體的電感和插入損失（insertion losses) ° 本發明實施例之另一優點在於，由於插塞44直接連 接晶粒3 0，因此不需要防焊劑’晶粒3 0的間距P (請茶 考第10圖）也可以減少。在一實施例中，間距P大約是 120μπι，而在傳統的封裝體中，由於凸塊被用來連接晶粒 和封裝基底，所以最小的間距至少也要140μπι。 雖然本發明已以較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之 精神和範圍内，當可作些許之更動與潤飾，因此本發明 之保護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 第1圖顯示傳統之封裝體，其中内連線層形成於核 心層之兩側。 第2至第10圖顯示本發明較佳實施例之製造過程剖 面圖。 凸塊〜6 ; 核心層〜8 ; 插塞〜12 ; 基板層〜24 ; 【主要元件符號說明】 半導體晶片（晶粒）〜2 ; 封裝基底〜4 ; 球閘陣列錫球〜10 ; 基板層〜20 ; 0503-A32702TWF;chadchou 13 200820410 黏著材料〜22 ; 開口〜26和28 ; 電子元件〜32 ; 開口〜3 8 ; 開口〜42 ; 種晶層〜46 ; 導電圖案〜50 ; 凸塊接點〜60 ; 0 球閘陣列錫球〜64 ; 核心層〜2〇ι、2〇2 ; 晶粒〜30 ; 絕緣層〜34 ; 接觸墊〜40 ; 插塞〜44 ; 乾膜〜48 ; 絕緣層〜52 ; 防焊護膜〜62 ; 間距〜P。 0503-A32702TWF;chadchou 14

Claims (1)

  1. 200820410 十、申請專利範圍： h一種半導體封裝結構，包括： 一第一基板層，其成份包括合金42材料； 一晶粒，附著於該第一基板層之一第一侧面上；及 内連線結構，位於該晶粒上，其中該内連線結構 包括插塞及連接該晶粒之導線。 2·如申請專利範圍第丨項所述之半導體封裝結構， 其更包括球閘陣列焊球，位於該内連線結構之頂表面上 且透過該互連結構連接該晶粒。 3.如申請專利範圍第1項所述之半導 其更包括-第二基板層，該第二基板層成分包括合 1 才^於：第一基板層之第-侧面上，其中該晶粒形 成於该弟二基板層之開口中。 4·_請專利範㈣丨項所狀半導體封裝 ，、更包括額外的電子元件，附著於該第一基板 側面上且連接到該内連線結構。 的弟一 ，1項所述之半導體封裝結構， 八中相連線結構和晶粒間之連接不含凸塊。 6. 如ί請翻_第〗韻叙半導 其中_連線結構包括插細直接連接到該晶粒構 7. 如申請專利範圍第〗項所述之半 其中該内連線結構包括少於6層之内連線層。衣、、、°構， 8. 如申請專利範圍第】項所述之 其申該第一基板層相對於哕第 _封衣結構， 對於及弟一側面之一第二側面不含 〇503-A32702TWF;chadchou 15 200820410 内連線結構。 • σ甲明專利範圍第 其中該第-基板層相對於言 項所述之半導體封裝結構， 第一侧面之一第二侧面不含 10·如申請專利 射該内連線結構不含核1/。所述之半導體封裝結構， 」::：種半導體封裝結構，包括：
    外基板層，其成份包括合金42材料； 一弟二基板声， 上； 板層附者於該第一基板層之一第一侧面 一開口， 一晶粒， 第一侧面上； 位於該第二基板層中； 位於該開π中，謂著於㈣—基板層之
    晶 一第一絕緣層， 複數個第一插塞 粒；及 位於該晶粒及第二基板層上，· ，位於該絕緣層中且實體性接觸 該 該内 連線：：構’位於該第一絕緣層上’其中 弟一絕緣層， 複數個第二插塞及導線，位於該第二絕緣層中，其 中至少有部分之第二插塞及導線連接到該些第一插塞/;、 及 ^ 複數個球閘陣列錫球，位於該内連線結構之上表面。 12·如申請專利範圍第〗i項所述之半導體封裝結 〇503-A32702TWF;chadchou 16 200820410 構，其中該第二基板層成分包括合金42材料。 構，申請專利範圍帛U項所述之半導體封裝結 構，、中该罘一絕緣層包括ABF增層膜材料。 14.如申請專利範圍第u項所述之 ”㈣球問陣列錫球之上表面到該第—基 表面之厚度為少於約45密爾。 一 15·如申請專利範圍帛n項所述之半導體 士 其更包括額外的電子元件，附著 ^ 構 中，_連線結構和第三插塞間之連接不含凸^構，其 6由如中請專·㈣u項所述之半導 中該内，線結構和晶粒間之連接不含凸塊。… 構 構包括少二=體封裝結 18 ·如申凊專利範圍笸 構 J: _哕第一其 項所述之半導體封裝結 -rd弟一基板層相對於一 不含内連線結構。 、^ 彳面之一第二侧面 19.如申請專利範圊 構，其中該第一基板 不含晶粒、 亥弟—側面之一第二側面 20.如申請專利範圍第 構’其令在該球閉陣列踢球㈣第二：二導體封裝結 線結構不含核心層。 /弟基板層之間的内連 0503-A32702TWF;chadchou 17
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