CN102339761A - Method for manufacturing packaged structures - Google Patents
Method for manufacturing packaged structures Download PDFInfo
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- CN102339761A CN102339761A CN2010102283543A CN201010228354A CN102339761A CN 102339761 A CN102339761 A CN 102339761A CN 2010102283543 A CN2010102283543 A CN 2010102283543A CN 201010228354 A CN201010228354 A CN 201010228354A CN 102339761 A CN102339761 A CN 102339761A
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- layer
- base plate
- packaging
- insulating protective
- loading plate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The invention relates to a method for manufacturing packaged structures. The method comprises the following steps of: firstly, cutting a large-area whole-layout package substrate into a plurality of package substrate blocks, wherein each package substrate block comprises a plurality of package substrate units; next, arranging a semiconductor chip on each package substrate unit and fixing and protecting by using a packaging material so as to form a plurality of packaged structure blocks, wherein each packaged structure block comprises a plurality of packaged structure units; and finally cutting the packaged structure blocks into a plurality of packaged structure units. According to the invention, the area of the package substrate blocks is moderate, thus the alignment error for each package substrate unit in each package substrate block in a manufacture process is reduced; and the whole package substrate units in each package substrate block can be subjected to semiconductor chip package once, the manufacture of package substrates and the package of semiconductor chips are integrated, and the process for manufacture is simplified, so that the overall productivity and the percent of pass are enhanced and the overall cost is lowered.
Description
Technical field
The present invention relates to a kind of manufacture method of encapsulating structure, particularly a kind of manufacture method that can improve overall throughput and reduce the encapsulating structure of whole cost.
Background technology
In existing routing engagement type (Wire Bond) semiconductor packaging; The non-acting surface of semiconductor chip connect put on a base plate for packaging; And the acting surface of this semiconductor chip is provided with a plurality of electronic padses; And this base plate for packaging connects the surface of putting this semiconductor chip and has a plurality of wire pads, and through corresponding respectively this electronic pads and the wire pad of electrically connecting of bonding wire, makes this semiconductor chip electrically connect this base plate for packaging.
Existing base plate for packaging is by a core board and be symmetrically formed at the circuit layer reinforced structure of its both sides and form; But because of using core board will cause conductor length and overall structure thickness to increase; And be difficult to satisfy the demand that the electronic product function constantly promotes and volume constantly dwindles; So develop the base plate for packaging that coreless layer (coreless) structure, shorten conductor length and reduction overall structure thickness to meet, reach the trend requirement that adapts to high frequencyization, microminiaturization.
In addition; The manufacture method of existing routing engagement type encapsulating structure is to provide one to accomplish leading portion manufacturing process and had the justifying face substrate body of multilayer line syndeton earlier; Have a plurality of wire pads and insulating protective layer at its outermost layer circuit, and form a plurality of perforates in this insulating protective layer, make respectively this wire pad correspondence of this layer reinforced structure expose to respectively this perforate; And respectively forming surface-treated layer on this wire pad that exposes, and form a justifying face base plate for packaging (panel); Then, this justifying face base plate for packaging is cut into a plurality of base plate for packaging unit (unit) or a plurality of base plate for packaging bar (strip), wherein respectively this base plate for packaging bar comprises a plurality of base plate for packaging unit; At last, be transported to encapsulation factory again and carry out follow-up putting crystalline substance, routing joint, encapsulation and/or cut list steps such as (singulation).
But, after this justifying face base plate for packaging is cut into a plurality of base plate for packaging unit, put crystalline substance, routing joint and encapsulation step again, then because once only can deal with to single base plate for packaging unit, thereby the production capacity reduction, and increase whole cost; Perhaps, after this justifying face base plate for packaging is cut into a plurality of base plate for packaging bars, put crystalline substance, routing joint again, encapsulate and cut single stage,, thereby form the waste of material cost then because the frame that this base plate for packaging bar is kept takies many effective areas.
On the other hand, along with the integral thickness of base plate for packaging is more and more thin, put procedure of processings such as crystalline substance or encapsulation difficulty more for base plate for packaging unit or base plate for packaging bar.
Yet; If earlier justifying face base plate for packaging is not cut into a plurality of base plate for packaging unit or a plurality of base plate for packaging bar; And directly put crystalline substance, routing joint, encapsulation and cut steps such as single with justifying face base plate for packaging, then must purchase bigger board, thereby cause the rising of integral device cost; Moreover the precision of the large tracts of land contraposition of justifying face base plate for packaging is lower, makes final encapsulating structure unit that bigger fabrication error is arranged easily, and then influences the overall acceptability rate.
Therefore, manufacture method how to avoid encapsulating structure of the prior art has the step of more complicated and causes low, and the effective area of the too much substrate of waste and cause problem such as whole cost rising of production capacity, has become the problem of desiring most ardently solution at present.
Summary of the invention
In view of the many disadvantages of above-mentioned prior art, main purpose of the present invention is to provide a kind of manufacture method that can improve overall throughput and reduce the encapsulating structure of whole cost.
For realizing above-mentioned purpose; The present invention discloses a kind of manufacture method of encapsulating structure; Comprise: a paired up and down justifying face base plate for packaging is provided; All form a plurality of wire pads and insulating protective layer on its two relative outermost surfaces, and form a plurality of perforates in this insulating protective layer, so that said wire pad correspondence is exposed to respectively this perforate; Separate this paired up and down justifying face base plate for packaging; And cut this justifying face base plate for packaging, forming a plurality of base plate for packaging blocks, and respectively this base plate for packaging block has opposite first and second surface; Have said wire pad and insulating protective layer at this first surface; And this second surface has a plurality of electric contact mats and dielectric layer, and said electric contact mat is embedded and exposes to this dielectric layer surface, and respectively this base plate for packaging block has and be (the base plate for packaging unit of arranged of m * n); Wherein, m and n are the integer greater than 1; Second loading plate is set on said electric contact mat and dielectric layer; On the insulating protective layer of this base plate for packaging unit respectively, connect and put semiconductor chip; The encapsulating structure block that has a plurality of encapsulating structures unit with formation; And this semiconductor chip has relative acting surface and non-acting surface; Have a plurality of electronic padses on this acting surface, and this non-acting surface is fixedly arranged on this insulating protective layer, and respectively this electronic pads is electrically connected to respectively this wire pad through bonding wire with correspondence; On this insulating protective layer, said bonding wire and said semiconductor chip, form the encapsulation material; Remove this second loading plate; And cut this encapsulating structure block to separate into a plurality of encapsulating structures unit.
According to the manufacture method of above-mentioned encapsulating structure, the manufacturing process of the justifying face base plate for packaging that this is paired up and down can comprise: provide one have relative two the surface first loading plate; On two surfaces of this first loading plate, all form the peel ply of area less than this first loading plate; The surface that does not form this peel ply at this first loading plate forms adhesion layer, so that this adhesion layer is around around this peel ply; On this peel ply and adhesion layer, form metal level; Order forms a plurality of electric contact mats and layer reinforced structure on this metal level; This layer reinforced structure comprises at least one dielectric layer, be formed on line layer on this dielectric layer, and a plurality of conductive blind holes that are formed in this dielectric layer and electrically connect this line layer and electric contact mat, and the outermost line layer of this layer reinforced structure also has said wire pad; And on this layer reinforced structure outermost layer, form this insulating protective layer, and form said perforate in this insulating protective layer, make said wire pad correspondence be exposed to respectively this perforate.Perhaps, the manufacturing process of this paired up and down justifying face base plate for packaging comprises: provide one have relative two the surface first loading plate; On two surfaces of this first loading plate, all form adhesion layer; On this adhesion layer, be sticked comprehensively area less than this first loading plate and all around for this adhesion layer around peel ply; On this peel ply and adhesion layer, form metal level; Order forms a plurality of electric contact mats and layer reinforced structure on this metal level; This layer reinforced structure comprises at least one dielectric layer, be formed on line layer on this dielectric layer, and a plurality of conductive blind holes that are formed in this dielectric layer and electrically connect this line layer and electric contact mat, and the outermost line layer of this layer reinforced structure also has said wire pad; And on this layer reinforced structure outermost layer, form this insulating protective layer, and form said perforate in this insulating protective layer, make said wire pad correspondence be exposed to respectively this perforate.
In addition, in above-mentioned manufacture method, the manufacturing process of said base plate for packaging block can comprise: the edge along this paired up and down justifying face base plate for packaging cuts, and cutting edge is through this peel ply; Remove this first loading plate and peel ply and separate into independently two justifying face base plate for packaging with the justifying face base plate for packaging that this is paired up and down; And cut this justifying face base plate for packaging, and remove this metal level, to form said base plate for packaging block.
According to above-mentioned manufacture method, after removing this second loading plate, also can be included in respectively and form soldered ball on this electric contact mat.
The present invention also discloses the manufacture method of another kind of encapsulating structure; Comprise: a paired up and down justifying face base plate for packaging is provided; All form a plurality of electric contact mats and insulating protective layer on its two relative outermost surfaces; And form a plurality of perforates in this insulating protective layer, make that respectively this electric contact mat correspondence is exposed to respectively this perforate; Separate this paired up and down justifying face base plate for packaging; And cut this justifying face base plate for packaging, forming a plurality of base plate for packaging blocks, have opposite first and second surface at this base plate for packaging block respectively; This first surface has said electric contact mat and insulating protective layer; And this second surface has a plurality of wire pads and dielectric layer, and said wire pad is embedded and exposes to this dielectric layer surface, and respectively this base plate for packaging block has and be (the base plate for packaging unit of arranged of m * n); Wherein, m and n are the integer greater than 1; Second loading plate is set on the insulating protective layer of this base plate for packaging block; On the dielectric layer of this base plate for packaging unit respectively, connect and put semiconductor chip; The encapsulating structure block that has a plurality of encapsulating structures unit with formation; And this semiconductor chip has relative acting surface and non-acting surface; Have a plurality of electronic padses on this acting surface, and this non-acting surface is fixedly arranged on this dielectric layer, and respectively this electronic pads is electrically connected to respectively this wire pad through bonding wire with correspondence; On this dielectric layer, said bonding wire and said semiconductor chip, form the encapsulation material; Remove this second loading plate; And cut this encapsulating structure block to separate into a plurality of encapsulating structures unit.
From the above mentioned, the manufacturing process of this paired up and down justifying face base plate for packaging can comprise: provide one have relative two the surface first loading plate; On two surfaces of this first loading plate, all form the peel ply of area less than this first loading plate; The surface that does not form this peel ply at this first loading plate forms adhesion layer, so that this adhesion layer is around around this peel ply; On this peel ply and adhesion layer, form metal level; Order forms a plurality of wire pads and layer reinforced structure on this metal level; This layer reinforced structure comprises at least one dielectric layer, be formed on line layer on this dielectric layer, and a plurality of conductive blind holes that are formed in this dielectric layer and electrically connect this line layer and wire pad, and the outermost line layer of this layer reinforced structure also has said electric contact mat; And on this layer reinforced structure outermost layer, form this insulating protective layer, and form said perforate in this insulating protective layer, make that respectively this electric contact mat correspondence is exposed to respectively this perforate.Perhaps, the manufacturing process of this paired up and down justifying face base plate for packaging comprises: provide one have relative two the surface first loading plate; On two surfaces of this first loading plate, all form adhesion layer; On this adhesion layer, be sticked comprehensively area less than this first loading plate and all around for this adhesion layer around peel ply; On this peel ply and adhesion layer, form metal level; On this metal level, form a plurality of electric contact mats and layer reinforced structure in regular turn; This layer reinforced structure comprises at least one dielectric layer, be formed on line layer on this dielectric layer, and a plurality of conductive blind holes that are formed in this dielectric layer and electrically connect this line layer and electric contact mat, and the outermost line layer of this layer reinforced structure also has said wire pad; And on this layer reinforced structure outermost layer, form this insulating protective layer, and form said perforate in this insulating protective layer, make said wire pad correspondence be exposed to respectively this perforate.
In addition, according to above-mentioned manufacture method, the manufacturing process of said base plate for packaging block can comprise; Edge along this paired up and down justifying face base plate for packaging cuts, and cutting edge is through this peel ply; Remove this first loading plate and peel ply and separate into independently two justifying face base plate for packaging with the justifying face base plate for packaging that this is paired up and down; And cut this justifying face base plate for packaging, and remove this metal level, to form said base plate for packaging block.
The manufacture method of encapsulating structure from the above mentioned after removing this second loading plate, also can be included in respectively and form soldered ball on this electric contact mat.
By on can know that the manufacture method of encapsulating structure according to the invention is; Earlier justifying face base plate for packaging is cut into a plurality of base plate for packaging blocks, respectively this base plate for packaging block includes a plurality of base plate for packaging unit; Then, on this base plate for packaging unit respectively, connect and put semiconductor chip and fix and protect with the encapsulation material; At last, cut into a plurality of encapsulating structures unit.Compared with prior art; The manufacture method of encapsulating structure according to the invention is integrated base plate for packaging manufacturing and semiconductor die package; Can be once the whole base plate for packaging unit in this base plate for packaging block be respectively carried out semiconductor die package, to simplify processing step and to improve production capacity; Moreover; The area of base plate for packaging block according to the invention is moderate; Can dwindle respectively this base plate for packaging unit bit errors in manufacturing process in this base plate for packaging block respectively, so the manufacture method of encapsulating structure according to the invention has advantages such as higher production capacity and qualification rate.
Description of drawings
Figure 1A to Fig. 1 H is the cross-sectional schematic of first embodiment of the manufacture method of encapsulating structure of the present invention; Wherein, Figure 1A ' is another form of implementation of Figure 1A, and Fig. 1 E ' is the vertical view of Fig. 1 E;
Fig. 2 A to Fig. 2 H is the cross-sectional schematic of second embodiment of the manufacture method of encapsulating structure of the present invention.
[primary clustering symbol description]
20a first loading plate
20b second loading plate
211 peel plies
212 adhesion layers
22 metal levels
23,23 ' electric contact mat
24 layer reinforced structures
241 dielectric layers
242 conductive blind holes
243 line layers
244,244 ' wire pad
25 insulating protective layers
250 perforates
26 surface-treated layers
27 cutting edges
28 semiconductor chips
The 28a acting surface
The non-acting surface of 28b
281 electronic padses
29 bonding wires
30 encapsulation materials
31 soldered balls
The justifying face base plate for packaging that 2a is paired up and down
2a ' justifying face base plate for packaging
2b base plate for packaging block
The 200a first surface
The 200b second surface
The matrix line number of m base plate for packaging block
The matrix columns of n base plate for packaging block
2c base plate for packaging unit
2b ' encapsulating structure block
2c ' encapsulating structure unit
Embodiment
In order further to understand other advantage of the present invention and effect, through particular specific embodiment execution mode of the present invention is described below.
First embodiment
Figure 1A to Fig. 1 H is the cross-sectional schematic of first embodiment of the manufacture method of encapsulating structure of the present invention; Wherein, Figure 1A ' is another form of implementation of Figure 1A, and Fig. 1 E ' is the vertical view of Fig. 1 E.
Shown in Figure 1A; Provide one have relative two the surface the first loading plate 20a; All form the peel ply 211 of area on its two surface less than this first loading plate 20a; And, make this adhesion layer 212 around around this peel ply 211, and on this peel ply 211 and adhesion layer 212, form metal level 22 at the surface formation adhesion layer 212 that this first loading plate 20a does not form this peel ply 211; Wherein, this peel ply 211 can be mould release membrance, and the material of this metal level 22 can be copper, and this metal level 22 can be used as in the plating step crystal seed layer (seed layer) as current conduction path.
Be depicted as another form of implementation of Figure 1A like Figure 1A '; Provide equally one have relative two the surface the first loading plate 20a; All form adhesion layer 212 on its two surface; And on this adhesion layer 212, be sticked comprehensively area less than this first loading plate 20a and all around for this adhesion layer 212 around peel ply 211, and on this peel ply 211 and adhesion layer 212, form metal level 22.Following manufacture method illustrates with Figure 1A.
Shown in Figure 1B; Order forms a plurality of electric contact mats 23 and layer reinforced structure 24 on this metal level 22; This layer reinforced structure 24 comprises at least one dielectric layer 241, be formed on line layer 243 on this dielectric layer 241, and a plurality of conductive blind holes 242 that are formed in this dielectric layer 241 and electrically connect this line layer 243 and electric contact mat 23, and these layer reinforced structure 24 outermost line layers 243 also have a plurality of wire pads 244; Then, on these layer reinforced structure 24 outermost layers, form insulating protective layer 25, and form a plurality of perforates 250 in this insulating protective layer 25, make said wire pad 244 correspondences be exposed to respectively this perforate 250; Then; On said wire pad 244, form surface-treated layer 26; Thereby form paired up and down justifying face base plate for packaging 2a; The material of this surface-treated layer 26 is nickel/gold (Ni/Au), change the nickel palladium soak gold (Electroless Nickel/Electroless Palladium/Immersion Gold, ENEPIG), tin (Sn), silver (Ag) or gold (Au).
Shown in Fig. 1 C, cut along the edge of this paired up and down justifying face base plate for packaging 2a, and cutting edge 27 is through this peel ply 211.
Shown in Fig. 1 D, remove this first loading plate 20a and peel ply 211 and separate into independently two justifying face base plate for packaging 2a ' with the justifying face base plate for packaging 2a that this is paired up and down; If according to the structure shown in Figure 1A ', then remove this first loading plate 20a, peel ply 211 and adhesion layer 212 to separate into independently two justifying face base plate for packaging 2a '.
Shown in Fig. 1 E and 1E ', Fig. 1 E ' is the vertical view of Fig. 1 E; As shown in the figure, cut this justifying face base plate for packaging 2a ', and remove this metal level 22; Forming a plurality of base plate for packaging block 2b, and respectively this base plate for packaging block 2b has opposite first 200a and second surface 200b, and this first surface 200a has said wire pad 244 and insulating protective layer 25; And this second surface 200b has said electric contact mat 23 and dielectric layer 241, and said electric contact mat 23 is embedded and exposes to this dielectric layer 241 surfaces, and respectively this base plate for packaging block 2b has and be (the base plate for packaging unit 2c of arranged of m * n); Wherein, m and n are the integer greater than 1, in the present embodiment; M and n are respectively 6 and 5, but not as limit.
Shown in Fig. 1 F, the second loading plate 20b is set on said electric contact mat 23 and dielectric layer 241.
Shown in Fig. 1 G; On the insulating protective layer 25 of this base plate for packaging unit 2c respectively, connect and put semiconductor chip 28; Have the encapsulating structure block 2b ' of a plurality of encapsulating structures unit 2c ' with formation, and this semiconductor chip 28 have relative acting surface 28a and non-acting surface 28b, has a plurality of electronic padses 281 on this acting surface 28a; And this non-acting surface 28b is fixedly arranged on this insulating protective layer 25, and respectively this electronic pads 281 is electrically connected to respectively this wire pad 244 through bonding wire 29 with correspondence; Then, on this insulating protective layer 25, said bonding wire 29 and said semiconductor chip 28, form encapsulation material 30; Then, remove this second loading plate 20b, and respectively forming soldered ball 31 on this electric contact mat 23; Perhaps, on this electric contact mat 23, do not form soldered ball 31, and directly be used for the electric connection (expression in the accompanying drawing) with Background Grid array packages (Land grid array, be called for short LGA) structure.
Shown in Fig. 1 H, cut this encapsulating structure block 2b ' to separate into a plurality of encapsulating structures unit 2c '.
Second embodiment
Fig. 2 A to Fig. 2 H is the cross-sectional schematic of second embodiment of the manufacture method of encapsulating structure of the present invention.
Shown in Fig. 2 A; Provide one have relative two the surface the first loading plate 20a; All form the peel ply 211 of area on its two surface less than this first loading plate 20a; And, make this adhesion layer 212 around around this peel ply 211, and on this peel ply 211 and adhesion layer 212, form metal level 22 at the surface formation adhesion layer 212 that this first loading plate 20a does not form this peel ply 211; Wherein, this peel ply 211 can be mould release membrance, and the material of this metal level 22 can be copper, and this metal level 22 is as the crystal seed layer of current conduction path in the plating step.Likewise, another form of implementation of Fig. 2 A also can be shown in Figure 1A ', and its details sees also above-mentioned explanation about Figure 1A ', does not give unnecessary details at this.
Shown in Fig. 2 B; Order forms a plurality of wire pads 244 ' and layer reinforced structure 24 on this metal level 22; This layer reinforced structure 24 comprises at least one dielectric layer 241, be formed on line layer 243 on this dielectric layer 241, and a plurality of conductive blind holes 242 that are formed in this dielectric layer 241 and electrically connect this line layer 243 and wire pad 244 ', and these layer reinforced structure 24 outermost line layers 243 also have a plurality of electric contact mats 23 '; Then; On these layer reinforced structure 24 outermost layers, form this insulating protective layer 25; And form a plurality of perforates 250 in this insulating protective layer 25, make that respectively this electric contact mat 23 ' correspondence is exposed to respectively this perforate 250, thereby form paired up and down justifying face base plate for packaging 2a.
Shown in Fig. 2 C, cut along the edge of this paired up and down justifying face base plate for packaging 2a, and cutting edge 27 is through this peel ply 211, to remove this adhesion layer 212.
Shown in Fig. 2 D, remove this first loading plate 20a and peel ply 211 and separate into independently two justifying face base plate for packaging 2a ' with the justifying face base plate for packaging 2a that this is paired up and down.
Shown in Fig. 2 E, cut this justifying face base plate for packaging 2a ', and remove this metal level 22; To form a plurality of base plate for packaging block 2b; And respectively this base plate for packaging block 2b has opposite first 200a and second surface 200b, have said electric contact mat 23 ' and insulating protective layer 25 at this first surface 200a, and this second surface 200b has said wire pad 244 ' and dielectric layer 241; And said wire pad 244 ' is embedded and exposes to this dielectric layer 241 surfaces; And respectively this base plate for packaging block 2b has and is that (the base plate for packaging unit 2c of arranged of m * n), wherein, m and n are the integer greater than 1.
Shown in Fig. 2 F, the second loading plate 20b is set on the insulating protective layer 25 of this base plate for packaging block 2b.
Shown in Fig. 2 G; Go up formation surface-treated layer 26 at said wire pad 244 '; The material of this surface-treated layer 26 is nickel/gold (Ni/Au), change the nickel palladium soak gold (Electroless Nickel/ElectrolessPalladium/Immersion Gold, ENEPIG), tin (Sn), silver (Ag) or gold (Au); Also on the dielectric layer 241 of this base plate for packaging unit 2c respectively, connect and put semiconductor chip 28; The encapsulating structure block 2b ' that has a plurality of encapsulating structures unit 2c ' with formation; And this semiconductor chip 28 has relative acting surface 28a and non-acting surface 28b; Have a plurality of electronic padses 281 on this acting surface 28a, and this non-acting surface 28b is fixedly arranged on this dielectric layer 241, and respectively this electronic pads 281 is electrically connected to respectively this wire pad 244 ' through bonding wire 29 with correspondence; Then, on this dielectric layer 241, said bonding wire 29 and said semiconductor chip 28, form encapsulation material 30; Then, remove this second loading plate 20b, and respectively forming soldered ball 31 on this electric contact mat 23 '; Perhaps, do not form soldered ball 31 on this electric contact mat 23 ', and directly be used for the electric connection (not representing) with Background Grid array packages (Land grid array, be called for short LGA) structure with accompanying drawing.
Shown in Fig. 2 H, cut this encapsulating structure block 2b ' to separate into a plurality of encapsulating structures unit 2c '.
Another form of implementation of the present invention; Also can earlier paired up and down justifying face base plate for packaging be cut into a plurality of paired up and down base plate for packaging blocks; Respectively this paired up and down base plate for packaging block separates into independently two base plate for packaging blocks again; And other step before is said, does not give unnecessary details at this.
In sum, the manufacture method of encapsulating structure of the present invention cuts into a plurality of base plate for packaging blocks with justifying face base plate for packaging earlier, and respectively this base plate for packaging block includes a plurality of base plate for packaging unit; Then, on this base plate for packaging unit respectively, connect and put semiconductor chip and fix and protect with the encapsulation material; At last, cut into a plurality of encapsulating structures unit.Compared with prior art; The manufacture method of encapsulating structure provided by the invention is integrated base plate for packaging manufacturing and semiconductor die package; Can be once the whole base plate for packaging unit in this base plate for packaging block be respectively carried out semiconductor die package, to simplify manufacturing process and to improve production capacity; Moreover; The area of base plate for packaging block of the present invention is moderate; Can dwindle respectively this base plate for packaging unit bit errors in manufacturing process in this base plate for packaging block respectively, so the manufacture method of encapsulating structure according to the invention has advantages such as higher production capacity and qualification rate.
Claims (12)
1. the manufacture method of an encapsulating structure is characterized in that, this manufacture method comprises:
One paired up and down justifying face base plate for packaging is provided, all forms a plurality of wire pads and insulating protective layer on its two relative outermost surfaces, and form a plurality of perforates in this insulating protective layer, make said wire pad correspondence be exposed to respectively this perforate;
Separate this paired up and down justifying face base plate for packaging; And cut this justifying face base plate for packaging, forming a plurality of base plate for packaging blocks, and respectively this base plate for packaging block has opposite first and second surface; Have said wire pad and insulating protective layer at this first surface; And this second surface has a plurality of electric contact mats and dielectric layer, and said electric contact mat is embedded and exposes to this dielectric layer surface, and respectively this base plate for packaging block has and be (the base plate for packaging unit of arranged of m * n); Wherein, m and n are the integer greater than 1;
Second loading plate is set on said electric contact mat and dielectric layer;
On the insulating protective layer of this base plate for packaging unit respectively, connect and put semiconductor chip; The encapsulating structure block that has a plurality of encapsulating structures unit with formation; And this semiconductor chip has relative acting surface and non-acting surface; Have a plurality of electronic padses on this acting surface, and this non-acting surface is fixedly arranged on this insulating protective layer, and respectively this electronic pads is electrically connected to respectively this wire pad through bonding wire with correspondence;
On this insulating protective layer, said bonding wire and said semiconductor chip, form the encapsulation material;
Remove this second loading plate; And
Cut this encapsulating structure block to separate into a plurality of encapsulating structures unit.
2. the manufacture method of encapsulating structure according to claim 1 is characterized in that, the manufacturing process of this upper and lower paired justifying face base plate for packaging comprises:
Provide one have relative two the surface first loading plate;
On two surfaces of this first loading plate, all form the peel ply of area less than this first loading plate;
The surface that does not form this peel ply at this first loading plate forms adhesion layer, so that this adhesion layer is around around this peel ply;
On this peel ply and adhesion layer, form metal level;
Order forms a plurality of electric contact mats and layer reinforced structure on this metal level; This layer reinforced structure comprises at least one dielectric layer, be formed on line layer on this dielectric layer, and a plurality of conductive blind holes that are formed in this dielectric layer and electrically connect this line layer and electric contact mat, and the outermost line layer of this layer reinforced structure also has said wire pad; And
On this layer reinforced structure outermost layer, form this insulating protective layer, and form said perforate in this insulating protective layer, make said wire pad correspondence be exposed to respectively this perforate.
3. the manufacture method of encapsulating structure according to claim 1 is characterized in that, the manufacturing process of this upper and lower paired justifying face base plate for packaging comprises:
Provide one have relative two the surface first loading plate;
On two surfaces of this first loading plate, all form adhesion layer;
On this adhesion layer, be sticked comprehensively area less than this first loading plate and all around for this adhesion layer around peel ply;
On this peel ply and adhesion layer, form metal level;
Order forms a plurality of electric contact mats and layer reinforced structure on this metal level; This layer reinforced structure comprises at least one dielectric layer, be formed at line layer on this dielectric layer, and a plurality of conductive blind holes that are formed in this dielectric layer and electrically connect this line layer and electric contact mat, and the outermost line layer of this layer reinforced structure also has said wire pad; And
On this layer reinforced structure outermost layer, form this insulating protective layer, and form said perforate in this insulating protective layer, make said wire pad correspondence be exposed to respectively this perforate.
4. according to the manufacture method of claim 2 or 3 described encapsulating structures, it is characterized in that the manufacturing process of said base plate for packaging block comprises:
Edge along this paired up and down justifying face base plate for packaging cuts, and cutting edge is through this peel ply;
Remove this first loading plate and peel ply and separate into independently two justifying face base plate for packaging with the justifying face base plate for packaging that this is paired up and down; And
Cut this justifying face base plate for packaging, and remove this metal level, to form said base plate for packaging block.
5. the manufacture method of encapsulating structure according to claim 1 is characterized in that, also is included on the said wire pad and forms surface-treated layer.
6. the manufacture method of encapsulating structure according to claim 1 is characterized in that, after removing this second loading plate, also is included in respectively and forms soldered ball on this electric contact mat.
7. the manufacture method of an encapsulating structure is characterized in that, this manufacture method comprises:
One paired up and down justifying face base plate for packaging is provided, all forms a plurality of electric contact mats and insulating protective layer on its two relative outermost surfaces, and form a plurality of perforates in this insulating protective layer, make that respectively this electric contact mat correspondence is exposed to respectively this perforate;
Separate this paired up and down justifying face base plate for packaging; And cut this justifying face base plate for packaging, forming a plurality of base plate for packaging blocks, have opposite first and second surface at this base plate for packaging block respectively; This first surface has said electric contact mat and insulating protective layer; And this second surface has a plurality of wire pads and dielectric layer, and said wire pad is embedded and exposes to this dielectric layer surface, and respectively this base plate for packaging block has and be (the base plate for packaging unit of arranged of m * n); Wherein, m and n are the integer greater than 1;
Second loading plate is set on the insulating protective layer of this base plate for packaging block;
On the dielectric layer of this base plate for packaging unit respectively, connect and put semiconductor chip; The encapsulating structure block that has a plurality of encapsulating structures unit with formation; And this semiconductor chip has relative acting surface and non-acting surface; Have a plurality of electronic padses on this acting surface, and this non-acting surface is fixedly arranged on this dielectric layer, and respectively this electronic pads is electrically connected to respectively this wire pad through bonding wire with correspondence;
On this dielectric layer, said bonding wire and said semiconductor chip, form the encapsulation material;
Remove this second loading plate; And
Cut this encapsulating structure block to separate into a plurality of encapsulating structures unit.
8. the manufacture method of encapsulating structure according to claim 7 is characterized in that, the manufacturing process of this upper and lower paired justifying face base plate for packaging comprises:
Provide one have relative two the surface first loading plate;
On two surfaces of this first loading plate, all form the peel ply of area less than this first loading plate;
The surface that does not form this peel ply at this first loading plate forms adhesion layer, so that this adhesion layer is around around this peel ply;
On this peel ply and adhesion layer, form metal level;
Order forms a plurality of wire pads and layer reinforced structure on this metal level; This layer reinforced structure comprises at least one dielectric layer, be formed on line layer on this dielectric layer, and a plurality of conductive blind holes that are formed in this dielectric layer and electrically connect this line layer and wire pad, and the outermost line layer of this layer reinforced structure also has said electric contact mat; And
On this layer reinforced structure outermost layer, form this insulating protective layer, and form said perforate in this insulating protective layer, make that respectively this electric contact mat correspondence is exposed to respectively this perforate.
9. the manufacture method of encapsulating structure according to claim 7 is characterized in that, the manufacturing process of this upper and lower paired justifying face base plate for packaging comprises:
Provide one have relative two the surface first loading plate;
On two surfaces of this first loading plate, all form adhesion layer;
On this adhesion layer, be sticked comprehensively area less than this first loading plate and all around for this adhesion layer around peel ply;
On this peel ply and adhesion layer, form metal level;
Order forms a plurality of electric contact mats and layer reinforced structure on this metal level; This layer reinforced structure comprises at least one dielectric layer, be formed on line layer on this dielectric layer, and a plurality of conductive blind holes that are formed in this dielectric layer and electrically connect this line layer and electric contact mat, and the outermost line layer of this layer reinforced structure also has said wire pad; And
On this layer reinforced structure outermost layer, form this insulating protective layer, and form said perforate in this insulating protective layer, make said wire pad correspondence be exposed to respectively this perforate.
10. according to Claim 8 or the manufacture method of 9 described encapsulating structures, it is characterized in that the manufacturing process of said base plate for packaging block comprises:
Edge along this paired up and down justifying face base plate for packaging cuts, and cutting edge is through this peel ply;
Remove this first loading plate and peel ply and separate into independently two justifying face base plate for packaging with the justifying face base plate for packaging that this is paired up and down; And
Cut this justifying face base plate for packaging, and remove this metal level, to form said base plate for packaging block.
11. the manufacture method of encapsulating structure according to claim 7 is characterized in that, also is included on the said wire pad and forms surface-treated layer.
12. the manufacture method of encapsulating structure according to claim 7 is characterized in that, after removing this second loading plate, also is included in respectively and forms soldered ball on this electric contact mat.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010228354.3A CN102339761B (en) | 2010-07-14 | 2010-07-14 | Method for manufacturing packaged structures |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010228354.3A CN102339761B (en) | 2010-07-14 | 2010-07-14 | Method for manufacturing packaged structures |
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| Publication Number | Publication Date |
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| CN102339761A true CN102339761A (en) | 2012-02-01 |
| CN102339761B CN102339761B (en) | 2014-05-07 |
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| CN201010228354.3A Expired - Fee Related CN102339761B (en) | 2010-07-14 | 2010-07-14 | Method for manufacturing packaged structures |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111238694A (en) * | 2020-02-06 | 2020-06-05 | 腾讯科技（深圳）有限公司 | Touch sensor, touch event detection method and device and intelligent robot |
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|---|---|---|---|---|
| CN1956635A (en) * | 2005-10-27 | 2007-05-02 | 全懋精密科技股份有限公司 | Structure of thin wire of multi-dielectric layer circuit board and its manufacturing method |
| CN1972554A (en) * | 2005-11-25 | 2007-05-30 | 全懋精密科技股份有限公司 | Thin circuit board structure |
| CN1980541A (en) * | 2005-12-07 | 2007-06-13 | 新光电气工业株式会社 | Method of manufacturing wiring substrate and method of manufacturing electronic component mounting structure |
| CN101471328A (en) * | 2007-12-25 | 2009-07-01 | 力成科技股份有限公司 | Substrate panel |
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2010
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1956635A (en) * | 2005-10-27 | 2007-05-02 | 全懋精密科技股份有限公司 | Structure of thin wire of multi-dielectric layer circuit board and its manufacturing method |
| CN1972554A (en) * | 2005-11-25 | 2007-05-30 | 全懋精密科技股份有限公司 | Thin circuit board structure |
| CN1980541A (en) * | 2005-12-07 | 2007-06-13 | 新光电气工业株式会社 | Method of manufacturing wiring substrate and method of manufacturing electronic component mounting structure |
| JP2007158174A (en) * | 2005-12-07 | 2007-06-21 | Shinko Electric Ind Co Ltd | Process for producing wiring board and process for producing electronic component mounting structure |
| CN101471328A (en) * | 2007-12-25 | 2009-07-01 | 力成科技股份有限公司 | Substrate panel |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111238694A (en) * | 2020-02-06 | 2020-06-05 | 腾讯科技（深圳）有限公司 | Touch sensor, touch event detection method and device and intelligent robot |
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| CN102339761B (en) | 2014-05-07 |
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