KR101205464B1 - Method for manufacturing a printed circuit board - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board manufacturing technology. In particular, three layers are formed on both sides to improve a board warpage problem, and a laser via is formed to reduce costs. The present invention, unlike the prior art, using a carrier having copper foil foil formed on both sides of the temporary adhesive without using an inner layer core as a starting material, and then forming a copper foil again, forming an inner layer circuit, and forming a copper foil again, and then separating. The laser via is formed on both sides and the through-holes are manufactured to manufacture the multilayer board, and thus the substrate may be manufactured in a thin plate, and there are advantages in that two printed circuit boards may be made in one process.

Description

Printed circuit board manufacturing method {METHOD FOR MANUFACTURING A PRINTED CIRCUIT BOARD}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer printed circuit board manufacturing technology, and more particularly, to a printed circuit board manufacturing method for preventing a problem of bending of a substrate during a thermocompression bonding process. The present invention fundamentally solves the problem of bending the substrate while at the same time converting the symmetrical four-layer substrate manufacturing process used inevitably in order to solve the problem of bending the substrate conventionally, and at the same time The present invention relates to a new concept of a printed circuit board manufacturing method capable of omitting expensive process steps such as a through hole manufacturing process and a copper plating process, which are essential processes.

1A to 1F are views illustrating a technique of manufacturing a three-layer printed circuit board according to the prior art. Referring to FIG. 1A, a three-layer printed circuit board manufacturing method starts with a structure in which an insulating layer 10 is disposed in the center and copper foils 20a and 20b are coated on both sides, such as a copper cladded layer (CCL). CCL is a structure in which copper foil is coated on both surfaces by using the resin of the state hardened at the center as the insulating layer 10.

Referring to FIG. 1B, a process of exposing, developing, etching, and the like is performed on the copper foil 20a on one surface to form a copper foil circuit pattern. Subsequently, referring to FIG. 1C, a thermocompression lamination is performed by stacking the insulating layer 30 and the copper foil 40 on the structure on which the copper foil circuit is formed. Here, as the insulating layer 30, a resin in a semi-cured state such as a prepreg is used. As a result, the copper foil 20b of the lower end of a structure forms a 1st layer, the copper foil 20a of the center forms a 2nd layer, and the copper foil 40 of an upper end forms a 3rd layer.

Next, referring to FIG. 1D, a laser drill process is performed to form vias 50 for connecting the first, second, and third layers of copper foils 20b, 20a, and 40 to each other. Subsequently, as shown in FIG. 1E, plating is performed to form a plating layer 60 that connects the first, second, and third copper foils 20b, 20a, and 40 to each other. Finally, as shown in FIG. 1F, a process of exposure, development, etching, and the like is performed to form a copper foil circuit pattern.

However, the three-layer substrate manufacturing technique according to the prior art shown in Figures 1a to 1f is a resin layer cured resin layer 10 of the CCL structure laminated for thermocompression, the insulating layer 30 laminated on the top Since the semi-curable resin is a problem of bending the substrate during the lamination process due to the difference in stress.

Thus, in order to solve the problem of a board | substrate bending, the 4-layer board | substrate manufacturing method is used. Build-up printed circuit board manufacturing technology used in the printed circuit board manufacturing industry. There is a technology of the Republic of Korea Patent No. 462,835 of Electronics Corporation.

2A to 2F are views showing an alib method as a prior art. First, via holes 11 are formed in the insulating material 10 constituting each layer of the printed circuit board using a laser drilling technique, and then the via holes are filled with the metallic paste 12. Subsequently, the copper foil 13 is laminated on the surface of the insulating material by a hot press method, and the circuit 14 is constituted by photolithography to complete one layer. After each layer is manufactured in this manner, the positions thereof are aligned and laminated using a hot press again to complete one substrate as shown in FIG. 2F.

Figure 3a to 3f is a view showing the NMBI manufacturing method according to the prior art. As shown in Fig. 3A, after the inner core board 100 is fabricated, the third layer material is etched to produce the bumps 21 as in Fig. 3C. Subsequently, the outer layer substrate 22 is manufactured by laminating the prepreg PREPREG of the B stage. Referring to FIG. 3E, the inner core 100 and the outer substrate 22 are aligned and hot pressed to cure to a C stage. Finally, as shown in FIG. 3F, the copper foil is corroded to the outer layer to form a circuit.

4A to 4I illustrate a bump via substrate manufacturing method disclosed in Korean Patent No. 462,835 as a prior art.

The technique of Patent No. 462,835 prepares the inner core 130, then proceeds with electroless copper plating 131, laminating the dry film 132 and pattern forming. Subsequently, referring to FIG. 4D, electrolytic copper plating 133 is performed on the exposed electroless copper plating on the dry film 132. Thereafter, when the dry film is removed, it is formed as shown in FIG. 4E. On the other hand, if copper plating bumps are formed behind the interlayer vias, the build-up resin 134 is coated on both sides and the surface is scrubbed (see FIG. 4G). The copper 135 is then plated and imaged to form the copper foil circuit 136.

However, since the prior arts described above with reference to FIGS. 2, 3, and 4 all depend on a method of connecting bumps using an inner layer core substrate, it is not easy to manufacture thin sheet metals, which are required by electronic products recently. There is a disadvantage. Moreover, there is a disadvantage in that the copper plating of the inner layer has to be carried out after the expensive through-hole drilling process and subsequent copper plating.

Accordingly, it is a first object of the present invention to provide a method of manufacturing a printed circuit board, which eliminates warpage of the substrate.

A second object of the present invention is to provide a method for manufacturing a printed circuit board in which a costly through-hole drilling process and a plating process are omitted in addition to the first object.

A third object of the present invention is to provide a printed circuit board manufacturing method capable of making the thickness of a substrate thin in addition to the first object.

The present invention starts the process by placing an adhesive film to bond an insulating layer such as prepreg and copper foil to produce a dummy carrier. Prepreg and copper foil are laminated on both surfaces of the dummy carrier formed in the order of copper foil / adhesive film / prepreg / adhesive film / copper foil and thermocompression bonding. Subsequently, the surface copper foil is selectively etched to form a copper foil circuit, and the prepreg and copper foil are further laminated and thermocompressed. Then, the adhesive film is peeled off and separated from the dummy carrier into two upper and lower substrates.

The present invention improves the problem that the substrate is bent due to the difference in thermal expansion during the thermocompression process by configuring the three-layer substrate on both sides of the dummy carrier, and unlike the conventional four-layer substrate method, by omitting the through-hole drilling process and subsequent plating process Cost reduction can be achieved. The present invention, unlike the prior art, by using a dummy carrier formed by bonding the copper foil to the prepreg as a temporary adhesive film without using an inner layer core, it is possible to perform a low cost laser via process on both sides In addition, since the thermal expansion stress is canceled on both sides of the dummy carrier, the substrate can be prevented from being bent, and two printed circuit boards can be simultaneously made in one process.

1A to 1F illustrate a technique for manufacturing a three-layer printed circuit board according to the prior art.
2A to 2F are views showing an alib method as a prior art.
3a to 3f are views showing the NMBI manufacturing method according to the prior art.
4A to 4I illustrate a bump via substrate manufacturing method disclosed in Korean Patent No. 462,835 as a prior art.
5A to 5H illustrate a method of manufacturing a printed circuit board according to the present invention.
6 is a view showing the degree of warpage of the substrate produced according to the prior art and the present invention.

Hereinafter, a method of manufacturing a printed circuit board according to the present invention will be described in detail with reference to FIGS. 5 and 6.

The present invention is characterized by starting the process with a low cost prepreg (PREPREG) as a starting material, without using a CCL and an inner layer core as starting materials. Referring to FIG. 5A, adhesive films 310a and 310b are attached to both surfaces of the first insulating layer 300, and the first copper foils 400a and 400b are compressed on the adhesive films 310a and 310b. . As a preferred embodiment of the present invention, the adhesive films 310a and 310b may use an adhesive film made of a nickel compound having a particle size of 20 to 30 nm. As a preferred embodiment of the present invention, the thickness of the adhesive film can be produced in the range of 18 ~ 32 ㎛, when applying a force of about 5 ~ 30 N / m adhesion by placing the adhesive film on the first insulating layer 300 It is possible to peel off the copper foils 400a and 400b. In a preferred embodiment of the present invention, the first insulating layer 300 may be a resin of B stage, that is, a prepreg, and the first copper foils 400a and 400b may be copper foils used throughout the art. ) Can be used. The thickness of the copper foil can be applied within the range of 2-3 μm. As a result, the starting material of the present invention uses a structure of copper foil 400a / adhesive film 310a / insulation layer 300 / adhesive film 310b / copper foil 400b instead of the expensive CCL inner core of the prior art. This will be referred to as a dummy carrier.

Here, the adhesive films 310a and 310b are layers for bonding the first copper foils 400a and 400b to the first insulating layer 300, and are made of nickel compounds having a particle size of 20 to 30 nm. film) can be used and does not denature under hot press laminate conditions. As a result, the copper foils 400a and 400b adhered to the first insulating layer 300 by the adhesive force of the adhesive films 310a and 310b are easily peeled off by applying a force of about 5 to 30 N / m. ), The first copper foils 400a and 400b can be easily separated from the first insulating layer 300.

Subsequently, referring to FIG. 5B, the second insulating layers 410a and 410b and the second copper foils 500a and 500b are laminated and thermally compressed to perform lamination. In the second insulating layers 410a and 410b according to the present invention, a resin of a B stage such as a prepreg may be used, and a copper foil may be used as the second copper foils 500a and 500b.

Referring to FIG. 5C, a copper foil circuit pattern is formed by selectively removing the second copper foils 500a and 500b on the surface by performing photographic processes such as exposure, development, and etching. At this time, since the first insulating layer 300 and the second insulating layers 410a and 410b both use the same prepreg, and the structure is also a symmetrical structure, stresses cancel each other during thermal expansion so that the substrate is not bent.

Subsequently, referring to FIG. 5D, the third insulating layers 510a and 510b and the third copper foils 600a and 600b are laminated and thermally compressed to perform lamination. As the third insulating layers 510a and 510b according to the present invention, a resin of a B stage such as a prepreg may be used, and a copper foil may be used as the third copper foils 600a and 600b. As a result, referring to FIG. 5D, it can be seen that two substrate structures are formed up and down about the dummy carrier. Then, the adhesive film of the dummy carrier is peeled off to separate the upper and lower structure substrates into two.

5E is a view showing a state in which the adhesive film of the dummy carrier is peeled off and separated into two substrates. Next, referring to FIG. 5F, the first copper foil 400a is the first layer, the second copper foil 500a is the second layer, and the third copper foil 600a is the third layer, and the insulating layer 700 is interposed therebetween. The board | substrate currently formed is shown, and the interlayer connection is advanced by forming the via 66 in the desired part by performing a laser drill. Referring to FIG. 5G, plating is performed after fabricating a laser via to proceed with interlayer connection. Subsequently, referring to FIG. 5H, the copper foil circuit on the surface is selectively etched, that is, the first layer and the third layer copper foil are selectively etched.

6 is a view showing the degree of warpage of the substrate produced according to the prior art and the present invention. Referring to FIG. 6, in the case of the prior art on the left side, a stress due to a difference in thermal expansion between the prepreg and the insulating layer of the CCL is applied, thereby showing that the substrate is bent a lot. On the other hand, the right picture of Fig. 6 is applied to the technique according to the present invention, it can be seen that the degree of warpage of the substrate due to thermal expansion is insignificant because it applies a double-sided substrate technology that is vertically symmetrical, and the insulating layer uses the same prepreg in common. .

The foregoing is a rather broad improvement of the features and technical advantages of the present invention to better understand the claims of the invention which will be described later. Additional features and advantages constituting the claims of the present invention will be described below. It should be appreciated by those skilled in the art that the disclosed concepts and specific embodiments of the invention can be used immediately as a basis for designing or modifying other structures to accomplish the invention and similar purposes.

In addition, the inventive concepts and embodiments disclosed herein may be used by those skilled in the art as a basis for modifying or designing other structures to accomplish the same purpose of the present invention. It will be apparent to those skilled in the art that various modifications, substitutions and alterations can be made hereto without departing from the spirit or scope of the invention as defined in the appended claims.

As described above, the present invention can prevent the problem of bending the substrate due to the difference in thermal expansion during the thermocompression bonding process by configuring the three-layer substrate on both sides of the dummy carrier, and unlike the conventional four-layer substrate method Cost reduction can be achieved by eliminating the subsequent plating step.

The present invention, unlike the prior art, by using a dummy carrier formed with copper foil on both sides of the temporary adhesive film, without using an inner core, it is possible to perform a low-cost laser via process on both sides, the thermal expansion stress on both sides of the dummy carrier The offset prevents the substrate from bending and has the advantage of making two printed circuit boards at the same time in a single process.

66: Via
300: first insulating layer
310a, 310b: adhesive film
400a, 400b: 1st copper foil
410a, 410b: second insulating layer
500a, 500b: 2nd copper foil
510a, 510b: third insulating layer
600a, 600b: 3rd copper foil
700: insulation layer

Claims (3)

In the method for manufacturing a three-layer printed circuit board composed of a first copper foil, a second copper foil, a third copper foil,
(a) Applying an adhesive film on both surfaces of the first insulating layer, and forming a first copper foil that can be peeled off on the adhesive film, so that the first copper foil / adhesive film / first insulating layer / adhesive film / first copper foil Forming dummy carriers stacked in order;
(b) sequentially laminating a second insulating layer and a second copper foil on the first copper foils on each of both surfaces of the dummy carrier, and performing thermal compression lamination;
(c) selectively etching each of the second copper foils formed on both surfaces of the dummy carrier according to the selected circuit pattern to form a copper foil circuit pattern;
(d) laminating a third insulating layer and a third copper foil in sequence on each of the second copper foils formed on both surfaces of the dummy carrier, and thermally compressing the laminate;
(e) separating the resulting structure of step (d) into two upper and lower structures by peeling the first copper foil bonded with the adhesive film from the first insulating layer;
(f) drilling the first copper foil or the third copper foil constituting both surfaces of the structure separated in step (e) to form a hole, whereby the first copper foil and the second copper foil, or the second copper foil and the second copper foil Forming vias for connecting the three copper foils or the first copper foil and the third copper foil to each other;
(g) plating to fill vias and perform interlayer connection; And
(h) forming copper foil circuits on both surfaces of the structure by selectively etching the conductor layer formed on the surface of the structure by the plating of step (g);
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