CN104254191B - Centreless layer package substrate and preparation method thereof - Google Patents
Centreless layer package substrate and preparation method thereof Download PDFInfo
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- CN104254191B CN104254191B CN201310265770.4A CN201310265770A CN104254191B CN 104254191 B CN104254191 B CN 104254191B CN 201310265770 A CN201310265770 A CN 201310265770A CN 104254191 B CN104254191 B CN 104254191B
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- layer
- copper foil
- conducting wire
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- external conducting
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- 239000000758 substrate Substances 0.000 title claims abstract description 89
- 238000002360 preparation method Methods 0.000 title claims abstract description 18
- 239000010410 layer Substances 0.000 claims description 160
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 92
- 239000011889 copper foil Substances 0.000 claims description 82
- 239000011241 protective layer Substances 0.000 claims description 14
- 238000003466 welding Methods 0.000 claims description 14
- 238000012545 processing Methods 0.000 claims description 11
- 238000003825 pressing Methods 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
- 229910052802 copper Inorganic materials 0.000 description 10
- 239000010949 copper Substances 0.000 description 10
- 238000000034 method Methods 0.000 description 10
- 238000009713 electroplating Methods 0.000 description 7
- 229910000906 Bronze Inorganic materials 0.000 description 2
- 239000010974 bronze Substances 0.000 description 2
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 2
- 238000005553 drilling Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 239000000654 additive Substances 0.000 description 1
- 239000012792 core layer Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
The present invention relates to a kind of centreless layer package substrate, it includes dielectric layer, inner layer conductive line pattern, the first external conducting wire figure and the second external conducting wire figure.The inner layer conductive line pattern is embedded in the dielectric layer.The first external conducting wire figure and the second external conducting wire figure are located at the opposite sides of the dielectric layer respectively.The inner layer conductive line pattern, the first external conducting wire figure and the second external conducting wire figure are electrical connected by the conductive through hole in the dielectric layer.The invention further relates to a kind of preparation method of centreless layer package substrate.
Description
Technical field
There is centreless layer package substrate and its making side the present invention relates to circuit board making technical field, more particularly to one kind
Method.
Background technology
As electronic product is toward miniaturization, the development in high speed direction, for carrying the package substrate of chip also from one side
Package substrate（I.e. one side has the substrate of conducting wire）, double-sided packaging substrate（The i.e. two-sided substrate with conducting wire）It is past many
Layer package substrate（There is the substrate of multilayer conductive circuit）Direction is developed.With sandwich layer（core）Layer multilayer packaging substrate have
More layout area, higher interconnection density, thus be widely used.However, just because of the presence of sandwich layer so that tool
There is the package substrate thickness of sandwich layer thicker.
The content of the invention
In view of this, it is necessary to which a kind of centreless layer package substrate solved the above problems and preparation method thereof is provided, with
Reduce the thickness of centreless layer package substrate.
A kind of centreless layer package substrate, it includes dielectric layer, inner layer conductive line pattern, the first external conducting wire figure
And the second external conducting wire figure.The inner layer conductive line pattern is embedded in the dielectric layer.First outer layer is conductive
Line pattern and the second external conducting wire figure are located at the opposite sides of the dielectric layer respectively.The inner layer conductive line map
Shape, the first external conducting wire figure and the second external conducting wire figure pass through the electrical phase of conductive through hole in the dielectric layer
Even.
A kind of preparation method of centreless layer package substrate, it includes：A loading plate is provided, the loading plate includes relative
First surface and second surface, overlap first copper foil, first glue successively on the first surface of the loading plate
Piece and second copper foil, overlap another first copper foil, another first film and another successively on the second surface
On individual second copper foil, and the second copper foil, the loading plate and the second surface described in one step press on first surface
Two copper foils, to obtain first solderless substrate, first solderless substrate includes a processing district and around the processing district
The first garbage area；Each second copper foil is made to form inner layer conductive line pattern；In each inner layer conductive circuit
Second film and the 3rd copper foil are overlapped on figure successively, and it is described on the upside of the first solderless substrate described in one step press
The second film and the 3rd copper foil on the downside of second film and the 3rd copper foil, first solderless substrate and the first solderless substrate, are obtained
To the second solderless substrate, in second solderless substrate, the first film and the second film on the upside of the first surface are total to
A dielectric layer is collectively formed with the first film and the second film constituted on the downside of a dielectric layer, the first surface；Remove
First garbage area, and the loading plate is removed, two circuit substrates being separated from each other, each circuit substrate is respectively provided with
Product zone and the second garbage area around the product zone, each circuit substrate is including described in a dielectric layer, one
First copper foil, the 3rd copper foil and an inner layer conductive line pattern, first copper foil and the 3rd copper foil point
Not Wei Yu the dielectric layer opposite sides, the inner layer conductive line pattern is embedded in the dielectric layer；In the circuit base
Multiple through holes are formed in the product zone of plate, each through hole runs through the circuit substrate, and each through hole is made led
Electric through-hole, the conductive through hole is electrically connected with first copper foil, inner layer conductive line pattern and the 3rd copper foil；In the dielectric
Layer forms the first external conducting wire figure on the surface of first copper foil, in the dielectric layer close to the 3rd bronze medal
The second external conducting wire figure, the first external conducting wire figure, the second external conducting wire are formed on the surface of paper tinsel
Figure and inner layer conductive line pattern are electrical connected by the conductive through hole；And second garbage area is removed, obtain nothing
Sandwich layer package substrate.
In centreless layer package substrate that the technical program is provided and preparation method thereof, the inner layer conductive line pattern is embedded in
In the dielectric layer, the first external conducting wire figure and the second external conducting wire figure are located at the dielectric layer respectively
Opposite sides, the inner layer conductive line pattern, the first external conducting wire figure and the second external conducting wire figure are logical
The conductive through hole crossed in the dielectric layer is electrical connected, compared with prior art, in the centreless layer package substrate in the technical program
There is no sandwich layer, thickness is substantially reduced.
Brief description of the drawings
Fig. 1 is the sectional view for the first solderless substrate with loading plate that the technical program embodiment is provided.
Fig. 2 is the section formed in the first garbage area of the first solderless substrate shown in Fig. 1 after multiple first tooling holes
Schematic diagram.
Fig. 3 is that the section that the second copper foil in the first solderless substrate in Fig. 2 is made after inner layer conductive line pattern shows
It is intended to.
Fig. 4 be in figure 3 overlap second film and the 3rd copper foil successively on each inner layer conductive line pattern
And the diagrammatic cross-section of the second solderless substrate formed after pressing.
Fig. 5 is to remove the diagrammatic cross-section after two circuit substrates that the loading plate in Fig. 4 is separated from each other.
Fig. 6 is that multiple second tooling holes are formed in the second garbage area of the circuit substrate shown in Fig. 5, in the circuit base
The diagrammatic cross-section formed in the product zone of plate after multiple through holes.
Fig. 7 is that each through hole in Fig. 6 is made into the diagrammatic cross-section after conductive through hole.
Fig. 8 is that the first copper foil and the 3rd copper foil in Fig. 7 are respectively prepared outside the first external conducting wire figure and second
Diagrammatic cross-section after layer conductive circuit pattern.
Fig. 9 is on the first external conducting wire figure in fig. 8, on the second external conducting wire figure and each conductive
The diagrammatic cross-section formed in through hole after welding resisting layer.
Figure 10 is that first protective layer is formed on golden finger end in fig .9, and one the is respectively formed in each weld pad
Diagrammatic cross-section after two protective layers.
Figure 11 is to remove the second garbage area in Figure 10 to obtain the diagrammatic cross-section of circuit board.
Main element symbol description
| Loading plate | 10 |
| First surface | 101 |
| Second surface | 102 |
| First copper foil | 11 |
| First film | 13 |
| Second copper foil | 15 |
| First solderless substrate | 20 |
| Processing district | 21 |
| First garbage area | 23 |
| Product zone | 211 |
| Second garbage area | 213 |
| First tooling hole | 25 |
| Inner layer conductive line pattern | 30 |
| Second film | 16 |
| 3rd copper foil | 17 |
| Second solderless substrate | 40 |
| Dielectric layer | 50 |
| Circuit substrate | 60 |
| Second tooling hole | 215 |
| Conductive through hole | 218 |
| First external conducting wire figure | 111 |
| Second external conducting wire figure | 117 |
| Welding resisting layer | 70 |
| First opening | 71 |
| Second opening | 73 |
| Golden finger end | 113 |
| Weld pad | 118 |
| First protective layer | 114 |
| Second protective layer | 119 |
| Centreless layer package substrate | 100 |
Following embodiment will further illustrate the present invention with reference to above-mentioned accompanying drawing.
Embodiment
The preparation method of the centreless layer package substrate provided below in conjunction with drawings and Examples the technical program and by
Centreless layer package substrate obtained by the preparation method is described in further detail.
The technical program embodiment provides centreless layer package substrate and comprised the following steps：
The first step, referring to Fig. 1, providing a loading plate 10.The loading plate 10 include relative first surface 101 and
Second surface 102.
Overlap first copper foil 11, the first film 13 and one successively on the first surface 101 of the loading plate 10
Second copper foil 15, overlaps first copper foil 11, the first film 13 and second copper foil 15 successively on second surface 102.
In the present embodiment, the thickness of first copper foil 11 is less than the thickness of second copper foil 15.
Then, the second copper foil 15 and the first film 13 described in one step press on first surface 101, loading plate 10 and described
The second copper foil 15 and the first film 13 on second surface 102, to obtain first solderless substrate 20.The first pressing base
Plate 20 includes a processing district 21 and the first garbage area 23 around the processing district 21.
Second step, referring to Fig. 2, by digital control hole drilling technique in the first garbage area 23 of first solderless substrate 20
Form multiple first tooling holes 25.Each first tooling hole 25 runs through first solderless substrate 20.
3rd step, referring to Fig. 3, the layers of copper that each second copper foil 15 corresponds to the processing district 21 is made to form interior
Layer conductive circuit pattern 30, and remove the layers of copper that each second copper foil 15 corresponds to first garbage area 23.Present embodiment
In, the layers of copper that each second copper foil 15 corresponds to the processing district 21 is made by shape by image transfer technique and etch process
Led into inner layer conductive line pattern 30, and each second copper foil 15 is etched into internal layer corresponding to the layers of copper of the processing district 21
While electric line figure 30, the copper that each second copper foil 15 corresponds to first garbage area 23 is removed by etch process
Layer.
4th step, referring to Fig. 4, overlapping second film 16 and successively on each inner layer conductive line pattern 30
Three copper foils 17.In the present embodiment, the thickness of the 3rd copper foil 17 is less than the thickness of second copper foil 15, and the 3rd bronze medal
The thickness of paper tinsel 17 is equal to the thickness of first copper foil 11.
Then, the copper foil 17 of second film 16 and the 3rd of the upside of the first solderless substrate of one step press 20, described first
The second film 16 and the 3rd copper foil 17 of the downside of 20 and first solderless substrate of solderless substrate 20 so that second film 16 is filled up
First tooling hole 25, obtains the second solderless substrate 40.
In second solderless substrate 40, positioned at first film 13 of the upside of the first surface 101 and one the
Two films 16 collectively form a dielectric layer 50；Positioned at first film 13 of the downside of the first surface 101 and one the
Two films 16 also collectively form a dielectric layer 50.The first copper foil 11 and the 3rd copper foil positioned at the upside of first surface 101
17 are located at the opposite sides of the dielectric layer 50 of the upside of first surface 101 respectively.In the upside of first surface 101
Layer conductive circuit pattern 30 is embedded in the dielectric layer 50 of the upside of first surface 101.Under the first surface 101
First copper foil 11 of side and the 3rd copper foil 17 are located at relative the two of the dielectric layer 50 of the downside of first surface 101 respectively
Side.Inner layer conductive line pattern 30 positioned at the downside of first surface 101 is embedded in Jie positioned at the downside of first surface 101
In electric layer 50.
5th step, referring to Fig. 5, removing first garbage area 23, and removes the loading plate 10, is separated from each other
Two circuit substrates 60.Each circuit substrate 60 corresponds to the processing district 21, and it is respectively provided with product zone 211 and around described
Second garbage area 213 of product zone 211.That is, the garbage area 213 of product zone 211 and second collectively forms described add
Work area 21.Each circuit substrate 60 includes a dielectric layer 50, first copper foil 11, in the 3rd copper foil 17 and one
Layer conductive circuit pattern 30.The copper foil 17 of first copper foil 11 and the 3rd is located at the opposite sides of the dielectric layer 50 respectively.Institute
Inner layer conductive line pattern 30 is stated to be embedded in the dielectric layer 50.
6th step, referring to Fig. 6, by digital control hole drilling technique in the second garbage area 213 of the circuit substrate 60 shape
Into multiple second tooling holes 215, multiple through holes 217 are formed in the product zone 211 of the circuit substrate 60.Each second instrument
Hole 215 and each through hole 217 run through the circuit substrate 60.
7th step, referring to Fig. 7, each through hole 217 is made into conductive through hole 218.The conductive through hole 218 electrically connects
Connect the firstth copper foil 11, the copper foil 17 of inner layer conductive line pattern 30 and the 3rd., will by electroplating technology in present embodiment
Copper electroplating layer is plated on hole wall, the first copper foil 11 and the 3rd copper foil 17 of each through hole 217, so that each through hole 217 be made
Into conductive through hole 218.In this way, the conductive through hole 218 is hollow conductive hole.
In other embodiments, each through hole 217 can also be filled up by electroplating process for filling hole, so as to will each lead to
Conductive through hole is made in hole 217.In such cases, the conductive through hole formed is solid conductive hole.
It is understood that when each through hole 217 is made into conductive through hole 218, without in whole first copper foil 11 and
Copper electroplating layer is also plated on whole 3rd copper foil 17, as long as the conductive through hole 218 is electrically connected with first copper foil 11, internal layer
The copper foil 17 of conductive circuit pattern 30 and the 3rd.
8th step, referring to Fig. 8, forming the first outer layer on the surface of first copper foil 11 in the dielectric layer 50
Conductive circuit pattern 111, the second external conducting wire figure is formed in the dielectric layer on the surface of the 3rd copper foil 17
Shape 117.The first external conducting wire figure 111, the second external conducting wire figure 117 and inner layer conductive line pattern 30
It is electrical connected by the conductive through hole 218.The first external conducting wire figure 111 and inner layer conductive line pattern 30 it
Between distance be D1.The distance between described second external conducting wire figure 117 and inner layer conductive line pattern 30 are D2.
D1/D2 is between 0.8 to 1.2.Wherein, D1 refers to the center of the thickness of the first external conducting wire figure 111 to internal layer
The distance at the center of the thickness of conductive circuit pattern 30；D2 refers to the thickness of the second external conducting wire figure 117
The distance at center to the center of the thickness of inner layer conductive line pattern 30.Preferably, in present embodiment, add using improved half
Cheng Fa（Modified Semi-Additive Process）Copper electroplating layer and the 3rd copper foil 17 by the first copper foil 11 and thereon
And the first external conducting wire figure 111 and the second external conducting wire figure 117 is respectively prepared in copper electroplating layer thereon.
9th step, referring to Fig. 9, on the first external conducting wire figure 111, the second external conducting wire figure
One layer of welding resisting layer 70 is formed on 117 and in each conductive through hole 218.The welding resisting layer 70 is covered in first outer layer and led
The external conducting wire figure 117 of electric line figure 111 and second, and be filled in the conductive through hole 218.And in described anti-welding
One first opening 71 and multiple second openings 73 are formed in layer 70.Part the first external conducting wire figure 111 is from institute
State multiple second openings 73 to expose, to define multiple weld pads 118.Part the second external conducting wire figure 117 is from institute
State the first opening 71 to expose, to define at least one golden finger end 113.Welding resisting layer 70 can use the side of solder-mask printing ink
Formula is formed.
In other embodiment, when filling up each through hole 217 by electroplating process for filling hole, then first outer layer is prevented
Can be formed in conductive circuit pattern 111 can form in addition on one layer of welding resisting layer, the second external conducting wire figure 117
One layer of welding resisting layer.
Tenth step, referring to Fig. 10, first protective layer 114 is formed on the golden finger end 113, each described
Weld pad 118 is respectively formed on second protective layer 119.First protective layer 114 can be nickel-gold layer.Second protective layer 119
Film can be welded for organic guarantor（OSP）, or NiPdAu layer.
11st step, also referring to Figure 10 and Figure 11, removes second garbage area 213, so as to obtain no sandwich layer envelope
Fill substrate 100.
After this, soldered ball can also be formed on weld pad 118, in order to be connected with other circuit boards.
The technical program also provides a kind of centreless layer package substrate 100, and the centreless layer package substrate 100 includes dielectric layer
50th, inner layer conductive line pattern 30, the first external conducting wire figure 111 and the second outer layer being embedded in the dielectric layer 50 are led
Electric line figure 117.
The first external conducting wire figure 111 and the second external conducting wire figure 117 are located at the dielectric respectively
The opposite sides of layer 50, and the first external conducting wire figure 111, the second external conducting wire figure 117 and internal layer lead
Electric line figure 30 is electrical connected by the conductive through hole 218 being formed in the dielectric layer 50.
The centreless layer package substrate 100 also includes being formed on the first external conducting wire figure 111, outside second
Welding resisting layer 70 in layer conductive circuit pattern 117 and in each conductive through hole 218.
One first opening 71 and multiple second openings 73 are formed with the welding resisting layer 70.Part second outer layer is led
Electric line figure 117 exposes from the described first opening 71, to define at least one golden finger end 113.Outside part described first
Layer conductive circuit pattern 111 is exposed from the multiple second opening 73, to define multiple weld pads 118.In other embodiment, when
When being plated layers of copper in conductive through hole 218 and filling up, the welding resisting layer only needs to be formed at the first external conducting wire figure 111
On upper and the second external conducting wire figure 117.
First protective layer 114 is formed with the golden finger end 113.Each weld pad 118 has been respectively formed on the
Two protective layers 119.First protective layer 114 can be nickel-gold layer.Second protective layer 119 can weld film for organic guarantor（OSP）,
Can also be NiPdAu layer.
Centreless layer package substrate that the technical program is provided and preparation method thereof, dielectric layer is by the first film and the second film
Constitute, inner layer conductive line pattern is embedded in the dielectric layer, the first external conducting wire figure and the second external conducting wire
Figure is located at the opposite sides of the dielectric layer, and the first external conducting wire figure, the second external conducting wire respectively
Figure and inner layer conductive line pattern are electrical connected by the conductive through hole being formed in the dielectric layer, it is not necessary to set core
Layer, reduces the thickness of centreless layer package substrate.In addition, in above-mentioned preparation method, two circuit substrates can be made simultaneously, from
And improve the producing efficiency of centreless layer package substrate.
It is understood that for the person of ordinary skill of the art, can be done with technique according to the invention design
Go out other various corresponding changes and deformation, and all these changes and deformation should all belong to the protection model of the claims in the present invention
Enclose.
Claims (5)
1. a kind of preparation method of centreless layer package substrate, it includes：
A loading plate is provided, the loading plate includes relative first surface and second surface, the first of the loading plate
First copper foil, first film and second copper foil are overlapped on surface successively, is folded successively on the second surface
Close another first copper foil, another first film and another second copper foil, and described in one step press on first surface
The second copper foil on two copper foils, the loading plate and the second surface, to obtain first solderless substrate, first pressure
Closing substrate includes a processing district and the first garbage area around the processing district；
Each second copper foil is made to form inner layer conductive line pattern；
Overlap second film and the 3rd copper foil, and one step press successively on each inner layer conductive line pattern
Under second film and the 3rd copper foil, first solderless substrate and the first solderless substrate on the upside of first solderless substrate
The second film and the 3rd copper foil of side, are obtained in the second solderless substrate, second solderless substrate, on the first surface
The first film and the second film of side collectively form the first film and the second film on the downside of a dielectric layer, the first surface
Collectively form a dielectric layer；
First garbage area is removed, and removes the loading plate, two circuit substrates being separated from each other, each circuit base
Plate is respectively provided with product zone and the second garbage area around the product zone, each circuit substrate include a dielectric layer,
One first copper foil, the 3rd copper foil and an inner layer conductive line pattern, first copper foil and
Three copper foils are located at the opposite sides of the dielectric layer respectively, and the inner layer conductive line pattern is embedded in the dielectric layer；
Multiple through holes are formed in the product zone of the circuit substrate, each through hole runs through the circuit substrate, and will
Each through hole is made conductive through hole, and the conductive through hole is electrically connected with first copper foil, inner layer conductive line pattern and the
Three copper foils；
The first external conducting wire figure is formed on the surface of first copper foil in the dielectric layer, in the dielectric layer
The second external conducting wire figure is formed on the surface of the 3rd copper foil, the first external conducting wire figure, the
Two external conducting wire figures and inner layer conductive line pattern are electrical connected by the conductive through hole；And
Second garbage area is removed, centreless layer package substrate is obtained.
2. the preparation method of centreless layer package substrate as claimed in claim 1, it is characterised in that the conductive through hole is mesopore
Conductive hole, after the first external conducting wire figure and the second external conducting wire patterning step is formed, remove described the
Before two garbage area steps, the preparation method of the centreless layer package substrate is additionally included in the first external conducting wire figure
Welding resisting layer is formed on upper, the second external conducting wire figure and in each conductive through hole, the welding resisting layer is covered in described
First external conducting wire figure and the second external conducting wire figure, and be filled in the conductive through hole, and in described anti-
The step of one first opening and multiple second openings are formed in layer, part the second external conducting wire pattern is from described
First opening is exposed, to define at least one golden finger end, and part the first external conducting wire figure is from the multiple
Second opening is exposed, to define multiple weld pads.
3. the preparation method of centreless layer package substrate as claimed in claim 2, it is characterised in that forming the welding resisting layer step
After rapid, remove before the second garbage area step, the preparation method of the centreless layer package substrate is additionally included in the gold
First protective layer is formed on finger end, the step of each weld pad is respectively formed on second protective layer.
4. the preparation method of centreless layer package substrate as claimed in claim 1, it is characterised in that obtaining first pressing
After substrate step, each second copper foil is made before forming inner layer conductive line pattern, the centreless layer package substrate
Preparation method be additionally included in the step of first garbage area forms multiple first tooling holes, each first tooling hole runs through
First solderless substrate.
5. the preparation method of centreless layer package substrate as claimed in claim 1, it is characterised in that the first outer layer conductor wire
The distance between road figure and inner layer conductive line pattern and the second external conducting wire figure and inner layer conductive line map
The ratio of the distance between shape is between 0.8 to 1.2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201310265770.4A CN104254191B (en) | 2013-06-28 | 2013-06-28 | Centreless layer package substrate and preparation method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310265770.4A CN104254191B (en) | 2013-06-28 | 2013-06-28 | Centreless layer package substrate and preparation method thereof |
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| CN104254191A CN104254191A (en) | 2014-12-31 |
| CN104254191B true CN104254191B (en) | 2017-08-25 |
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| CN107611036A (en) * | 2016-07-12 | 2018-01-19 | 碁鼎科技秦皇岛有限公司 | Package substrate and preparation method thereof, encapsulating structure |
| CN113498275B (en) * | 2020-04-07 | 2023-02-28 | 无锡深南电路有限公司 | Preparation method of coreless circuit board |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101364587A (en) * | 2007-08-10 | 2009-02-11 | 全懋精密科技股份有限公司 | Circuit board construction for embedding capacitor element and preparation thereof |
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| US7838779B2 (en) * | 2005-06-17 | 2010-11-23 | Nec Corporation | Wiring board, method for manufacturing same, and semiconductor package |
| TWI283152B (en) * | 2005-06-20 | 2007-06-21 | Phoenix Prec Technology Corp | Structure of circuit board and method for fabricating the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101364587A (en) * | 2007-08-10 | 2009-02-11 | 全懋精密科技股份有限公司 | Circuit board construction for embedding capacitor element and preparation thereof |
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