CN103327748B - Circuit board and preparation method thereof - Google Patents
Circuit board and preparation method thereof Download PDFInfo
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- CN103327748B CN103327748B CN201210073659.0A CN201210073659A CN103327748B CN 103327748 B CN103327748 B CN 103327748B CN 201210073659 A CN201210073659 A CN 201210073659A CN 103327748 B CN103327748 B CN 103327748B
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Abstract
The present invention provides the manufacture method of a kind of circuit board, including step: providing the circuit substrate with product zone and garbage area, described circuit substrate includes substrate, insulating barrier and the copper foil layer stacked gradually；Etched circuit substrate, so that the copper foil layer of product zone is formed conducting wire, and formed at garbage area and to run through multiple air slots of copper foil layer, multiple air slots are adjacent one another are and are parallel to each other, and multiple air slots all extend to the direction away from product zone with having a common boundary of garbage area from product zone；And the coverlay with at least one inducing QI through hole is fitted in copper foil layer, and so that coverlay is fitted in surface, conducting wire, and covering multiple air slot, each air slot is all connected with an inducing QI through hole.The present invention also provides for a kind of circuit board prepared by above method.
Description
Technical field
The present invention relates to circuit board technology, particularly relate to a kind of circuit board with preferable product quality and preparation method thereof.
Background technology
Along with the progress of science and technology, circuit board is being widely applied that electronic product obtains.Application about circuit board refers to document Takahashi, A. Ooki, N. Nagai, A. Akahoshi, H. Mukoh, A. Wajima, M. Res. Lab,
High density multilayer printed circuit board for HITAC M-880, IEEE Trans. on Components, Packaging, and Manufacturing
Technology, 1992, 15(4): 418-425。
The circuit of circuit board surface is typically protected by coverlay, and coverlay is typically fitted in circuit surface by the method for pressing.But, during laminating, it is very easy between coverlay and circuit produce bubble; such then make the laminating effect of coverlay bad; not only make circuit to be effectively protected and be prone to oxidation, also can increase the danger of plate bursting in finishing operations, the most also affect the outward appearance of circuit board product.It is to say, the laminating effect not good general of coverlay causes circuit board product quality to reduce.
Summary of the invention
Therefore, it is necessary to provide a kind of circuit board with preferable product quality and preparation method thereof.
Hereinafter with embodiment, a kind of circuit board and preparation method thereof will be described.
The manufacture method of a kind of circuit board, including step: providing circuit substrate, described circuit substrate includes substrate, insulating barrier and the first copper foil layer stacked gradually, and described circuit substrate has product zone and the garbage area being connected with product zone；Etched circuit substrate, so that the first copper foil layer of described product zone is formed conducting wire, and multiple first air slots of the first copper foil layer are run through in the formation of described garbage area, the plurality of first air slot is adjacent one another are and is parallel to each other, and multiple first air slots all extend to the direction away from product zone with having a common boundary of garbage area from product zone；And first coverlay with at least one the first inducing QI through hole is fitted in the first copper foil layer of circuit substrate, so that the first coverlay is fitted in the surface of the conducting wire of product zone, and covering multiple first air slots of garbage area, each first air slot is all connected with a first inducing QI through hole.
Preferably, the width of each first air slot is 0.1 millimeter to 0.3 millimeter, and the spacing of adjacent two the first air slots is 0.1 millimeter to 0.3 millimeter.
Preferably, described circuit substrate also includes the first adhesive-layer being arranged between insulating barrier and the first copper foil layer, and the plurality of first air slot runs through the first copper foil layer and the first adhesive-layer.
Preferably, after circuit substrate is provided, the step offering multiple first registration holes it is additionally included on circuit substrate；Before the first coverlay is fitted in the first copper foil layer of circuit substrate, multiple first opening, multiple second registration holes and at least one first inducing QI through hole described is offered in the first coverlay, the plurality of first opening corresponds to edge connector and the pad of the conducting wire of the first copper foil layer, and the plurality of second registration holes is corresponding with multiple first registration holes；After offering multiple second registration holes in the first coverlay before the first coverlay is fitted in the first copper foil layer of circuit substrate, by the cooperation of multiple first registration holes and multiple second registration holes, the first coverlay is alignd with circuit substrate.
Preferably, the substrate of described circuit substrate includes the second copper foil layer；When the first copper foil layer of etched circuit substrate, also etch described second copper foil layer, so that the second copper foil layer of described product zone is formed conducting wire, and multiple second air slots of the second copper foil layer are run through in the formation of described garbage area, the plurality of second air slot is adjacent one another are and is parallel to each other, and multiple second air slots all extend to the direction away from product zone with having a common boundary of garbage area from product zone；After the first coverlay is fitted in the first copper foil layer of circuit substrate, second coverlay with at least one the second inducing QI through hole is provided, and the second coverlay is fitted in the second copper foil layer surface of circuit substrate, so that the second coverlay covers multiple second air slots of garbage area, each second air slot is all connected with a second inducing QI through hole.
Preferably, the width of each second air slot is 0.1 millimeter to 0.3 millimeter, and the spacing of adjacent two the second air slots is 0.1 millimeter to 0.3 millimeter.
A kind of circuit board, it includes the substrate stacked gradually, insulating barrier, first copper foil layer and the first coverlay, described circuit board has product zone and the garbage area being connected with product zone, first copper foil layer of described product zone is formed with conducting wire, described garbage area is formed through the first copper foil layer and multiple first air slots covered by the first coverlay, the plurality of first air slot is adjacent one another are and is parallel to each other, multiple first air slots all extend to the direction away from product zone with having a common boundary of garbage area from product zone, the garbage area of described first coverlay is formed with at least one first inducing QI through hole, each first air slot is all connected with a first inducing QI through hole.
Preferably, the width of each first air slot is 0.1 millimeter to 0.3 millimeter, and the spacing of adjacent two the first air slots is 0.1 millimeter to 0.3 millimeter.
Preferably, described substrate includes the second copper foil layer, described circuit board also includes the second coverlay being arranged on the second copper foil layer away from insulating barrier side, second copper foil layer of described product zone is also formed with conducting wire, described garbage area is also formed with multiple second air slots running through the second copper foil layer and being covered by the second coverlay, the plurality of second air slot is adjacent one another are and is parallel to each other, multiple second air slots all extend to the direction away from product zone with having a common boundary of garbage area from product zone, the garbage area of described second coverlay is formed with at least one second inducing QI through hole, each second air slot is all connected with a second inducing QI through hole.
Preferably, the width of each second air slot is 0.1 millimeter to 0.3 millimeter, and the spacing of adjacent two the second air slots is 0.1 millimeter to 0.3 millimeter.
The manufacture method of the technical program circuit board has the advantage that in the technical program, form multiple first air slots in garbage area etching when the etching of the product zone of circuit substrate makes conducting wire simultaneously, and before surface, conducting wire pressing first coverlay of circuit substrate, in the first coverlay, offered at least one first inducing QI through hole, so, when surface, conducting wire pressing the first coverlay, gas between circuit substrate and the first coverlay can be derived by multiple first air slots, and finally from the first inducing QI through hole effusion connected with the first air slot.Further, multiple first air slots are the most adjacent, within the first coverlay will not be collapsed upon any one first air slot, the most then fully ensured that the inducing QI performance of the first air slot.Therefore, the technical program avoids and produces bubble in bonding processes between the first coverlay and circuit substrate so that the first coverlay and circuit substrate are in close contact, and improve pressing effect and final circuit board end properties.The circuit board of the technical program has good product quality and smooth outward appearance.
Accompanying drawing explanation
The schematic flow sheet of the manufacture method of the circuit board that Fig. 1 provides for the technical program embodiment.
The front view of the circuit substrate that Fig. 2 provides for the technical program embodiment.
The top view of the circuit substrate that Fig. 3 provides for the technical program embodiment.
The schematic top plan view of the first copper foil layer after the etched circuit substrate that Fig. 4 provides for the technical program embodiment.
Fig. 5 is the Fig. 4 sectional view along V-V line.
The elevational schematic view of the second copper foil layer after the etched circuit substrate that Fig. 6 provides for the technical program embodiment.
The schematic top plan view of the first coverlay that Fig. 7 provides for the technical program embodiment.
Fig. 8 is fitted in the cross-sectional schematic behind the first copper foil layer surface of circuit substrate in the first air slot position for the first coverlay that the technical program embodiment provides.
Fig. 9 is fitted in the front elevational schematic behind the first copper foil layer surface of circuit substrate in the first air slot position for the first coverlay that the technical program embodiment provides.
The elevational schematic view of the second coverlay that Figure 10 provides for the technical program embodiment.
Figure 11 is the front elevational schematic of the circuit board that the technical program embodiment obtains.
Main element symbol description
| Circuit substrate | 10 |
| First copper foil layer | 11 |
| First adhesive-layer | 12 |
| Insulating barrier | 13 |
| Second adhesive-layer | 14 |
| Second copper foil layer | 15 |
| Substrate | 100 |
| Product zone | 101 |
| Garbage area | 102 |
| First registration holes | 103 |
| First air slot | 104 |
| Second air slot | 105 |
| Edge connector | 111 |
| First pad | 112 |
| First line | 113 |
| Second pad | 151 |
| Second circuit | 152 |
| First coverlay | 16 |
| First opening | 161 |
| First inducing QI through hole | 162 |
| Second registration holes | 163 |
| Second coverlay | 17 |
| Second opening | 171 |
| Second inducing QI through hole | 172 |
| 3rd registration holes | 173 |
| Circuit board | 108 |
Following detailed description of the invention will further illustrate the present invention in conjunction with above-mentioned accompanying drawing.
Detailed description of the invention
Below in conjunction with drawings and Examples, the manufacture method of the circuit board that the technical program provides and the circuit board made are described in further detail.
Refer to Fig. 1, the manufacture method of the circuit board that the technical program provides, including step:
The first step, refers to Fig. 2 and Fig. 3, it is provided that circuit substrate 10.In the present embodiment, described circuit substrate 10 has glue Flexible copper-clad plate for two-sided, and it includes first copper foil layer the 11, first adhesive-layer 12, insulating barrier the 13, second adhesive-layer 14 and the second copper foil layer 15 set gradually from top to bottom.Described insulating barrier 13 is played a supporting role, and its most frequently used material is polyimides (Polyimide, PI) but it also may for polyethylene terephthalate glycol (Polyethylene Terephtalate,
PET) or be PEN (poly (ethylene naphthalate),
PEN).Described second adhesive-layer 14 and the second copper foil layer 15 constitute substrate 100.
Certainly, it will be understood by those skilled in the art that circuit substrate 10 can be other structures.Such as, circuit substrate 10 can be two-sided glue-free Flexible copper-clad plate, is and only includes the first copper foil layer 11, insulating barrier 13 and the structure of the second copper foil layer 15, and does not include the first adhesive-layer 12 and the second adhesive-layer 14.The most such as, circuit substrate 10 can be multilager base plate, i.e. substrate 100 is the structure including the alternately arranged copper foil layer of multilamellar with insulating barrier.
Described circuit substrate 10 has product zone 101 and the garbage area 102 being connected with product zone 101.Product zone 101 is used for constituting circuit board finished product, and garbage area 102 does not constitute circuit board finished product, for playing the effect supporting auxiliary product zone 101 in the manufacturing process of circuit board finished product, will be removed before making circuit board finished product.In the present embodiment, product zone 101 is rectangle, and garbage area 102 is positioned at product zone 101 surrounding, and around connecting product zone 101.Product zone 101 and garbage area 102 are respectively provided with identical stacked structure, i.e. all include first copper foil layer the 11, first adhesive-layer 12, insulating barrier the 13, second adhesive-layer 14 and a part for the second copper foil layer 15.
Carrying out before next step, circuit substrate 10 can also be carried out the step such as perforate, copper facing, to form conducting the first copper foil layer 11 and via of the second copper foil layer 15 in the product zone 101 of circuit substrate 10, and output multiple first registration holes 103 for follow-up para-position at garbage area 102.
Second step, sees also Fig. 4 to Fig. 6, etched circuit substrate 10, so that the first copper foil layer 11 of described product zone 101 and the second copper foil layer 15 are respectively formed conducting wire, and forms multiple first air slot 104 and multiple second air slot 105 at described garbage area 102.
It should be noted that depending on the specific design of conducting wire need to be according to the demand of specific product, in the diagram, be only the structure schematically drawing conducting wire in the present embodiment.In the present embodiment, the conducting wire of the first copper foil layer 11 includes multiple edge connector 111, multiple first pad 112 and a plurality of first line 113, and the conducting wire of certain first copper foil layer 11 can also include All other routes element.The conducting wire of the second copper foil layer 15 includes multiple second pad 151 and a plurality of second circuit 152, certainly can also include All other routes element.It addition, the chemical etching liquor for etched circuit substrate 10 has stronger etching performance, in general, removal portion adhesive layer 12,14 can also be etched while etching is removed part copper layers of foil 11,15 thus formed conducting wire.It is to say, it is said that in general, be the insulating barrier 13 exposed between conducting wire, air slot 104,105 also exposes insulating barrier 13.
Each first air slot 104 all runs through the first copper foil layer 11 and the first adhesive-layer 12, and exposes insulating barrier 13.The plurality of first air slot 104 is adjacent one another are and is parallel to each other.Each second air slot 105 all runs through the second copper foil layer 15 and the second adhesive-layer 14, and exposes insulating barrier 13.Multiple second air slots 105 are the most adjacent one another are and are parallel to each other.Multiple first air slots 104 and multiple second air slot 105 all extend to the direction away from product zone 101 with having a common boundary of garbage area 102 from product zone 101.Specifically, multiple first air slots 104 extend to garbage area 102 from a corner of product zone 101, and multiple second air slots 105 extend to garbage area 102 from a limit of product zone 101.The quantity of the first air slot 104 and the second air slot 105 does not limits, in the present embodiment, the quantity of the first air slot 104 and the second air slot 105 is 5, the width of each air slot 104,105 is about 0.11mm, the width of adjacent two the first air slots 104 is 0.1mm, and the width of adjacent two the second air slots 105 is 0.1mm.In actual applications, the width range of each air slot 104,105 is 0.1mm to 0.3mm.The width range of adjacent two the first air slots 104 is 0.1mm to 0.3mm, and the width range of adjacent two the second air slots 105 is 0.1mm to 0.3mm.
The thickness that the degree of depth is the first copper foil layer 11 of each first air slot 104 and the thickness of the first adhesive-layer 12 add and, in the present embodiment, about 30 μm.The most in actual applications, the thickness range of the first copper foil layer 11 is about 12 μm-30 μm, and the thickness of the first adhesive-layer 12 is about 10 μm-25 μm, and therefore, the depth bounds of the first air slot 104 is 22 μm-55 μm.The degree of depth of the second air slot 105 be the thickness of the thickness of the second copper foil layer 15 and the second adhesive-layer 14 add and, the second air slot 105 depth bounds is 22 μm-55 μm.
It will be appreciated by those skilled in the art that, when circuit substrate 10 is the two-sided glue-free Flexible copper-clad plate not including adhesive-layer 12,14, first air slot 104 only runs through the first copper foil layer 11 and exposes insulating barrier 13, and its thickness range is equivalent to the thickness range of the first copper foil layer 11；Second air slot 105 only runs through the second copper foil layer 15 and exposes insulating barrier 13, and its thickness range is equivalent to the thickness range of the second copper foil layer 15.
3rd step, refers to Fig. 7 to Fig. 9, it is provided that the first coverlay 16, and the first coverlay 16 is fitted in the surface of the first copper foil layer 11 of circuit substrate 10.
The size shape of the first coverlay 16 is corresponding with circuit substrate 10.Before laminating, need to be by the first perforate in the first coverlay 16 of the mode such as stamp or boring, to offer multiple first opening 161 corresponding to the region of product zone 101 in the first coverlay 16, and at least one first inducing QI through hole 162 and multiple second registration holes 163 are offered in region corresponding to garbage area 102 in the first coverlay 16.Multiple first openings 161 are for exposing the region needing to carry out at postorder surface process in product zone 101, such as golden finger area, pad etc..At least one first inducing QI through hole 162 described is corresponding with multiple first air slots 104, and the plurality of second registration holes 163 is corresponding with multiple first registration holes 103, for making the first coverlay 16 coordinate para-position with circuit substrate 10 when fitting the first coverlay 16.
Coordinate para-position by multiple second registration holes 163 with multiple first registration holes 103, so that the first coverlay 16 and circuit substrate 10 align, so, the first coverlay 16 can be made by the method for pressing can be fitted in the surface of the first copper foil layer 11.Specifically, in product zone 101, first coverlay 16 is fitted in the surface of the conducting wire of the first copper foil layer 11, and multiple first openings 161 expose the region needing to carry out at postorder surface process in the conducting wire of the first copper foil layer 11, such as edge connector the 111, first pad 112 etc.；At garbage area 102, the first coverlay 16 covers multiple first air slots 104 of garbage area 102, the most also makes each first air slot 104 all be connected, as shown in Figure 9 with a first inducing QI through hole 162.In the present embodiment, at least one first inducing QI through hole 162 described is a first inducing QI through hole 162, and five the first air slots 104 all connect with this first inducing QI through hole 162.The diameter range of this first inducing QI through hole 162 is 1mm to 4mm.It should be noted that the quantity of the first inducing QI through hole 162 does not limits, the quantity of the first air slot 104 connected with a first inducing QI through hole 162 does not limits, it is only necessary to each first air slot 104 is all connected with a first inducing QI through hole 162.For example, it is possible to offer two the first inducing QI through holes 162 at the first coverlay 16 so that two the first air slots 104 respectively with a corresponding connection of the first inducing QI through hole 162, the other three the first air slot 104 is corresponding with another the first inducing QI through hole 162 to be connected.The most such as, in other embodiments, five the first inducing QI through holes 162 can be offered at the first coverlay 16 so that the connection corresponding with first inducing QI through hole 162 respectively of each first air slot 104.The most such as, the length of each the first air slot 104 can be inconsistent, and so, the distributing position of five the first inducing QI through holes 162 can be depending on the length of each first air slot 104.
It will be appreciated by those skilled in the art that, during first coverlay 16 is fitted in the surface of the first copper foil layer 11, it is very easy between the first coverlay 16 and the surface of the first copper foil layer 11 produce micro-bubble, especially corresponds to the position away from the first opening 161 in the region of product zone 101 at the first coverlay 16.In the present embodiment, the first opening 161 concentrates on upside and the right side of product zone 101, thus, the lower left side in product zone 101 is prone in bonding processes produce bubble.But, in the technical program, owing to the lower left side of product zone 101 has the existence of multiple first air slots 104 extended from garbage area 102, so that lower left side in product zone 101 is prone to the gas producing bubble and is derived by multiple first air slots 104 in bonding processes, and finally escape from the first inducing QI through hole 162.And, owing to the width of each first air slot 104 is less, multiple first air slots 104 are the most adjacent, within the first coverlay 16 can't be collapsed upon any one first air slot 104, as shown in Figure 8, the most then the inducing QI performance of the first air slot 104 has been fully ensured that.Therefore, the technical program avoids and produces bubble in bonding processes between the first coverlay 16 and the first copper foil layer 11 so that the first coverlay 16 and the first copper foil layer 11 are in close contact, and improve pressing effect and final circuit board end properties.
According to the above description, it will be understood by those skilled in the art that offering position and offering quantity and do not limit of the first air slot 104, be preferably opened in the region needing to carry out at postorder surface process in the conducting wire away from the first copper foil layer 11.In fact, in the present embodiment, in addition to offering multiple first air slot 104 in the lower left side of the product zone 101 of the first copper foil layer 11, it is also possible to all offer multiple first air slot 104 in left side and the downside of the product zone 101 of the first copper foil layer 11, so can more preferably play the effect of inducing QI.
In addition, it is necessary to point out, the first inducing QI through hole 162 can be various hole, such as, can be tooling hole, also act as the effect of inducing QI while the effect playing tooling hole.
4th step, by circuit substrate 10 turn-over of the first coverlay 16 of having fitted, and the second coverlay 17 as shown in Figure 10 of fitting on the second copper foil layer 15 surface of circuit substrate 10.
The size shape of the second coverlay 17 is also corresponding with circuit substrate 10.Before laminating, need to be by the first perforate in the second coverlay 17 of the mode such as stamp or boring, to offer multiple second opening 171 corresponding to the region of product zone 101 in the second coverlay 17, and at least one second inducing QI through hole 172 and multiple 3rd registration holes 173 are offered in region corresponding to garbage area 102 in the second coverlay 17.Multiple second openings 171 need to carry out at postorder the region of surface process, the such as second pad 151 etc. in the conducting wire of the second copper foil layer 15 exposing product zone 101.At least one second inducing QI through hole 172 described is corresponding with multiple second air slots 105, and the plurality of 3rd registration holes 173 is corresponding with multiple first registration holes 103, for making the second coverlay 17 coordinate para-position with circuit substrate 10 when fitting the second coverlay 17.
The attaching process of the second coverlay 17 and the attaching process of the first coverlay 16 are close, can be fitted in the surface of the second copper foil layer 15 by the method for pressing.Specifically, in product zone 101, the second coverlay 17 is fitted in the surface of the conducting wire of the second copper foil layer 15, and multiple second openings 171 expose the region needing to carry out surface process at postorder；At garbage area 102, the second coverlay 16 covers multiple second air slots 105 of garbage area 102, the most also makes each second air slot 105 all be connected with a second inducing QI through hole 172.
It will be appreciated by those skilled in the art that, during laminating the second coverlay 17, it is very easy between the second coverlay 17 and the surface of the second copper foil layer 15 produce micro-bubble, especially corresponds to the position away from the second opening 171 in the region of product zone 101 at the second coverlay 17.In the present embodiment, the second opening 171 concentrates on upper left side and the lower left side of product zone 101, thus, it is prone in bonding processes in the left side of product zone 101 produce bubble.But, in the technical program, owing to the left side of product zone 101 has the existence of multiple second air slots 105 extended from garbage area 102, so that right side in product zone 101 is prone to the gas producing bubble and is derived by multiple second air slots 105 in bonding processes, and finally escape from the second inducing QI through hole 172.So, then avoid in bonding processes, between the second coverlay 17 and the second copper foil layer 15, produce bubble.
In addition, it is necessary to it is noted that when substrate 100 is to have included the monolayer of coverlay, bilayer or multiple structure, the technical program can not include the step of the 4th step.
After laminating the second coverlay 17, circuit substrate 10 can be made circuit board 108.It should be noted that the step of laminating the second coverlay 17 can also complete with the step of the first coverlay 16 of fitting simultaneously.Those skilled in the art know, after laminating the second coverlay 17, it is also possible to circuit board 108 carries out gold-plated, stamp etc. science and engineering skill, final obtain circuit board finished product.
Seeing also Fig. 1 to Figure 11, the circuit board 108 made by above-mentioned technique includes the second coverlay 17, substrate 100, insulating barrier the 13, first adhesive-layer the 12, first copper foil layer 11 and the first coverlay 16 stacked gradually from bottom to top.Described circuit board 108 has product zone 101 and the garbage area 102 being connected with product zone 101, first copper foil layer 11 of described product zone 101 is formed with conducting wire, described garbage area 102 is formed through the first copper foil layer 11 and multiple first air slots 104 covered by the first coverlay 16, the plurality of first air slot 104 is adjacent one another are and is parallel to each other, and multiple first air slots 104 all extend to the direction away from product zone 101 with having a common boundary of garbage area 102 from product zone 101.First coverlay 16 of described garbage area 102 is formed with at least one first inducing QI through hole 162, and each first air slot 104 is all connected with a first inducing QI through hole 162.
In the present embodiment, substrate 100 is the single layer structure including one layer of copper foil layer, and in other embodiments, substrate 100 can be the dielectric base including copper foil layer, it is also possible to be the multiple structure including the above copper foil layer of two-layer.In the present embodiment, substrate 100 does not include coverlay, in other embodiments, substrate 100 can be the multiple structure including dielectric film, such as, substrate 100 can be to include the second adhesive-layer the 14, second copper foil layer 15 and structure of the second coverlay 17, or can be to include alternately arranged multiple layer of copper layers of foil and multilayer dielectric layer and the structure of one layer of coverlay.So, the second coverlay 17 in circuit board 108 is not essential features.
nullIt will be appreciated by those skilled in the art that，In the technical program，Form multiple first air slots 104 and multiple second air slot 105 in garbage area 102 etching when the etching of the product zone 101 of circuit substrate 10 makes conducting wire simultaneously，And before surface, conducting wire pressing first coverlay 16 and the second coverlay 17 of circuit substrate 10 both sides，At least one first inducing QI through hole 162 and second inducing QI through hole 172 is offered respectively in advance in the first coverlay 16 and the second coverlay 17，So，When circuit substrate 10 both sides pressing the first coverlay 16 and the second coverlay 17，Gas between circuit substrate 10 and the first coverlay 16 can be derived by multiple first air slots 104，And finally escape from the first inducing QI through hole 162 connected with the first air slot 104，Gas between circuit substrate 10 and the second coverlay 17 can be derived by multiple second air slots 105，And finally escape from the second inducing QI through hole 172 connected with the second air slot 105.And, owing to the width of each first air slot 104 and the second air slot 105 is less, multiple first air slots 104 are the most adjacent, multiple second air slots 105 are the most adjacent, within first coverlay 16 can't be collapsed upon any one first air slot 104, within second coverlay 17 is not the most collapsed upon any one second air slot 105, the most then fully ensure that the first air slot 104 and inducing QI performance of the second air slot 105.Therefore, the technical program avoids and produces bubble in bonding processes between coverlay 16,17 and circuit substrate 10 so that coverlay 16,17 and circuit substrate are in close contact, and improve pressing effect and final circuit board end properties.
It is understood that for the person of ordinary skill of the art, can conceive according to the technology of the present invention and make other various corresponding changes and deformation, and all these change all should belong to the protection domain of the claims in the present invention with deformation.
Claims (10)
1. a manufacture method for circuit board, including step:
Thering is provided circuit substrate, described circuit substrate includes substrate, insulating barrier and the first copper foil layer stacked gradually,
Described circuit substrate has product zone and the garbage area being connected with product zone；
Etched circuit substrate, to form conducting wire by the first copper foil layer of described product zone, and at described waste material
District is formed runs through multiple first air slots of the first copper foil layer, the plurality of first air slot adjacent one another are and
It is parallel to each other, multiple first air slots all having a common boundary to the direction away from product zone from product zone and garbage area
Extending, the width of each first air slot is 0.1 millimeter to 0.11 millimeter；And
First coverlay with at least one the first inducing QI through hole is fitted in the first copper foil layer of circuit substrate,
So that the first coverlay is fitted in the surface of the conducting wire of product zone, and cover multiple the first of garbage area
Air slot, each first air slot is all connected with a first inducing QI through hole.
2. the manufacture method of circuit board as claimed in claim 1, it is characterised in that adjacent two the first inducing QIs
The spacing of groove is 0.1 millimeter to 0.3 millimeter.
3. the manufacture method of circuit board as claimed in claim 1, it is characterised in that described circuit substrate also wraps
Including the first adhesive-layer being arranged between insulating barrier and the first copper foil layer, the plurality of first air slot runs through
First copper foil layer and the first adhesive-layer.
4. the manufacture method of circuit board as claimed in claim 1, it is characterised in that provide circuit substrate it
After, it is additionally included on circuit substrate the step offering multiple first registration holes；By the first coverlay laminating
Before the first copper foil layer of circuit substrate, the first coverlay is offered multiple first opening, Duo Ge
Two registration holes and at least one first inducing QI through hole described, the plurality of first opening corresponds to the first Copper Foil
Edge connector in the conducting wire of layer and pad, the plurality of second registration holes and multiple first registration holes phases
Corresponding；After offering multiple second registration holes in the first coverlay and the first coverlay is being fitted in electricity
Before first copper foil layer of base board, will by the cooperation of multiple first registration holes and multiple second registration holes
First coverlay aligns with circuit substrate.
5. the manufacture method of circuit board as claimed in claim 1, it is characterised in that the base of described circuit substrate
The end, includes the second copper foil layer；When the first copper foil layer of etched circuit substrate, also etch described second Copper Foil
Layer, so that the second copper foil layer of described product zone to be formed conducting wire, and runs through in the formation of described garbage area
Multiple second air slots of the second copper foil layer, the plurality of second air slot is adjacent one another are and is parallel to each other,
Multiple second air slots all extend to the direction away from product zone with having a common boundary of garbage area from product zone；To
After first coverlay fits in the first copper foil layer of circuit substrate, it is provided that there is at least one second inducing QI
Second coverlay of through hole, and the second coverlay is fitted in the second copper foil layer surface of circuit substrate, with
Make the second coverlay cover multiple second air slots of garbage area, each second air slot all with one second
Inducing QI through hole is connected.
6. the manufacture method of circuit board as claimed in claim 5, it is characterised in that each second air slot
Width is 0.1 millimeter to 0.3 millimeter, the spacing of adjacent two the second air slots be 0.1 millimeter to 0.3 milli
Rice.
7. a circuit board, it includes substrate, insulating barrier, the first copper foil layer and the first coverlay stacked gradually,
Described circuit board has product zone and the garbage area being connected with product zone, the first copper foil layer of described product zone
Being formed with conducting wire, described garbage area is formed through the first copper foil layer and is covered by the first coverlay
Multiple first air slots, the plurality of first air slot is adjacent one another are and is parallel to each other, multiple first inducing QIs
Groove all extends to the direction away from product zone with having a common boundary of garbage area from product zone, each first air slot
Width is 0.1 millimeter to 0.11 millimeter, the garbage area of described first coverlay be formed at least one first
Inducing QI through hole, each first air slot is all connected with a first inducing QI through hole.
8. circuit board as claimed in claim 7, it is characterised in that the spacing of adjacent two the first air slots is
0.1 millimeter to 0.3 millimeter.
9. circuit board as claimed in claim 7, it is characterised in that described substrate includes the second copper foil layer, institute
State the second coverlay that circuit board also includes being arranged on the second copper foil layer away from insulating barrier side, described product
Second copper foil layer in district is also formed with conducting wire, described garbage area be also formed with running through the second copper foil layer and
Multiple second air slots covered by the second coverlay, the plurality of second air slot is adjacent one another are and mutual
Parallel, multiple second air slots all prolong to the direction away from product zone from the boundary of product zone with garbage area
Stretching, the garbage area of described second coverlay is formed with at least one second inducing QI through hole, each second inducing QI
Groove is all connected with a second inducing QI through hole.
10. circuit board as claimed in claim 9, it is characterised in that the width of each second air slot is 0.1
Millimeter is to 0.3 millimeter, and the spacing of adjacent two the second air slots is 0.1 millimeter to 0.3 millimeter.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210073659.0A CN103327748B (en) | 2012-03-20 | 2012-03-20 | Circuit board and preparation method thereof |
| TW101110698A TWI444116B (en) | 2012-03-20 | 2012-03-28 | Printed circuit board and method for manufacturing same |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210073659.0A CN103327748B (en) | 2012-03-20 | 2012-03-20 | Circuit board and preparation method thereof |
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| CN103327748A CN103327748A (en) | 2013-09-25 |
| CN103327748B true CN103327748B (en) | 2016-12-14 |
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| CN (1) | CN103327748B (en) |
| TW (1) | TWI444116B (en) |
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| CN104470257B (en) * | 2014-12-12 | 2017-10-13 | 东莞市康庄电路有限公司 | It is a kind of to improve the processing method that pcb board golden finger plugs positional precision |
| CN111385962A (en) * | 2018-12-29 | 2020-07-07 | 广东生益科技股份有限公司 | PCB and preparation method thereof |
| CN110099507B (en) * | 2019-05-29 | 2022-04-05 | 广东依顿电子科技股份有限公司 | Thick copper circuit board and manufacturing method thereof |
| CN112739075B (en) * | 2020-12-08 | 2022-05-24 | 深圳市祺利电子有限公司 | Manufacturing method for preventing tin spraying and explosion of circuit board |
| CN113329556B (en) * | 2021-05-19 | 2022-06-07 | 景旺电子科技(龙川)有限公司 | Flexible circuit board and manufacturing method thereof |
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| CN101494957A (en) * | 2008-01-23 | 2009-07-29 | 富葵精密组件(深圳)有限公司 | Method and substrate for producing multi-layer circuit board |
| TWI341159B (en) * | 2007-09-07 | 2011-04-21 | Foxconn Advanced Tech Inc | Method for cutting pritned circuit board |
| TW201125455A (en) * | 2010-01-11 | 2011-07-16 | Foxconn Advanced Tech Inc | Method for manufacturing printed circuit board |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3994597B2 (en) * | 1999-10-08 | 2007-10-24 | 株式会社村田製作所 | Method and apparatus for manufacturing ceramic multilayer substrate |
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- 2012-03-20 CN CN201210073659.0A patent/CN103327748B/en active Active
- 2012-03-28 TW TW101110698A patent/TWI444116B/en active
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|---|---|---|---|---|
| TWI341159B (en) * | 2007-09-07 | 2011-04-21 | Foxconn Advanced Tech Inc | Method for cutting pritned circuit board |
| CN101494957A (en) * | 2008-01-23 | 2009-07-29 | 富葵精密组件(深圳)有限公司 | Method and substrate for producing multi-layer circuit board |
| TW201125455A (en) * | 2010-01-11 | 2011-07-16 | Foxconn Advanced Tech Inc | Method for manufacturing printed circuit board |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201340804A (en) | 2013-10-01 |
| CN103327748A (en) | 2013-09-25 |
| TWI444116B (en) | 2014-07-01 |
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Effective date of registration: 20170811 Address after: No. 18, Tengfei Road, Qinhuangdao Economic & Technological Development Zone, Hebei, China Co-patentee after: Peng Ding Polytron Technologies Inc Patentee after: Hongqisheng Precision Electronic (Qinhuangdao) Co., Ltd. Address before: 066000 Qinhuangdao economic and Technological Development Zone, Hebei Tengfei Road, No. 18 Co-patentee before: Zhending Technology Co., Ltd. Patentee before: Hongqisheng Precision Electronic (Qinhuangdao) Co., Ltd. |
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