1260189 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種基板之製造方法，且特別是有關於 種内埋被動元件的基板之製造方法。 【先前技術】 隨著通訊電子產品日益進步，輕薄短小和高功能化產品已 疋市％主流趨勢，縮小零組件體積與使用數目遂成為產品設計 與應用之重點。系統構裝（System in package)具有縮小構裝面 積、南速化、開發時程短及生產成本低等優勢，已成為取代傳 統$別構裝系統的主流技術。整個系統構裝分為整合型基板與 p度互連二大主軸’其中整合型基板強調基板的高功能及整 口特|±，將被動元件内埋入基板，終極希望能將主動元件及光 傳導通路也-起埋人基板。高密度互連技術則在強調透過特殊 的材料（例如奈米材料）及製程，將錢間距由現㈣微米 下降到100微米以下。 在有限的基板空間内，縮小或埋入被動元件以創造更多空 ，來架構主動it件為目前薇商視為模組化之重要技術。一般而 内埋it件基板技術的構裝整合，可以用來取代傳統離散式 =動凡件（例如電容、電阻及電感等〉，崎的功能性高分子複 口材料技術’將被動兀件以塗佈、網印、壓合蝕刻等方式， =藏在電路板_層巾。内層的㈣與疊層結構可以依照實際 應用時之電路特性與需求來作選擇。 傳統將被動元件Μ在基板外側（可能是基板的上下兩 動一 J想而知有整體組件厚度可觀之缺點。而相較於此，將被 動几件内駐基板的優點眾多1了可省下基板表面的空間使1260189 IX. Description of the Invention: [Technical Field] The present invention relates to a method of manufacturing a substrate, and more particularly to a method of manufacturing a substrate in which a passive component is embedded. [Prior Art] With the advancement of communication electronic products, the thin, light and high-functionalized products have become the mainstream trend of the market, and the reduction in the size and number of components has become the focus of product design and application. System in package has the advantages of reduced package area, south speed, short development time and low production cost, and has become the mainstream technology to replace the traditional $. The whole system is divided into two types: integrated substrate and p-interconnected two major spindles. The integrated substrate emphasizes the high function of the substrate and the whole port is ±±, and the passive component is buried in the substrate. Ultimately, it is desirable to have the active component and light. The conduction path also - from the buried substrate. High-density interconnect technology emphasizes the use of special materials (such as nanomaterials) and processes to reduce the pitch of money from the current (four) micron to less than 100 microns. In a limited substrate space, shrinking or embedding passive components to create more space to construct active components is an important technology that Weishang considers to be modular. In general, the assembly and integration of the embedded substrate technology can be used to replace the traditional discrete = moving parts (such as capacitors, resistors and inductors), and the functional polymer cross-over material technology of Saki will be passive. Coating, screen printing, press etching, etc., hidden in the circuit board _ layer towel. The inner layer (four) and the laminated structure can be selected according to the circuit characteristics and requirements in practical applications. Traditionally, the passive component is placed on the outside of the substrate. (It may be that the upper and lower movements of the substrate are known to have the disadvantages of a considerable thickness of the overall assembly. In contrast, the advantages of the passive internal substrate are numerous, and the space on the surface of the substrate can be saved.
TW2073PA 5 1260189 基板所需之表面積縮小和整體組件厚度倍減之外，還可因被動 元件埋至基板内而大幅減少電路板之焊錫接點，降低因高頻所 產不’、、要之寄生效應，進而提升射頻模組在高頻的電氣響 應，亚增加模組製作與組裝的良率與可靠度；也由於上述之優 點’使製造成本大幅降低。 以目前無源零件的數量每年成長30%，同時基板面積以每 年縮小3〇%的發展情勢下，傳統離散式無源零件的更新替換勢 在必行。因此如何將元件精準地埋入基板内以形成—種穩定的 _ 基板、、Ό構，已為相關業界努力研發的重要目標之一。 【發明内容】 有鏗於此，本發明的目的就是在提供一種基板之製造方 法，包括步驟： 提供一芯板（Core)，芯板之上下側係具有一内層線路； 形成一容置空間（Receiving Cavity)於芯板處； 埋入一元件於容置空間，並形成一絕緣層以包覆元件、芯 板及其上下側的内層線路； # 在絕緣層處形成複數個孔洞，以裸露出元件之複數個電 極； 形成複數個通孔（Through Hole)以貫穿絕緣層與芯板； 形成一導電薄膜於絕緣層之表面和通孔之側壁； 形成一導電層於導電薄膜上； 圖案化導電層’以形成一外層線路；及 形成一防銲層（Solder Mask)於外層線路上。 為讓本發明之上述目的、特徵、和優點能更明顯易懂，下 文特舉一較佳實施例，並配合所附圖式，作詳細說明如下： TW2073PA . 1260189 【實施方式】 請參照第1A〜1K圖，其繪示依照本發明一較佳實施例之内 埋兀件之基板之製造方法。首先，提供一芯板（c〇re)1〇，如第1A 圖所示。之後，在芯板10之上下側形成一内層線路，如第18圖 所示。在此實施例中，可在芯板的第一表面101和第二表面102 各鍍上一導電層11，導電層11的材料可以是任何金屬，在此則 以銅膜作為導電層，並利用曝光、顯影和蝕刻等方式使導電層）） 圖案化，以形成内層線路12。芯板之材質例如是玻璃纖=/布或 非玻璃纖維布（如ABF)。 接著，形成一容置空間（Receiving Cavity)13於芯板處10， 如第1C圖所示。形成容置空間13的方法有很多種，例如是以機 械鑽孔（Machine Drilling)之方式形成。而容置空間13的實際大 小則視欲埋入基板的元件尺寸而定。 然後，將一兀件（例如是電容、電感或電阻等被動元件 埋入容置空間13，並形成一絕緣部（即之後所提及之第一介電層 15和第二介電層16)以包覆元件14、芯板1〇及芯板1〇上下^ 的内層線路12。其中一種可實行之方法如下： 首先，將元件14设置於芯板1 〇下方，使容置空間’ 3與 元件14的位置相對應，並提供一第一介電層15於元件14之、 下方和提供一第二介電層16於芯板10之上方，如第id圖所 示。一般可選用還未完全硬化的材料（尚有部分流動性）做為第 一介電層15和第二介電層16,以使元件14在壓合後可完全被 芯板10、第一介電層15與第二介電層16包圍。也因 過程中，第一、第二介電層仍有部分流動性因此可較佳地ς 供一第一離形紙17與一第二離形紙18於第一介電層與第 二介電層16之上方，以避免在之後的壓合過程中^未完全硬TW2073PA 5 1260189 The surface area required for the substrate is reduced and the thickness of the overall component is doubled. The passive components can be buried in the substrate to greatly reduce the solder joints of the board, and the parasitic noise caused by high frequency can be reduced. The effect, in turn, improves the electrical response of the RF module at high frequencies, and increases the yield and reliability of module fabrication and assembly; and because of the above advantages, the manufacturing cost is greatly reduced. With the current number of passive parts growing by 30% per year and the substrate area shrinking by 3% per year, the replacement of traditional discrete passive parts is imperative. Therefore, how to accurately embed components into the substrate to form a stable _ substrate and structure has become one of the important goals of the industry. SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide a method for manufacturing a substrate, comprising the steps of: providing a core board having an inner layer line on the lower side of the core board; forming an accommodating space ( Receiving Cavity) at a core plate; embedding a component in the accommodating space and forming an insulating layer to cover the component, the core plate and the inner layer of the upper and lower sides thereof; # forming a plurality of holes at the insulating layer to expose a plurality of electrodes of the component; forming a plurality of through holes to penetrate the insulating layer and the core plate; forming a conductive film on the surface of the insulating layer and sidewalls of the through holes; forming a conductive layer on the conductive film; patterned conductive The layer 'is formed to form an outer layer; and a solder mask is formed on the outer layer. The above described objects, features, and advantages of the present invention will become more apparent from the description of the preferred embodiments of the invention. 1K, which illustrates a method of fabricating a substrate for embedding a device in accordance with a preferred embodiment of the present invention. First, a core plate (c〇re) is provided, as shown in Fig. 1A. Thereafter, an inner layer wiring is formed on the lower side of the core board 10 as shown in Fig. 18. In this embodiment, a conductive layer 11 may be plated on each of the first surface 101 and the second surface 102 of the core board. The material of the conductive layer 11 may be any metal, and the copper film is used as a conductive layer, and the copper layer is used as a conductive layer. The conductive layer)) is patterned by exposure, development, and etching to form the inner layer wiring 12. The material of the core plate is, for example, a glass fiber = / cloth or a non-glass cloth (such as ABF). Next, a receiving cavity 13 is formed at the core panel 10 as shown in FIG. 1C. There are many ways to form the accommodating space 13, for example, in the form of Mechanical Drilling. The actual size of the accommodating space 13 depends on the size of the component to be buried in the substrate. Then, a passive component such as a capacitor, an inductor or a resistor is buried in the accommodating space 13 and an insulating portion (ie, the first dielectric layer 15 and the second dielectric layer 16 mentioned later) is formed. The inner layer 12 is covered by the cladding member 14, the core board 1 and the core board 1 . One of the implementable methods is as follows: First, the component 14 is disposed under the core board 1 , to make the accommodating space '3 and The position of the component 14 is corresponding, and a first dielectric layer 15 is provided under the component 14 and a second dielectric layer 16 is disposed above the core board 10, as shown in the id diagram. The fully hardened material (which has partial fluidity) is used as the first dielectric layer 15 and the second dielectric layer 16 so that the element 14 can be completely replaced by the core board 10, the first dielectric layer 15 and the first layer after pressing. The second dielectric layer 16 is surrounded. Also, during the process, the first and second dielectric layers still have partial fluidity, so that a first release paper 17 and a second release paper 18 are preferably provided. Above the dielectric layer and the second dielectric layer 16 to avoid being completely hard during the subsequent lamination process
TW2073PA 7 1260189 化的第一、第二介電層污染了壓合機台。 之後’以壓合步驟對此堆疊體進行壓合，使元件14埋入容 置空間内1 3，如第1 £圖所示。壓合步驟一般係在高溫高壓下進 行，以固化第一介電層15與第二介電層16。完成壓合步驟後， 可移除第一離形紙1 7與一第二離形紙1 8。其中，第一介電層^ 5 與第一介電層16係構成一絕緣層，在壓合步驟後包覆元件14、 芯板10及内層線路12。 接著’在絕緣層處形成複數個孔洞19，以裸露出元件的複 數個電極142，如第1 F圖所示。在此實施例中，可使用雷射鑽 • 孔（Laser Drillin9)方式在第二介電層16處形成孔洞19，以裸露 出元件14的電極142。 然後’形成複數個通孔（Through Hole)21以貫穿第一介· 層16、芯板1〇與第一介電層_15,如第1G圖所示。在實際廉用 中f採用機械鑽孔（Machine Drilling)方式形成通孔21。The first and second dielectric layers of the TW2073PA 7 1260189 contaminate the press table. Thereafter, the stack is pressed by a press-fitting step to cause the component 14 to be buried in the accommodating space 13 as shown in the first £. The pressing step is generally performed under high temperature and high pressure to cure the first dielectric layer 15 and the second dielectric layer 16. After the pressing step is completed, the first release paper 17 and a second release paper 18 can be removed. The first dielectric layer 5 and the first dielectric layer 16 form an insulating layer, and the component 14, the core 10 and the inner layer 12 are covered after the pressing step. A plurality of holes 19 are then formed at the insulating layer to expose a plurality of electrodes 142 of the component, as shown in Figure 1F. In this embodiment, a hole 19 can be formed at the second dielectric layer 16 using a Laser Drillin 9 method to expose the electrode 142 of the component 14. Then, a plurality of through holes 21 are formed to penetrate the first dielectric layer 16, the core plate 1 and the first dielectric layer -15, as shown in Fig. 1G. In the practical and inexpensive use, the through hole 21 is formed by a mechanical drilling method.
接著，形成一導電薄膜23於絕緣層之表面和通孔21之侧 壁，如第1H圖所示。在實際應用中可對如第ig圖所示之組件 進行濺鍍（Sputter)，除了在第一介電層15和第二介電層16上會 形成一層導電薄膜23外，通孔21的側壁上也會覆蓋一層導带^ 膜23。導電薄膜的材料例如是金屬銅。 然後，形成一第一導電層24和一第二導電層25於導電薄 膜23上，如第1丨圖所示。在此實施例中，可利用電鍍方弋 (Plating)形成第一導電層24和一第二導電層％，且诵 : 、札21側 i上的導電薄膜23亦會同時增厚。第一導電層24和一 μ 電層2 5的材料例如是金屬銅。 :: 以形成一 顯影、|虫 接著，圖案化第一導電層24和第二導電層25, 外層線路26，如第1J圖所示。其中，可利用曝光、Next, a conductive film 23 is formed on the surface of the insulating layer and the side walls of the through holes 21 as shown in Fig. 1H. In practical applications, the component shown in FIG. ig can be sputtered, except that a conductive film 23 is formed on the first dielectric layer 15 and the second dielectric layer 16, and the sidewall of the via 21 is formed. A layer of conductive film 23 is also covered. The material of the conductive film is, for example, metallic copper. Then, a first conductive layer 24 and a second conductive layer 25 are formed on the conductive film 23 as shown in Fig. 1. In this embodiment, the first conductive layer 24 and the second conductive layer % can be formed by using plating, and the conductive film 23 on the side of the slab 21 is also thickened at the same time. The material of the first conductive layer 24 and the one-electrode layer 25 is, for example, metallic copper. :: to form a development, worm Next, the first conductive layer 24 and the second conductive layer 25 are patterned, and the outer layer 26 is as shown in FIG. 1J. Among them, exposure can be used,
TW2073PA 8 1260189 刻等步驟形成基板之外層線路26。 最後，形成一防銲層（Solder Mask)於外層線路26上，如 第1K圖中所示之第一銲料層27a和第二銲料層27b分別形成 於圖案化之第一導電層24與圖案化之第二導電層25上。 根據上述實施例所述之製造方法，可將一元件，特別是一 被動元件（如電容、電感或電阻），穩定的埋入基板内。内埋被 動π件的基板具有諸多優點，例如：在有限的基板空間内埋入 被動元件，不但可降低整體模件之厚度，還可增加更多空間來 架構主動元件，以提升模組的多功能性。再者，因被動元件埋 至基板内而大幅減少電路板之焊錫接點，降低因高頻所產生不 必要之寄生效應，進而提升射頻模組在高頻的電氣響應，並增 加模組製作與組裝的良率與可靠度；也由於上述這些優點，使 衣造成本大幅降低。 ，綜上所述，雖然本發明已以一較佳實施例揭露如上，然其 亚非用以限定本發明’任何熟習此技藝者，在不脫離本發明之 :神和範圍内，當可作各種之更動與潤飾，因此本發明之保護 视圍當視後附之申請專利範圍所界定者為準。 ^The TW2073PA 8 1260189 is etched to form the substrate outer layer line 26. Finally, a solder mask is formed on the outer layer line 26, and the first solder layer 27a and the second solder layer 27b as shown in FIG. 1K are respectively formed on the patterned first conductive layer 24 and patterned. On the second conductive layer 25. According to the manufacturing method described in the above embodiments, an element, particularly a passive component such as a capacitor, an inductor or a resistor, can be stably embedded in the substrate. The embedded π-piece substrate has many advantages. For example, embedding a passive component in a limited substrate space can not only reduce the thickness of the overall module, but also add more space to construct the active component to enhance the module. Feature. Furthermore, since the passive components are buried in the substrate, the solder joints of the circuit board are greatly reduced, and unnecessary parasitic effects due to high frequencies are reduced, thereby improving the electrical response of the RF module at high frequencies, and increasing the module fabrication and The yield and reliability of the assembly; also due to these advantages, the garment is greatly reduced. In conclusion, the present invention has been disclosed in a preferred embodiment as described above, but it is intended to limit the invention to any skilled person skilled in the art without departing from the scope of the invention. The various modifications and refinements are therefore intended to be in accordance with the scope of the appended claims. ^
【圖式簡單說明】 一較佳實施例之内埋元件之 第1Α〜1Κ圖繪示依照本發明 基板之製造方法。BRIEF DESCRIPTION OF THE DRAWINGS A first embodiment of a buried device of a preferred embodiment illustrates a method of fabricating a substrate in accordance with the present invention.
TW2073PA 9 1260189 【主要元件符號說明】 I 〇 :芯板 101 :第一表面 102 ··第二表面 II :芯板上之導電層 12 :内層線路 1 3 :容置空間 14 :元件 142 :電極TW2073PA 9 1260189 [Description of main component symbols] I 〇 : Core board 101 : First surface 102 · Second surface II : Conductive layer on core board 12 : Inner layer line 1 3 : accommodating space 14 : Element 142 : Electrode
15 ： 第一介電層 16 ·· 第二介電層 17 ： 第一離形紙 18 ·· 第二離形紙 19 ： 孔洞 21 ·· 通孔 23 ·· 導電薄膜 24 ： 第一導電層 25 ： 第二導電層 26 ： 外層線路 27 ： 防銲層 27a :第一銲料層 27b :第二銲料層 1015 : First dielectric layer 16 · Second dielectric layer 17 : First release paper 18 · Second release paper 19 : Hole 21 · Through hole 23 · Conductive film 24 : First conductive layer 25 : Second conductive layer 26 : Outer layer 27 : solder resist layer 27 a : first solder layer 27 b : second solder layer 10
TW2073PATW2073PA