12 9 8 今 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種基板製程，且特別是有關於一種 内埋元件之基板製程。 【先前技術】 一般而言，線路基板主要是由多層圖案化線路層 (patterned circuit layer )以及介電層（dielectric layer )交 替疊合所構成。其中，圖案化線路層是由銅箔層（c〇pper foil)經過微影與蝕刻製程定義形成，而介電層配置於圖案 化線路層之間，用以隔離兩相鄰之圖案化線路層。此外， 相鄰之圖案化線路層之間是透過貫穿介電層的導電通孔 (plating through hole，PTH )或導電孔道（conductive via ) 而彼此電性連接。最後，在線路基板的表面配置各種電子 元件（例如主動元件或被動元件），並藉由内部線路之電 路設計而達到電子訊號傳遞（electrical signal propagation) 之目的。 叹有對於電子產品應具有輕薄短小攜 一内埋元件，如可埋设於線路基板之内部的 達到電子產品薄型化之目^線路基板表面之佈線面積，以 程示之:種内埋元件之基板的製 層η。具有-第—介===: c/e 一表面112a的線路層114以及一位於第一介電層112之另 一表面112b的線路層116。 然後，如圖1B所示，利用機械鑽孔或雷射鑽孔於核 〜層110中形成一貫孔（through hole) 11 〇a並且將一内埋 元件102放置於貫孔11 〇a中，其中内埋元件IQ:具有兩電 極102a。接著，如圖1C所示，分別於第一介電層112之 表面112a與表面112b上形成一第一疊合層12〇與一第一 豐合層130，其中第一疊合層120包括一線路層I】。以及 一第二介電層124,第二疊合層130則包括一線路層132 以及日-第三介電層134，且第二介電層124與第三介電層 134是分別朝向線路層114與線路層116。 曰 •接者’請參考圖1D ’形成至少一導電通孔刚 個導電孔道106，其中導電通孔刚貫 /、 核心層110與第人层成巧仏 且〇層120、 =一且σ層 使件線路層122與線路層 m過導電通孔104彼此電性連接。之後“ 線路層U2,與圖案化線 ς =成圖木化 即可透過這 2 32内埋泰2之兩電極 之基層132，紐連接。如此，即完朗埋元件 然而，在上诚由 _ 應用雷射鑽孔或是機二:：板^二中 内埋元件配置於貫孔、、杉^ 3中形成一貝孔，再將 元件配置於其中之牛⑯。先於核心層中形成貫孔再將内埋 ^驟不僅較為複雜且耗費較多時間及成 6 12989朴doc/e 本。此外，_元件f透過導電孔道舆線路# 如此將會增加線喊板的整 連接。 另-個需要改善的_。低祕基板的厚度是 【發明内容】 本發明之目的是提供一 化内埋元件之基板製程。 種内埋元件之基板製程 ，以簡 種内埋元件之基板製 本發明之另一目的是提供一 程，以降低基板之整體厚度。 為達上述或是其他目的，本發明提出一種内埋元件之 基板製程，其包括下列步驟。錢，提供—内埋元件與_ 支撐板，並將内埋元件置放於支撐板之一表面上，其中内 埋元件具有至少一電極。然後，於支撐板之表面上形成一 第一介電層，第一介電層具有一第一表面及一與其相對之 第二表面，且第一介電層暴露出内埋元件。接著，移除支 撐板。之後’利用數位贺墨印刷技術（Digital Inkjet Printing Technology)於第一介電層之第一表面及第二表面上分別 形成一第一線路層與一第二線路層，其中第一線路層及/ 或第二線路層與電極電性連接。 在一實施例中，内埋元件例如是主動元件或是被動元 件。 在一實施例中，支撐板例如是一玻璃板或是一聚對苯 二酸乙稀酯膜（Polyethylene Terephthalate film，PET film)。 在一實施例中，形成第一介電層之方式例如是塗佈或 129894私 doc/e 印刷。 在一實施例中，形成第一介電層之後，本發明例如4 使第一介電層與内埋元件之表面平整（levd)。 曰 在一貫施例中，形成第一線路層與第二線路層之材 包括一高分子材料以及分佈於高分子材料中之多數個導+ 粒子。 、 在-實施例中’形成第-線路層與第二線路層之 例如是一導電高分子材料。 在Λ把例中，形成弟一線路層與第二線路層之後， 本發明可以於第—介電層之第—表面與第二表面上分別形 成-第-銲罩層（s〇lder mask)與_第二鲜罩層，其中第 一銲罩層暴露iH至少部分第-線路層，而f二銲罩層暴露 出至少部分第二線路層。接著’於第—銲罩層所暴露之^ 少部分乐-線路層上形成-第-抗氧化層 J層所暴露之至少部分第二線路層上形成一第二 滑0 ^^闕巾，形成第-抗氧切與第二抗氧化層的 別在第-銲罩層所暴露之至少部分第一線路層 ί/H弟二銲罩層所暴露之至少部分第二線路層上電鐘一 在一實施例中，形成第一線路層蛊 本發明可以於第一線路層與第二線路居^路^之4 ， 之一第-抗氧化層與圖案化之-第二別形成圖案化 第-介電層之第-表面及第二表面上&切。之後，於 刀別形成一第一銲罩 I29894Ad〇c/e 層與一第二銲罩層，其中第一銲罩層覆蓋第一線路層，並 暴露出第一抗氧化層，而第二銲罩層覆蓋第二線路層，並 暴露出第二抗氧化層。 在一實施例中，形成第一線路層與第二線路層之後， 本發明可以利用數位喷墨印刷技術於第一線路層上形成至 少一第一疊合層，第一疊合層包括一第二介電層及位於第 二介電層上之一第三線路層，其中第二介電層配置於相鄰 之二線路層之間。 在一實施例中，形成第一疊合層之後，本發明可以於 最外層之第三線路層上形成一銲罩層，其中録罩層暴露出 至少部分第三線路層。接著，於銲罩層所暴露之至少部分 第三線路層上形成一抗氧化層，而形成抗氧化層的方法例 如是分別於銲罩層所暴露之至少部分第三線路層上電鍍一 鎳/金層。 在一實施例中，形成第一疊合層之後，本發明可以 於最外層之第三線路層上形成圖案化之一抗氧化層。接 著，在第二介電層上形成一銲罩層，其中銲罩層覆蓋第三 線路層，並暴露出抗氧化層。 在一實施例中，形成第一疊合層之後，本發明可以利 用數位喷墨印刷技術於第二線路層上形成至少一第二疊合 層，第二疊合層包括一第三介電層及位於第三介電層上之 一第四線路層，其中第三介電層配置於相鄰之二線路層之 間。 在一實施例中，形成第二疊合層之後，本發明可以於 Ι298^441^άοο/6 取外層之第四線路層上形成一鲜罩層，Α 至）、部分第四線路層。之後，在銲罩層所層恭露出 第四線路層上形成_抗氧化層，而形成抗少部分 如是分別於銲罩層所Α 匕層的方法例 鎳/金層。*曰所恭路之至少部分弟四線路層上電链一 在一實施例中，形成第二疊合層之 、 最外層之第四線 ★月可以於 於第三介電成圖案化之—抗氧化層。接著， 層，並暴露出抗氧化層。s ^干罩層设盖弟四線路 於*上„將_元件置放於支撐板之表面上，接著 1 %2面上形成介電層，其中此介電層暴露出内埋 」。ί 續板之後，再數㈣墨印刷技術於介 电盾之表面上形祕路層。由於本發明是直接數位嗔 墨2刷技缺介電層之表面上形成線路層，因此，可有效 地簡化内埋元件之基板製程，且降低其製作成本 。此外， 由於内埋元件無需透過導電通孔即可直接與線路層電性連 接，因此，可使基板具有較薄之整體厚度。 一為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說 明如下。 【實施方式】 圖2Α至圖2Ε繪示為本發明第一實施例之内埋元件之 基板的製程示意圖。首先，請參考圖2α，提供一内埋元件 202與一支撐板210，並將内埋元件2〇2置放於支撐板21〇 10 1298doc/e 之一表面210a上，其中内埋元件202具有至少_電極 202a(本實施例之内埋元件202具有二電極202a)。上=之 内埋元件202例如是主動元件或是被動元件，而支撐板21〇 例如是一玻璃板或是一聚對苯二酸乙烯酯膜。 然後，如圖2B所示，於支撐板210之表面21 〇a上形 成一第一介電層220，其中第一介電層220具有一第一表 面220a及一與其相對之第二表面22〇b，且第一介電層22^ 暴露出内埋元件202。舉例來說，形成第_介電層22〇之 方式例如是塗佈、印刷或是其他適當方式。在本實施例中， 為能使第一介電層220與内埋元件2〇2之表面平整，因此 在形成第-介電層22G之後，例如可以應用數位喷墨 於第-介電層220上形成一層薄的介電層，使第一介带芦 220與内埋元件202之表面平整（如圖2C所示）。接二 圖2D所示，移除支撐板21〇。 之後，如圖2£所示，利用數位噴墨印刷技術於第一 „電層220之第-表面22〇a及第二表面2鳥 7”第-線路f 222與-第二線路層故，而此第一二: 及:線路層224會與内埋元件2〇2之電極施電性 連接，如此，即元成基本的具有内埋元件之 在本實施例中，形成第一線路 :、衣。 材料例如是一導_=層 =於高分刪巾之⑽崎 2粒子例如是姉子或是鋼粒子），而上述料導 細 由數位喷墨印刷技術形成於第一介電層22(Γ的第-表; 9 8 ^oc^e 220a與第二表面22〇b之後，須再叙 以形成第-線路層222與第二線二 (CUnng)處理， 術之先於介電層上形成金屬線路層Ί二相較於習知技 術來定義出圖案化線路層的方式:本:二=及蝕刻技 喷墨印刷技術於介電層之兩側利:數位 喷墨印刷技術定義出的線路層具^ ^且，數位 個基板可達到薄型化之要求。 /專之尽度，進而使整 可利成上述_元件之基㈣製作流程後，更 成銲罩第—介電層22G兩側的線路層上形 Π二= 蒦線路層免於受損及受潮。 後再利用_=^==_之電鑛線，之 上形忐浐麵几 、、、路層222和第二線路層224 圖3A至圖3δ綠示為預先在基板上保留 簡弟一介電層上依序形成鮮罩層及抗氧化層之 ❿ 首先’如圖3Α所示，在第一介帝 :成I;: 222與第二線路層224(請參考圖 :第=Γ步於第—介電層220之第-表面‘ 罩第—鮮罩層230與一第二銲 -i肺=本貝施例中’第一銲罩層230暴露出部分第 層故，以作亦暴露出部分第二線路 之間⑽、“Γ 其電子元件（如晶片、被動元件） u連接的媒介’其中第—鲜罩層23〇與第二鮮軍層 12 1298944^〇咖 240例如是經由微影及蝕刻技術來暴露出部分第一線路岸 222與部分第二線路層224。 θ 八从接著’如圖3Β所示，於第一銲罩層23〇所暴露之部 1線路層222上形成一第一抗氧化層25〇，並且在 2:0戶斤暴露之部分第二線路層224上形成-第二BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate process, and more particularly to a substrate process for a buried component. [Prior Art] In general, a circuit substrate is mainly composed of a plurality of patterned circuit layers and a dielectric layer alternately stacked. Wherein, the patterned circuit layer is formed by a copper foil layer (c〇pper foil) through a lithography and etching process, and a dielectric layer is disposed between the patterned circuit layers for isolating two adjacent patterned circuit layers. . In addition, the adjacent patterned circuit layers are electrically connected to each other through a conductive through hole (PTH) or a conductive via extending through the dielectric layer. Finally, various electronic components (such as active components or passive components) are disposed on the surface of the circuit substrate, and the electrical signal propagation is achieved by circuit design of the internal wiring. It is sighed that the electronic product should have a light and short carrying a buried component, such as a wiring area that can be embedded in the inside of the circuit substrate to achieve thinning of the electronic product, and the circuit board surface of the substrate is embedded in the circuit. Layer η. A circuit layer 114 having a surface 112a and a circuit layer 116 on the other surface 112b of the first dielectric layer 112. Then, as shown in FIG. 1B, a through hole 11 〇a is formed in the core layer 110 by mechanical drilling or laser drilling, and an embedded component 102 is placed in the through hole 11 〇a, wherein The buried element IQ: has two electrodes 102a. Next, as shown in FIG. 1C, a first stacked layer 12 and a first rich layer 130 are formed on the surface 112a and the surface 112b of the first dielectric layer 112, wherein the first stacked layer 120 includes a first layer Line layer I]. And a second dielectric layer 124, the second stacked layer 130 includes a circuit layer 132 and a third-third dielectric layer 134, and the second dielectric layer 124 and the third dielectric layer 134 are respectively facing the circuit layer. 114 and circuit layer 116.接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接 接The wiring layer 122 and the wiring layer m are electrically connected to each other through the conductive vias 104. After that, "the circuit layer U2, and the patterned line ς = can be formed into the base layer 132 of the two electrodes buried in the 2 32, and the new layer is connected. Thus, the burying component is completed. Application of laser drilling or machine 2:: plate ^ two embedded components are arranged in the through hole, cedar ^ 3 to form a shell hole, and then the components are placed in the cattle 16 . Before the formation of the core layer It is not only complicated but also takes a lot of time to make the hole buried. It is also a doc/e book. In addition, the _ component f passes through the conductive hole 舆 line #. This will increase the whole connection of the line board. The invention is directed to providing a substrate process for a buried component. A substrate process for implanting a component, a substrate of a simple embedded component, and another substrate of the present invention One objective is to provide a process to reduce the overall thickness of the substrate. To achieve the above or other objects, the present invention provides a substrate process for embedding components, which comprises the following steps. Money, providing - embedded components and _ support plates, And placing the embedded component on the support plate a surface, wherein the embedded component has at least one electrode. Then, a first dielectric layer is formed on the surface of the support plate, the first dielectric layer has a first surface and a second surface opposite thereto, and A dielectric layer exposes the buried component. Then, the support plate is removed. Then, a digital Inkjet Printing Technology is used to form a first surface on the first surface and the second surface of the first dielectric layer. a circuit layer and a second circuit layer, wherein the first circuit layer and/or the second circuit layer are electrically connected to the electrodes. In an embodiment, the embedded component is, for example, an active component or a passive component. The support plate is, for example, a glass plate or a polyethylene terephthalate film (PET film). In one embodiment, the first dielectric layer is formed by, for example, coating or 129894. Private doc/e printing. In one embodiment, after forming the first dielectric layer, the present invention, for example, 4 planarizes the surface of the first dielectric layer and the embedded component. One circuit layer The material of the second circuit layer comprises a polymer material and a plurality of conductive particles distributed in the polymer material. In the embodiment, the forming of the first circuit layer and the second circuit layer is, for example, a conductive polymer material. In the example, after forming the circuit layer and the second circuit layer, the present invention may form a -first solder mask layer on the first surface and the second surface of the first dielectric layer. And a second fresh cover layer, wherein the first solder mask layer exposes at least a portion of the first circuit layer of the iH, and the f solder mask layer exposes at least a portion of the second circuit layer. Then the 'the first solder mask layer is exposed ^ a part of the music layer formed on the circuit layer - the at least part of the second circuit layer exposed on the layer J of the anti-oxidation layer forms a second sliding film to form a first anti-oxidation layer and a second oxidation-resistant layer And at least a portion of the second circuit layer on which the at least a portion of the first circuit layer exposed by the first solder mask layer is exposed. In one embodiment, the first circuit layer is formed. The invention can be used in the first circuit layer and the second circuit, and the first anti-oxidation layer The patterning - to form a patterned second respectively - of the first dielectric layer - an upper surface and a second surface & cut. Thereafter, a first solder mask I29894Ad〇c/e layer and a second solder mask layer are formed on the blade, wherein the first solder mask layer covers the first circuit layer and exposes the first oxidation resistant layer, and the second soldering layer The cover layer covers the second circuit layer and exposes the second oxidation resistant layer. In one embodiment, after forming the first circuit layer and the second circuit layer, the present invention can form at least one first stacked layer on the first circuit layer by using a digital inkjet printing technique, and the first stacked layer includes a first And a second dielectric layer on the second dielectric layer, wherein the second dielectric layer is disposed between the adjacent two circuit layers. In one embodiment, after forming the first laminate layer, the present invention can form a solder mask layer on the third circuit layer of the outermost layer, wherein the mask layer exposes at least a portion of the third wiring layer. Next, an oxidation resistant layer is formed on at least a portion of the third wiring layer exposed by the solder mask layer, and the method of forming the oxidation resistant layer is, for example, plating a nickel on at least a portion of the third wiring layer exposed by the solder mask layer. Gold layer. In one embodiment, after forming the first laminate layer, the present invention can form a patterned one of the oxidation resistant layers on the third wiring layer of the outermost layer. Next, a solder mask layer is formed on the second dielectric layer, wherein the solder mask layer covers the third wiring layer and exposes the oxidation resistant layer. In one embodiment, after forming the first stacked layer, the present invention can form at least one second stacked layer on the second wiring layer by using a digital inkjet printing technique, and the second laminated layer includes a third dielectric layer. And a fourth circuit layer on the third dielectric layer, wherein the third dielectric layer is disposed between the adjacent two circuit layers. In an embodiment, after forming the second laminated layer, the present invention may form a fresh cover layer, a portion of the fourth circuit layer on the fourth circuit layer of the outer layer of Ι298^441^άοο/6. Thereafter, an _anti-oxidation layer is formed on the fourth wiring layer on the layer of the solder mask layer, and a nickel/gold layer which is a resistive layer which is a layer of the solder mask layer is formed. * At least part of the fourth circuit layer of the Christine Road, in one embodiment, the fourth layer of the outermost layer of the second laminated layer can be patterned in the third dielectric - Antioxidant layer. Next, the layer is exposed and the antioxidant layer is exposed. s ^ dry cover layer is set up on the fourth line of the _ _ component placed on the surface of the support plate, then a dielectric layer is formed on the 1% 2 surface, wherein the dielectric layer is exposed to bury. ί After the slab is renewed, a few (4) ink printing techniques are used to shape the road layer on the surface of the dielectric shield. Since the present invention is a circuit layer formed on the surface of the direct digital ink-removing dielectric layer, the substrate process of the embedded component can be effectively simplified, and the manufacturing cost thereof can be reduced. In addition, since the embedded component can be directly electrically connected to the wiring layer without passing through the conductive via, the substrate can have a thin overall thickness. The above and other objects, features, and advantages of the present invention will become more fully understood from [Embodiment] FIG. 2A to FIG. 2B are schematic diagrams showing a process of a substrate of a buried component according to a first embodiment of the present invention. First, referring to FIG. 2α, a buried component 202 and a support plate 210 are provided, and the embedded component 2〇2 is placed on one surface 210a of the support plate 21〇10 1298doc/e, wherein the embedded component 202 has At least the _ electrode 202a (the buried element 202 of the present embodiment has the two electrodes 202a). The buried component 202 is, for example, an active component or a passive component, and the support plate 21 is, for example, a glass plate or a polyethylene terephthalate film. Then, as shown in FIG. 2B, a first dielectric layer 220 is formed on the surface 21 〇a of the support plate 210. The first dielectric layer 220 has a first surface 220a and a second surface 22 opposite thereto. b, and the first dielectric layer 22 is exposed to the buried component 202. For example, the manner in which the first dielectric layer 22 is formed is, for example, coating, printing, or other suitable means. In this embodiment, in order to make the surface of the first dielectric layer 220 and the buried device 2〇2 flat, after the formation of the first dielectric layer 22G, for example, digital inkjet can be applied to the first dielectric layer 220. A thin dielectric layer is formed thereon to planarize the surface of the first tape reed 220 and the embedded component 202 (as shown in FIG. 2C). Next, as shown in Fig. 2D, the support plate 21 is removed. Thereafter, as shown in FIG. 2, digital inkjet printing technology is used on the first surface 22a of the first electric layer 220 and the second surface 2 bird 7" first line f 222 and - second circuit layer, And the first two: and: the circuit layer 224 is electrically connected to the electrode of the embedded component 2〇2, so that the element has a buried component, and in the embodiment, the first line is formed: clothes. The material is, for example, a conductive layer = a high-density smear (10), such as a scorpion or a steel particle, and the material is finely formed by a digital inkjet printing technique on the first dielectric layer 22 (Γ After the first table - 9 8 ^ oc ^ e 220a and the second surface 22 〇 b, must be repeated to form the first line layer 222 and the second line two (CUnng) processing, before the formation of the dielectric layer The metal circuit layer Ί two phase defines the pattern of the circuit layer compared to the prior art: this: two = and etching technology inkjet printing technology on both sides of the dielectric layer: the line defined by digital inkjet printing technology The layer has ^ ^ and the number of substrates can be thinned. /Specialty, so that the whole can be made into the above-mentioned _ component base (four) production process, further into the welding hood - dielectric layer 22G The shape of the circuit layer is =2 = 蒦 the circuit layer is protected from damage and moisture. After that, the _=^==_ electric ore line is used, and the upper surface layer, the road layer 222 and the second circuit layer are used. 224 Figure 3A to Figure 3 δ green is shown in advance to form a fresh cover layer and an anti-oxidation layer on the substrate on the substrate. First, as shown in Figure 3, at the first Jiedi: I;: 222 and the second circuit layer 224 (please refer to the figure: the first step - the first surface of the dielectric layer 220 - the cover - the fresh cover layer 230 and a second weld - i lung In the example of Benbe, the first solder mask layer 230 exposes a portion of the first layer so as to expose a portion of the second line (10), "the medium through which the electronic components (such as wafers, passive components) are connected] The first fresh layer 23 〇 and the second fresh layer 12 1298944 〇 240 are exposed, for example, by lithography and etching techniques to expose a portion of the first line bank 222 and a portion of the second line layer 224. θ eight from the next ' As shown in FIG. 3A, a first anti-oxidation layer 25A is formed on the portion 1 of the first solder mask layer 23, and is formed on a portion of the second wiring layer 224 exposed by 2:0 jin. -second
Si觸二的’以防止第—線路層222及第二線路層224 妾觸到4而產生氧化的情形。在此實施例中，第叶 及第二抗氧化層⑽例如是由—鎳/金層‘ 及抗= = 兩側之表面上形成銲罩層 樣可以在線路層上形成板保留電鍍線，而同 一種在圖2E中所示圖4A至圖4B繪示為另 作流程圖。首先，如圖f^形成銲罩層及抗氧化層之製 與第二線路層224(如m 9P斤!"，在形成第一線路層222 層222與第二線路層1不）之後，可以先於第一線路 化層250,與圖案化之—μ 別形成圖案化之一第一抗氧 第一抗氧化層250,與圖抗f化層260,，其中圖案化之 由微影及蝕刻技術所之第一抗氧化層260,例如是經 於第一介電層220之第—出來的。之後，如圖4Β所示， 別形成-第-銲罩層第二表面220b上分 銲罩層230覆蓋第一線路声、乐一杯罩層240,其中第一 250,，而第二銲罩層^，並暴露出第一抗氧化層 覆盍第二線路層224，並暴露出 129894和〇^ C層260’。使用者可依據不同的使用需求，僅於 化層^層220其中一側之表面上依序形成銲罩層及抗氧 其故^ A至圖5 F繪示為本發明第二實施例之内埋元件之 程不意圖。第二實施例之内埋元件之基板製程是 Hi—實施例所述之第-線路層222與第二線路層 ^作後，進：步在内埋树之基板上形成其他線路 ^程/。下文將詳細描述第二實施例之内埋元件之基板 百先，請參考圖5A，在形成第一線路層222與第二 請參考圖2E)之後，本實施例可以利用數位喷 ^刷技術於第一線路層222上形成一第一疊合層謂（圖 1個），f 一叠合層270包括一第二介電層Μ及 + ;罘一介電層272上之一第三線路層274，其中第二介 电層272配置於相鄰之二線路層（第一線路層奶*第三線 ^層274)之間。請參考圖5Β，在形成第一疊合層^之 ，，於最外層之第三線路層274上形成一銲罩層Μ，盆 中銲罩層276暴露出部分第三線路層274。接著，如圖冗 二二於鮮罩層276所暴露之部分第三線路層274上形成 抗氧化層278，而形成抗氧化層278的方法例如是分別 ^銲罩層276所暴露之部分第三線路層274上電鑛一鎳/ =層。與圖4A至圖4B所綠示之基板製程相同，本實施例 2先於第三線路層274上形成圖案化之抗氧化層挪， 妾著於第一”电層272上形成鮮罩層276 ;本發明對於在 14 線路化層及銲罩層之順序不作任何限制。 應用利用數位噴墨印刷技術 更步 疊合層。請參考圖5D,利用數 二-弟二®合層，其中第二疊合層280包括 居^^-2!2及位於第三介電層282上之一第四線路 二 弟二介電層282是配置於相鄰之二線路層（第二 舆第三線路層284)之間。在形成第：疊合層‘ (如圖5E所示），其中銲罩層286暴露出部^第二 秦路層284。之後’如圖5F所示，於銲罩層286所暴露之 部分第四線路層284上形成一抗氧化層288，而形成抗氧 化層288的方法例如是分別於銲罩層286所暴露之部分第 四線路層284上電鍍一鎳/金層。當然，本發明亦可先於第 四線路層284上形成圖案化之抗氧化層288，接著於第三 介電層282上形成銲罩層286(與圖4A至圖4B所繪示之基 板製程相同）。 承上所述，本發明亦可僅於第一介電層之一侧形成一 璺合層，並經由微影及蝕刻技術來完成内埋元件之基板製 程，上述實施例僅為舉例之用，本發明在此並不做任何限 制0 綜上所述’本發明是先將内埋元件置放於支撐板之表 面上’接著於支撐板之表面上形成介電層，其中此介電層 暴露出内埋元件。在移除支撐板之後，再利用數位喷墨印 15 1298944^0 •c/e 侧成線路層，以完成内埋元件之The susceptor of the Si touch is prevented from being oxidized by preventing the first wiring layer 222 and the second wiring layer 224 from contacting the fourth wiring layer 224. In this embodiment, the first leaf and the second oxidation resistant layer (10) are formed by, for example, forming a solder mask layer on the surface of both the nickel-gold layer and the anti-== sides, and forming a plate-retaining plating line on the wiring layer, and The same type of FIG. 4A to FIG. 4B shown in FIG. 2E is illustrated as another flow chart. First, as shown in FIG. 12, a solder mask layer and an anti-oxidation layer are formed and the second wiring layer 224 (eg, m 9P jin!", after the first wiring layer 222 layer 222 and the second wiring layer 1 are formed), A first anti-oxidation first anti-oxidation layer 250 may be patterned prior to the first wiring layer 250 and patterned, and the anti-f-layer 260 may be patterned, wherein the pattern is lithographically The first anti-oxidation layer 260 of the etching technique is, for example, first through the first dielectric layer 220. Thereafter, as shown in FIG. 4A, the solder mask layer 230 is formed on the second surface 220b of the second solder cap layer to cover the first line sound, the music cup cover 240, wherein the first 250, and the second solder mask layer And exposing the first anti-oxidation layer to cover the second wiring layer 224 and exposing 129894 and the C layer 260'. According to different usage requirements, the user can sequentially form a solder mask layer on the surface of one side of the layer 220 and resist oxidation. FIG. 5 F is shown in the second embodiment of the present invention. The process of burying components is not intended. In the substrate process of the buried component of the second embodiment, after the first-line layer 222 and the second circuit layer described in the Hi-embodiment, the other steps are formed on the substrate embedded in the tree. Hereinafter, the substrate of the embedded component of the second embodiment will be described in detail. Referring to FIG. 5A, after forming the first circuit layer 222 and the second reference FIG. 2E, the embodiment can utilize the digital inkjet technique. A first laminated layer (FIG. 1) is formed on the first circuit layer 222, and the f-stack layer 270 includes a second dielectric layer + and a + a third circuit layer on the dielectric layer 272. 274, wherein the second dielectric layer 272 is disposed between two adjacent circuit layers (the first circuit layer milk * third wire layer 274). Referring to FIG. 5A, in forming the first stacked layer, a solder mask layer is formed on the third wiring layer 274 of the outermost layer, and the solder mask layer 276 in the basin exposes a portion of the third wiring layer 274. Next, as shown in FIG. 22, an oxidation resistant layer 278 is formed on a portion of the third wiring layer 274 exposed by the fresh mask layer 276, and the method of forming the oxidation resistant layer 278 is, for example, separately soldering the exposed portion of the mask layer 276 to a third portion. The circuit layer 274 is energized with a nickel/= layer. Similar to the substrate process shown in FIG. 4A to FIG. 4B, the second embodiment forms a patterned anti-oxidation layer on the third circuit layer 274, and forms a fresh cap layer 276 on the first "electric layer 272". The present invention does not impose any restrictions on the order of the 14-line layer and the solder mask layer. The application uses digital inkjet printing technology to further laminate layers. Please refer to Figure 5D, using the number two-di-two layer, the second The laminated layer 280 includes a ^^-2!2 and the fourth dielectric layer 282 on the third dielectric layer 282 is disposed on the adjacent two circuit layers (the second third circuit layer) Between 284), in forming a: superposed layer ' (as shown in FIG. 5E), wherein the solder mask layer 286 exposes the second Qin road layer 284. Thereafter, as shown in FIG. 5F, in the solder mask layer 286 An anti-oxidation layer 288 is formed on a portion of the exposed fourth wiring layer 284, and the anti-oxidation layer 288 is formed by, for example, plating a nickel/gold layer on a portion of the fourth wiring layer 284 exposed by the solder mask layer 286. Of course, the present invention may also form a patterned anti-oxidation layer 288 on the fourth circuit layer 284, followed by a shape on the third dielectric layer 282. The solder mask layer 286 is the same as the substrate process shown in FIG. 4A to FIG. 4B. As described above, the present invention can also form a bonding layer only on one side of the first dielectric layer, and through the lithography and The etching process is used to complete the substrate process of the embedded component. The above embodiment is for example only, and the present invention does not impose any limitation here. In summary, the present invention first places the embedded component on the surface of the support plate. The upper layer is then formed on the surface of the support plate, wherein the dielectric layer exposes the buried component. After the support plate is removed, the digital inkjet printing 15 1298944^0 •c/e side is used to form the circuit layer. To complete the embedded components
-二㈣是將_元件置放於切板上广再 =τ出上述内埋元件之介電層。如此，即可不U 化基板的製作流程，並降低其製作成本。貝孔切 面上用數t噴墨印刷技術於介電層之表 透過導+、gl予又乂，專之線路層，再加上内埋元件盔需 透過w通孔即可直接與線 =而 述製程所製作而成之具有内埋元件的:且==2上 厚度，如此，使得庫用:〕土板/、有較溥之整體 的產品設計要求用此基板之電子產品可符合輕薄短小 雖然本發明已以較佳實施例 =發明:任何熟習此技藝者，在不脫離:發 内/可作些許之更動與潤飾，因此本發明之；蒦 乾圍當視後附之申請專利範圍所界定者為準。“之保護 【圖式簡單說明】 程示Γ至圖1喻為習知之—種内埋元件之基板的製 基板繞示為本發明第一實施例之内埋元件之 ，3Α至圖3Β綠示為預先在基板 弟—介電層上依序形成㈣層及抗氧化層之 16 129894^ doc/e 圖4A至圖4B繪示為另一種在圖2E中所示之基板上 形成銲罩層及抗氧化層之製作流程圖。 圖5A至圖5F繪示為本發明第二實施例之内埋元件之 基板的製程示意圖。 【主要元件符號說明】 102 :内埋元件 102a :電極 104 :導電通孔 106 :導電孔道 110 :核心層 110a :貫孔 112 :第一介電層 112a、112b :表面 114、116 :線路層 120 :第一疊合層 122 :線路層 122’ ：圖案化線路層 124 :第二介電層 130 :第二疊合層· 132 :線路層 132’ ：圖案化線路層 134 :第三介電層 202 :内埋元件 202a :電極 210 :支撐板 210a :表面 220 :第一介電層 220a ··第一表面 220b :第二表面 222 :第一線路層 224 :第二線路層 230 :第一銲罩層 240 :第二銲罩 250、250’ ：第一抗氧化層 260、260’ ：第二抗氧化層 270 :第一疊合層 272 :第二介電層 274 :第三線路層 276 :銲罩層 278 :抗氧化層 280 :第二疊合層 282 :第三介電層 284 ··第四線路層 286 :銲罩層 288 :抗氧化層- two (four) is to place the _ component on the cutting board and then τ out the dielectric layer of the embedded component. In this way, the manufacturing process of the substrate can be eliminated, and the manufacturing cost can be reduced. The bet hole cut surface is printed by the number t inkjet printing technology on the surface of the dielectric layer through the lead +, gl and 乂, the special circuit layer, plus the embedded component helmet can pass through the through hole to directly with the line = The manufacturing process has embedded components: and ==2 upper thickness, so that the library uses:] earth plate /, the overall product design requires that the electronic products of the substrate can be light and short Although the invention has been described in the preferred embodiment of the invention: any person skilled in the art, without departing from the hair, may make some modifications and retouching, and thus the present invention; The definition is subject to change. "Protection of a simple description of the drawings" is shown in Fig. 1 as a conventional substrate-based substrate of a buried component is shown as a buried component of the first embodiment of the present invention, 3Α to 3 Forming a (four) layer and an anti-oxidation layer in advance on the substrate-dielectric layer. FIG. 4A to FIG. 4B are diagrams showing another formation of a solder mask layer on the substrate shown in FIG. 2E and FIG. 5A to FIG. 5F are schematic diagrams showing the process of the substrate of the embedded component according to the second embodiment of the present invention. [Main component symbol description] 102: embedded component 102a: electrode 104: conductive Hole 106: conductive via 110: core layer 110a: via 112: first dielectric layer 112a, 112b: surface 114, 116: wiring layer 120: first stacked layer 122: wiring layer 122': patterned wiring layer 124 : second dielectric layer 130 : second stacked layer · 132 : wiring layer 132 ′ : patterned wiring layer 134 : third dielectric layer 202 : buried component 202 a : electrode 210 : support plate 210 a : surface 220 : a dielectric layer 220a · a first surface 220b: a second surface 222: a first circuit layer 224: a second line 230: first solder mask layer 240: second solder mask 250, 250': first oxidation resistant layer 260, 260': second anti-oxidation layer 270: first laminated layer 272: second dielectric layer 274: Three circuit layer 276: solder mask layer 278: oxidation resistant layer 280: second laminated layer 282: third dielectric layer 284 · fourth wiring layer 286: solder mask layer 288: oxidation resistant layer