TWI334761B - Circuit connecting process and structure thereof - Google Patents
Circuit connecting process and structure thereof Download PDFInfo
- Publication number
- TWI334761B TWI334761B TW96121495A TW96121495A TWI334761B TW I334761 B TWI334761 B TW I334761B TW 96121495 A TW96121495 A TW 96121495A TW 96121495 A TW96121495 A TW 96121495A TW I334761 B TWI334761 B TW I334761B
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- conductive
- pad
- hole
- conductive layer
- Prior art date
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Description
1334761 0612003 23125twf.doc/p 九、發明說明: 【發明所屬之技術領域】 本發明是有關於一種線路板,且特別是有關於—種線 路連接製程及其結構。 ' 【先前技術】1334761 0612003 23125twf.doc/p IX. Description of the Invention: [Technical Field] The present invention relates to a circuit board, and more particularly to a line connection process and a structure thereof. 'Prior art
線路連接結構常用於雙面板以及多層板型態的印刷 電路板上,用以電性連接不同層之圖案化線路層。如 專=公告第J23U66號「線路連接結構及其製程」所提及 子由於導電孔多由雷射成孔製程所形成,其成 為—致、然而其深度過深(約超過_陴),使 付^電孔之縱橫比(深度/寬度的比例)過高,導 = 導電孔内。當導電膜之厚度繼續增力; 在罪近導電孔之頂部的導電 孔之底部附近將會產生、且在*近導電 線路連接結構及其製輕專利提出了 1The line connection structure is commonly used on double-panel and multi-layer board type printed circuit boards for electrically connecting patterned layer layers of different layers. As mentioned in the special announcement No. J23U66 "Line Connection Structure and Its Process", since the conductive holes are mostly formed by the laser hole forming process, they become, but the depth is too deep (about _陴). The aspect ratio (depth/width ratio) of the ^ hole is too high, and the conduction = inside the conductive hole. When the thickness of the conductive film continues to increase; near the bottom of the conductive hole at the top of the sin-conducting hole, a near-conducting line connection structure and its light-weight patent are proposed.
孔的深度相對錢,使打變之情況下,二導電 地防止鍍膜產生空孔或氣泡。電孔之縱橫比較小,以有效 然而,上述專利僅能掩 低一導電孔的深度仍有一h、個塾的厚度,對於降 雙面板之一側作為導電墊疋,限制。此外,上述專利是以 適用於埋入式線路。 ,只適用於非埋入式線路,無法 【發明内容】 本發明提供一 種線路連接製 程及其結構,可降低二The depth of the hole is relative to the money, so that in the case of a change, the conductive film prevents voids or bubbles from being formed. The vertical and horizontal holes of the electric holes are relatively small to be effective. However, the above patent can only cover the depth of a conductive hole and still have a thickness of one h, and the thickness of one side of the double-panel is limited as a conductive pad. In addition, the above patents are applicable to buried circuits. It is only applicable to non-buried lines, and it is not possible. [Invention] The present invention provides a line connection process and a structure thereof, which can reduce two
1334761 0612003 23125twf.doc/p 案化線路層之間的導電孔的深度 或氣泡》 本!,明提出-種線路連接製程,包括下列步驟首 ^提:-連接層,該連接層包括一核心層以 孔墊及第二孔藝於該核心二第-1334761 0612003 23125twf.doc/p Depth or bubble of conductive holes between circuit layers. This is a circuit connection process, including the following steps: - connection layer, the connection layer includes a core layer With the hole pad and the second hole in the core two -
二孔塾電性導通;提供-第一導塾 介電層、至少一笛矛寺冤層、至少一第一 -導電層、該第〜介二:層:及-第二導電層;壓合該第 該第二導電層,二二r連接層、該第二介電層以及 貫穿該第-導電層反丄對應於該第-孔墊,形成 於該第二孔塾介電層之-第-開孔;對應 之-第二開孔;形層以及該第二介電層 形成-第-導電挺 料於該第-開孔中,以 孔中,以形成一第二導電‘。一第二導電材料於該第二開The second hole is electrically conductive; providing a first conductive dielectric layer, at least one whistling layer, at least one first conductive layer, the second dielectric layer: and the second conductive layer; The second conductive layer, the second and second dielectric layers, and the second conductive layer and the first conductive layer are opposite to the first hole, and are formed on the second dielectric layer. - an opening; corresponding to the second opening; the layer and the second dielectric layer forming a -first conductive material in the first opening, in the hole to form a second conductive '. a second conductive material in the second opening
以防止鍍膜時產生空孔 :介構二”接層、一第 層。連接層具有1心層 Ί層以及—第二導電 連接墊貫過該核心層,,y=獨立連接墊,該獨立 該核心層的二表面上,立贫二有第一孔墊及第二孔墊於 導通。第-介電層配置在核心:c該第二孔墊電性 該第一孔墊上之〜第_:#带一表面,且具有配置在 之另-表®,且具有配in’第二介電層配置在核心層 柱。第一導電層配置在該第孔塾上之一第―二導電 層上,並與該第一導電 1334761 0612003 23125twf.doc/p 柱電性連接。第二導電層配置在該第二介電層上,並與該 第二導電柱電性連接。 在本發明之一實施例中,第一開孔以及第二開孔包括 以雷射成孔、電漿蝕孔或機械鑽孔所形成。 在本發明之一實施例中,第一導電層具有對應於第一 孔墊之一第一環形墊,該第一環形墊於壓合該第一導電層 於該第一介電層上時内埋於該第一介電層中。此外,第二 導電層具有對應於該第二孔墊之一第二環形墊,該第二環 形墊於壓合該第二導電層於該第二介電層上時内埋於該第 二介電層中。 本發明又提出一種線路連接製程,包括下列步驟:首 先,提供一連接層,該連接層包括一核心層以及至少一獨 立連接墊,該獨立連接墊貫過該核心層,並分別形成一第 一孔墊及一第二孔墊於該核心層的二表面上,其中該第一 孔墊與該第二孔墊電性導通;接著,提供一第一導電層、 至少一第一介電層、至少一第二介電層以及一第二導電 層;壓合該第一導電層、該第一介電層、該連接層、該第 二介電層以及該第二導電層,以形成複數板;對應於該第 一孔墊,形成貫穿該第一導電層以及該第一介電層之一第 一開孔;對應於該第二孔墊,形成貫穿該第二導電層以及 該第二介電層之一第二開孔;之後,形成一第一導電材料 於該第一開孔中,以形成一第一導電柱;形成一第二導電 材料於該第二開孔中,以形成一第二導電柱。 本發明又提出一種線路連接結構,包括一連接層、一 7 1334761 0612003 23125twf.doc/p 第一介電層、一第二介電 — 電層。連接層具有一核心層 層以及—第二導 立連接塾貫過該核心層,並二f立連接塾’該獨 孔塾於該核心層的二表面二第2塾及一第二 有配置在該第-孔塾上之該核心層之一表面,且具 在該核心層之另一表面,且::導電柱。f二介電層配置 第二導電柱。第一導電居罢、酉己置在該第二孔墊上之- 弟,柱電性連接。第二導電 ^與该 上,並與該第二導電柱電性連接。s ^罘一"電層 本發明因採用設有獨立連接 位於二圖案化線路層之間的 運^曰〜性導通 度及縱橫比相對較小,進 % ’口此一導電柱的深 提喊膜的良率。 為讓本發明之上述特徵和 舉較佳實施例,並配人所 ” b£ ’下文特 【實施方式】 所附圖式’作詳細說明如下。 圖1A〜圖1?是本發明第—每 其結構的示意圖。衫相:^例之線路連接製程及 直勺杯y ^ 考 錢提供—連接層100, A括一核心層110以及一獨立連 核心層110為樹炉m入+ , (數里不拘)。In order to prevent the occurrence of voids during the coating: a two-layer layer, a first layer, the connecting layer has a core layer and a second conductive connection layer through the core layer, y = independent connection pad, the independent On the two surfaces of the core layer, the first hole pad and the second hole pad are turned on. The first dielectric layer is disposed at the core: c the second hole pad is electrically connected to the first hole pad. #带一表面, and having a further configuration, and having a second dielectric layer disposed in the core layer pillar. The first conductive layer is disposed on one of the second conductive layers on the first aperture And electrically connected to the first conductive 1334761 0612003 23125 twf.doc/p column. The second conductive layer is disposed on the second dielectric layer and electrically connected to the second conductive pillar. In one embodiment, the first opening and the second opening comprise a laser hole, a plasma hole or a mechanical hole. In one embodiment of the invention, the first conductive layer has a first hole pad a first annular pad, the first annular pad is buried in the first when the first conductive layer is pressed onto the first dielectric layer In addition, the second conductive layer has a second annular pad corresponding to the second hole pad, and the second annular pad is embedded in the second conductive layer on the second dielectric layer. In the second dielectric layer, the present invention further provides a line connection process, comprising the steps of: firstly, providing a connection layer, the connection layer comprising a core layer and at least one independent connection pad, the independent connection pad passing through the core a first hole pad and a second hole pad are respectively formed on the two surfaces of the core layer, wherein the first hole pad is electrically connected to the second hole pad; then, a first conductive layer is provided, At least one first dielectric layer, at least one second dielectric layer, and a second conductive layer; pressing the first conductive layer, the first dielectric layer, the connection layer, the second dielectric layer, and the first a second conductive layer to form a plurality of plates; corresponding to the first hole pad, forming a first opening penetrating through the first conductive layer and the first dielectric layer; corresponding to the second hole pad, forming through the first a second conductive layer and a second opening of one of the second dielectric layers; thereafter, Forming a first conductive material in the first opening to form a first conductive pillar; forming a second conductive material in the second opening to form a second conductive pillar. The invention further provides a line connection The structure comprises a connection layer, a 7 1334761 0612003 23125 twf.doc/p first dielectric layer, a second dielectric layer, the connection layer has a core layer and a second conductive connection passes through the core a layer, and a two-hole connection, the single hole is formed on the surface of the core layer, and the second surface of the core layer is disposed on the surface of the core layer The other surface of the layer, and:: a conductive column. The second dielectric layer is disposed on the second dielectric layer. The first conductive layer is placed on the second hole pad, and the column is electrically connected. ^ is connected to and electrically connected to the second conductive post. s ^罘一"Electrical layer The present invention uses a separate connection between the two patterned circuit layers to achieve a relatively small degree of conduction and an aspect ratio, and a deep rise of the conductive column Shouting the film's yield. The above features and preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings. FIG. 1A to FIG. 1 are the first embodiment of the present invention. Schematic diagram of the structure: the shirt phase: ^ example of the line connection process and the straight cup y ^ test money provided - the connection layer 100, A includes a core layer 110 and an independent core layer 110 for the tree furnace m into +, (number Not limited.)
==:層110的上、下表面,並分別形成Z 弟一孔墊124於核心層π〇 ⑴、Π4上。由圖1Α可知,第一孔 =面 之間的距離即為核心層„〇的厚度。在本實二= W4/61 0612003 23125twf.doc/p 覆有第-孔墊i22以及第二孔塾124的連 以雙面銅絲板經_化形成多個成對㈣一 ^ ㈣及第二孔塾m,每一對第—孔二= ,再以貫穿核心層110的導電柱126電 圖1A所示之獨立連接墊12〇。 咬按以形成==: the upper and lower surfaces of the layer 110, and respectively form a Z-hole pad 124 on the core layers π 〇 (1), Π 4. It can be seen from Fig. 1 that the distance between the first hole=face is the thickness of the core layer 。. In the present two = W4/61 0612003 23125 twf.doc/p, the first hole pad i22 and the second hole 124 are covered. The two-sided copper wire plate is formed into a plurality of pairs (four) one (four) and two holes 塾m, each pair of first holes φ, and then the conductive pillars 126 penetrating the core layer 110 are electrically connected to FIG. 1A. Show the independent connection pad 12〇. Press to form
接著’請參寺圖1B以及圖]c,提供 :3〇、-第-介電層14G、—第二介電層15Q以及一第^ J層160,並碰合第-導電層130、第一介電層‘導 、接層刚、第二介電層15G以及第 s 對應於弟-孔墊122,而第二導電層副更可具有第二環Then, please refer to FIG. 1B and FIG. 2c to provide: 3〇, −-dielectric layer 14G, second dielectric layer 15Q, and a first J layer 160, and contact the first conductive layer 130, A dielectric layer 'conductive, junction layer, second dielectric layer 15G and s corresponding to the via-hole pad 122, and the second conductive layer pair may have a second ring
:,丄62’其對應於第二孔塾124。第一環形塾132在壓合 里於第一介電層140中,且第二環形墊162在 1過各中也可内埋於第二介電層150中,因而形成具有 埋線路的雙面⑯細。在本實施例中,由於連接層動 卞為连接第一、第二導電層130、160之媒介,並不需要 特別製作線路圖案,因此第一/第二孔墊122、124的面積 ^當調整而大於或等於第—/第二環形墊132、162的面 積,如此可放寬層間對位的要求。 /接著,請麥考圖1D,當完成雙面板200之壓合步驟 二,、’對?於第一孔墊122的位置,形成貫穿第一導電層 以及第一介電層140之第一開孔134,以使第一開孔 的底部顯露出第—孔墊H同樣,對應於第二孔墊 4的位置,形成貫穿第二導電層16〇以及第二介電層15〇 0612003 23125twf.doc/p 之第二開孔164,以使第二開?丨] ㈣。形成第-、二: = = ==:機械鑽孔等,但其他光_技二:, 丄 62' corresponds to the second aperture 124. The first annular crucible 132 is pressed into the first dielectric layer 140, and the second annular pad 162 can also be buried in the second dielectric layer 150 in one pass, thereby forming a double with buried lines. Face 16 is fine. In this embodiment, since the connection layer is a medium for connecting the first and second conductive layers 130 and 160, and no special line pattern is required, the area of the first/second aperture pads 122 and 124 is adjusted. And greater than or equal to the area of the / / second annular pads 132, 162, so that the requirements for interlayer alignment can be relaxed. / Next, please take McCaw 1D, when the double-panel 200 is pressed, step 2, 'right? a first opening 134 is formed through the first conductive layer and the first dielectric layer 140 at a position of the first hole pad 122 such that the bottom of the first opening exposes the first hole pad H, corresponding to the second The position of the hole pad 4 forms a second opening 164 extending through the second conductive layer 16 and the second dielectric layer 15〇0612003 23125twf.doc/p to make the second opening?丨] (4). Form the first -, second: = = ==: mechanical drilling, etc., but other light
值得注意的是,苐-導電層⑽上的第 於形成第-開孔m之後,輸於第—開孔134之^端3。2 由圖id可知,以雷射成孔的第一開孔134的寬产 上與第-㈣墊132的孔徑相當。由於雷射所形成的第一 開孔134的寬度一致’因此當第二開孔134的深度變小, 其縱橫比(深度/寬度的比例)也會隨之縮小。麸二,本 明與習知技術不同的是,第-導電層n◦與第二導電層⑽ 之間有三層介電層,即第-介電層14Q、核心層ιι〇 二介電層150,因此第一導電層13〇與第二導電層16〇之 間的間距D比習知只有二層介電層的間距來得大,以有效 解決漏電流的問題。另外’本發明採用雙面設有第一/第一 孔塾的獨立連接墊12〇,可使第-、第二開孔134、164 ^ 深度變小’且第-、第二開孔134、164的深度僅為第一導 的三分之一或更 突破習知技術的瓶頸及限制 接著,請參考圖1E以及圖lF,將第—導電材料填入 於第-開孔134中,以形成與第-導電層13()電性連接之 第-導電柱136。同樣’將第二導電材料填人於第二開孔 164中,以形成與第二導電層160電性連接之第二導電柱 166。第―、第二導電材料例如是鋼、銀或電阻小於等二導 10 1334761 0612003 23125twf.doc/p 電層及電性連接塾的適當材料。 形成第一、第二導電柱136、16 性^導電材料於第一導電層13〇、第二導電層^疋^ =墊122以及第二孔墊124上(如圖1£所示)、或是選 擇性電鍍/噴印導電材料於第„、f二㈣134、^ =上,鍍=程之後,更可進行銅層薄化 i之圖案以及第二線路圖案’如圖1F所 衣/ 132以及第二環形墊162。鋼層薄化的步 二面5刻第-、第二導電層130,及其上方 的电材枓,或選擇性蝕刻第一、第二導電芦 及其上方的導騎料卿成所需⑽路圖案/ 1D的1連接製程配合圖式的說明依序完成圖 本锁田且有H Ε的鑛孔以及圖1F之銅層薄化,但 化而變更其製程的步 式。此外,本發明雖以雙層之第一、第二導電層m、湖 為例’但亦可_在單層之導電層,而任^ 不經=案化製程以作為完整的導電接二1 時:本發:月不限定應用在埋入式線路上,亦可應I】 入式(外路的)線路或兩者組合之線路。〜 在上述第一實施例中’雙面覆有第一孔 二孔塾m的連接層100亦可變 ^ 圖2之變化例:第-孔塾1⑽第二孔二:ί 1334761 0612003 23125twf.doc/p 電柱126’偏離第一開孔】34鱼 樣,第一開孔134與第-開孔164的中心轴。同 甘〜 開】64的位置亦可適當改變, 其餘駄構如同弟—實施例所述,在此不再贅述。 3A_ : 3F :本發明第二實施例之線路連接製程及 m、茶考圖3A,首先提供一連接層, 其包括一核心層310以及一獨立連接塾320(數量不拘),It should be noted that after the first opening on the conductive layer (10) is formed, the first opening is formed by the laser. The wide yield of 134 is comparable to the aperture of the (-)th pad 132. Since the width of the first opening 134 formed by the laser is uniform, the aspect ratio (depth/width ratio) is also reduced as the depth of the second opening 134 becomes smaller. Bran II, in contrast to the prior art, there are three dielectric layers between the first conductive layer n◦ and the second conductive layer (10), that is, the first dielectric layer 14Q and the core layer ιι 〇 dielectric layer 150 Therefore, the spacing D between the first conductive layer 13 〇 and the second conductive layer 16 得 is larger than that of the conventional two-layer dielectric layer to effectively solve the problem of leakage current. In addition, the present invention adopts a separate connection pad 12 设有 provided with a first/first aperture on both sides, so that the first and second apertures 134, 164 ^ can be reduced in depth ' and the first and second apertures 134, The depth of 164 is only one third of the first lead or more than the bottleneck and limitation of the prior art. Next, referring to FIG. 1E and FIG. 1F, the first conductive material is filled in the first opening 134 to form A first conductive pillar 136 electrically connected to the first conductive layer 13(). Similarly, a second conductive material is filled in the second opening 164 to form a second conductive pillar 166 electrically connected to the second conductive layer 160. The first and second conductive materials are, for example, steel, silver or a suitable material having a resistance less than that of the second conductor 10 1334761 0612003 23125 twf.doc/p electrical layer and electrical connection. Forming first and second conductive pillars 136, 16 conductive material on the first conductive layer 13〇, the second conductive layer 垫^=pad 122, and the second hole pad 124 (as shown in FIG. 1), or The selective electroplating/printing of the conductive material is performed on the first, second, fourth, fourth, and fourth, after the plating, the copper layer is thinned, and the second line pattern is as shown in FIG. 1F/132. a second annular pad 162. The second layer of the steel layer is thinned by the second surface, the second conductive layer 130, and the electrical material 上方 above it, or the first and second conductive reeds are selectively etched. The required (10) road pattern / 1D 1 connection process with the description of the pattern is completed in sequence. The mine hole with H Ε and the copper layer of Figure 1F are thinned, but the process of changing the process is changed. In addition, although the present invention uses the first and second conductive layers m and the lake of the double layer as an example, it can also be used as a conductive layer of a single layer, and can be used as a complete conductive connection. 2:1: This issue: The month is not limited to the application on the buried line, and may also be the I-in (external) line or a combination of the two. ~ In the above first embodiment 'The connection layer 100 with the first hole and the second hole 塾m on both sides can also be changed. The variation of FIG. 2: the first hole 塾 1 (10) the second hole two: ί 1334761 0612003 23125 twf.doc / p The electric column 126' deviates from the first Open hole] 34 fish sample, the first opening 134 and the central axis of the first opening 164. The position of the same to the opening 64 can also be changed as appropriate, and the rest of the structure is as described in the embodiment - the embodiment is no longer 3A_ : 3F: The line connection process of the second embodiment of the present invention, and the m and tea test chart 3A, firstly provide a connection layer, which includes a core layer 310 and an independent connection port 320 (the number is not limited).
^同,认卿之具有獨立連接墊12Q之連接層·。接 者,在圖3A中,提佯—笛 道+ a, ㈣一--人+ 導電層330、一第一介電層 弟一"電層350以及一第二導電層36〇,並接續壓 合第-導電層330、第—介電層⑽、連接層·、第二介 電層351以及第二導電層36G,以形成雙面板400。^ Same as the connection layer of the independent connection pad 12Q. In FIG. 3A, the 佯-- flute + a, (four) one--person + conductive layer 330, a first dielectric layer, a " electrical layer 350 and a second conductive layer 36〇, and continue The first conductive layer 330, the first dielectric layer (10), the connection layer, the second dielectric layer 351, and the second conductive layer 36G are laminated to form the double panel 400.
/接著,請茶考圖3C,當完成雙面板4〇〇之壓合步驟 之後’對應於第-孔墊322的位置,形成貫穿第一導電層 330以及第-介電層34〇之第—開孔334,以使第一開孔 334的底部顯露出第—孔墊322。同樣,對應於第二孔墊 324的位置,形成貫穿第二導電層36〇以及第二介電層35〇 之第二開孔364,以使第二開孔364的底部顯露出第二孔 墊324。形成第—、第二開孔334、364的方式例如是雷射 成孔、電漿钱孔或機械鑽孔等,但其他光蝕刻技術或化學 蝕刻技術亦可適用。 值得注意的是,本發明採用雙面設有第一/第二孔墊的 獨立連接墊320,可使第一、第二開孔334、364的深度變 小’以突破習知技術的瓶頸及限制,進而提高鍍膜的良率。 接著’請參考圖3D,將第一導電材料填入於第一開 1334761 0612003 23125twf.d〇c/p 孔334中,以形成與第一導電層330電性連接之第一導電 柱336。同樣,將第二導電材料填入於第二開孔3料中, 以开》成與第二導電層360電性連接之第二導電柱366。第 一、第二導電材料例如是銅、銀或電阻小於等於導電層及 電性連接墊的適當材料。 之後,請參考圖3E,圖案化第一導電層33〇及其上方 之導電材料,以形成一第一線路圖案33〇a,而第一線路圖 案330a例如是外露的銲墊及/或線路。此外,圖荦化第二 導電層360及其上方的導電材料’以形成一第二線路圖; 3圖而4^線路曾圖案遍例如是外露的鲜塾及/或線路。 了圖木化弟—導電層330及第二導電層360上方的導雷 外,本發明另一實施例中亦可選擇性保留或減除導 的干有本發明之線路連接結構的多層線路板 時,;:以二實施例其中之一的線路連接製程 i如〜4縣方式分別製作至少—上層圖宰化線 接結構線路53。於本發明之線路連 多層線路板丨四層、六層或八層等 如是晶片、電咸、電上層圖案化線路wo例 明之線路連接結構 的配,,用以傳遞電=球、電膠、接卿等介面 知上所述’本發明之線路連接製程及其結構具有下列 13 H > 1334761 0612003 23125twf.doc/p 優點: (1) 本發明可,%§小雷射成孔的縱橫比,防止获胺吐 產生空孔或氣泡。 (2) 本發明可採用雙面設有第一/第二孔墊的獨立 接墊可電性導通位於二圖案化線路層之間的二導電柱,因 ^二導電柱的深度及縱橫比相對較小,進而提高鍍膜的良 (3) 本發明亦可採用單面設有獨立連接墊的連 層,可使開孔的深度變小,以縮小開孔的縱橫比。 (4) 連接層除了電性連接上、下導電層之外, :==_性’以及增加上、下導電層之間的間距二 導電声孔的深度僅為第—導電層與第二 頸及限制。 皮白知技術的瓶 在不 神和範_,當可作些許之更動與 本鲞月已以較佳實施例揭露如上,麸f i 限定本發明,任何所屬技術領域中具有通常知識=用以 潤飾 因此本發明之保護 為準 範圍當視後附之申請專利範圍所界定者 【圖式簡單說明】 其結是本侧—實施狀鱗連接製程及 圖2是第一實施例之變化例的示意圖。 14 1334761 0612003 23125twf.doc/p 圖3A〜圖3E 其結構的示意圖。 是本發明第二實施例之線路連接製程及 的示種具有本發明之線路連接結構的多層線路板 【主要元件符號說明】/ Next, please refer to FIG. 3C for tea, and after completing the pressing step of the double panel 4', corresponding to the position of the first-hole pad 322, forming the first through the first conductive layer 330 and the first-dielectric layer 34- The hole 334 is opened such that the bottom of the first opening 334 exposes the first hole pad 322. Similarly, corresponding to the position of the second hole pad 324, the second opening 364 is formed through the second conductive layer 36 and the second dielectric layer 35, so that the bottom of the second opening 364 reveals the second hole pad. 324. The manner of forming the first and second openings 334, 364 is, for example, a laser hole, a plasma hole or a mechanical hole, but other photolithography techniques or chemical etching techniques are also applicable. It should be noted that the present invention adopts a separate connection pad 320 with a first/second aperture pad on both sides, which can make the depths of the first and second openings 334 and 364 smaller. Limitation, which in turn increases the yield of the coating. Next, referring to FIG. 3D, the first conductive material is filled in the first opening 1334761 0612003 23125 twf.d〇c/p hole 334 to form a first conductive pillar 336 electrically connected to the first conductive layer 330. Similarly, the second conductive material is filled in the second opening 3 to form a second conductive pillar 366 electrically connected to the second conductive layer 360. The first and second conductive materials are, for example, copper, silver or a suitable material having a resistance equal to or less than the conductive layer and the electrical connection pads. Thereafter, referring to FIG. 3E, the first conductive layer 33 and the conductive material thereon are patterned to form a first line pattern 33A, and the first line pattern 330a is, for example, an exposed pad and/or line. In addition, the second conductive layer 360 and the conductive material ′ above it are patterned to form a second circuit pattern; and the lines are patterned such as exposed fresh sputum and/or lines. In another embodiment of the present invention, a multilayer circuit board having the line connection structure of the present invention may be selectively retained or subtracted in another embodiment of the present invention. At the time of the line connection process i of one of the two embodiments, at least the upper layer of the slaughter line connection structure line 53 is produced. In the circuit of the present invention, the four-layer, six-layer or eight-layer circuit of the multi-layer circuit board, such as the wafer, the electric salt, and the electric upper layer patterned circuit, are arranged to transmit the electric ball, the electric glue, The interface and the structure of the present invention have the following 13 H > 1334761 0612003 23125 twf.doc/p advantages: (1) The present invention can, the % aspect ratio of the small laser into a hole To prevent the production of pores or bubbles by the amine. (2) The present invention can be electrically connected to two conductive pillars located between two patterned circuit layers by using independent pads provided with first/second aperture pads on both sides, because the depth and aspect ratio of the two conductive pillars are relatively Smaller, and thus better to improve the coating (3) The present invention can also be used to connect layers with independent connecting pads on one side, so that the depth of the opening can be reduced to reduce the aspect ratio of the opening. (4) In addition to electrically connecting the upper and lower conductive layers, the connection layer is :==_sity' and increases the spacing between the upper and lower conductive layers. The depth of the conductive holes is only the first conductive layer and the second neck. And restrictions. The bottle of the whispering technique is not sacred, and when some changes can be made and the present invention has been disclosed in the preferred embodiment as above, the bran defines the invention, and any prior art has the usual knowledge = to retouch The protection of the present invention is based on the scope of the patent application, which is defined by the scope of the patent application. [Brief Description] The present invention is the present side-implementation scale connection process and FIG. 2 is a schematic view of a variation of the first embodiment. 14 1334761 0612003 23125twf.doc/p FIG. 3A to FIG. 3E are schematic views of the structure thereof. The present invention relates to a line connection process of the second embodiment of the present invention and a multilayer circuit board having the line connection structure of the present invention.
100 :連接層 112、114 :上、下表面 122 :第一孔塾 126 ' 126’ :導電柱 132 :第一環形墊 136 :第一導電柱 150 :第二介電層 162 .弟一壞形塾 166 :第二導電桂 300 :連接層 32〇 :獨立連辏墊 330a.弟一線略圖案 336:導電桎 μ 350 :第二介電層 360a .第一缘雖圖案 366 :第二導電柱” 510 :上層圖素化線路 530:下層圖衆化線路 W :寬度 110 :核心層 120 :獨立連接塾 124 :第二孔墊 130 :第一導電層 134 :第一開孔 140 :第一介電層 160 :第二導電層 164 :第二開孔 200、40〇 :雙面板 310 .核心層 330 :第一導電層 334 :第一開孔 340 :第—介電層 360 :第二導電層 364 :第二開孔 500 :多層線路板 520 ·線路連接結構 D :間距 15100: connection layer 112, 114: upper and lower surface 122: first aperture 塾 126 ' 126': conductive pillar 132: first annular pad 136: first conductive pillar 150: second dielectric layer 162. Shape 166: second conductive guinea 300: connecting layer 32 〇: independent 辏 pad 330a. 弟一略略 pattern 336: conductive 桎μ 350: second dielectric layer 360a. first edge although pattern 366: second conductive column 510: upper layerization line 530: lower layer picture line W: width 110: core layer 120: independent connection 塾 124: second hole pad 130: first conductive layer 134: first opening 140: first Electrical layer 160: second conductive layer 164: second opening 200, 40: double panel 310. core layer 330: first conductive layer 334: first opening 340: first dielectric layer 360: second conductive layer 364: second opening 500: multilayer wiring board 520 · line connection structure D: spacing 15
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW96121495A TWI334761B (en) | 2007-06-14 | 2007-06-14 | Circuit connecting process and structure thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW96121495A TWI334761B (en) | 2007-06-14 | 2007-06-14 | Circuit connecting process and structure thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200850105A TW200850105A (en) | 2008-12-16 |
TWI334761B true TWI334761B (en) | 2010-12-11 |
Family
ID=44212055
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW96121495A TWI334761B (en) | 2007-06-14 | 2007-06-14 | Circuit connecting process and structure thereof |
Country Status (1)
Country | Link |
---|---|
TW (1) | TWI334761B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI505757B (en) * | 2012-07-19 | 2015-10-21 | A circuit board with embedded components |
-
2007
- 2007-06-14 TW TW96121495A patent/TWI334761B/en active
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI505757B (en) * | 2012-07-19 | 2015-10-21 | A circuit board with embedded components |
Also Published As
Publication number | Publication date |
---|---|
TW200850105A (en) | 2008-12-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI283152B (en) | Structure of circuit board and method for fabricating the same | |
JP2017143254A (en) | Wiring board having lamination and embedded capacitor and manufacturing method | |
TWI380756B (en) | Circuit structure and process thereof | |
TW200623318A (en) | Method for fabricating a multi-layer circuit board with fine pitch | |
TW200921816A (en) | Method of making multi-layer package board of copper nuclear layer | |
TW200836606A (en) | Circuit board process | |
TW201414379A (en) | Printed circuit board and method for manufacturing same | |
JP4256603B2 (en) | Manufacturing method of laminated wiring board | |
JP2006100789A (en) | Manufacturing method of electric wiring structure | |
TWI272886B (en) | Substrate with multi-layer PTH and method for forming the multi-layer PTH | |
TWI678952B (en) | Circuit board structure and manufacturing method thereof | |
TW200922429A (en) | Structure and manufacturing method of (with embedded component) multilayer circuit board | |
TWI334761B (en) | Circuit connecting process and structure thereof | |
TW200948238A (en) | Structure and manufacturing process for circuit board | |
TWI298941B (en) | Method of fabricating substrate with embedded component therein | |
TWI306729B (en) | Method for making circuit board and multi-layer substrate with plated through hole structure | |
TWI556704B (en) | Non - welded multilayer circuit board and its manufacturing method | |
JPH03285398A (en) | Interlayer conduction structure of multilayer circuit board and method of forming the same | |
TW200845846A (en) | Three-dimensional patterned structure of circuit board and process thereof | |
CN109757037A (en) | High density circuit board and preparation method thereof | |
TW200623997A (en) | Method for fabricating a multi-layer packaging substrate | |
CN104768319B (en) | Printed circuit board and manufacturing method thereof | |
CN101351091B (en) | Line connection technique and structure thereof | |
CN107205311A (en) | Without weld pad multilayer circuit board and preparation method thereof | |
JP2009060151A (en) | Production process of laminated wiring board |