TWI505757B - A circuit board with embedded components - Google Patents
A circuit board with embedded components Download PDFInfo
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- TWI505757B TWI505757B TW101126000A TW101126000A TWI505757B TW I505757 B TWI505757 B TW I505757B TW 101126000 A TW101126000 A TW 101126000A TW 101126000 A TW101126000 A TW 101126000A TW I505757 B TWI505757 B TW I505757B
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Description
本發明係有關一種具有內埋元件之電路板,特別是指一種應用於內埋元件,可縮小接點面積,有利於高密度以及細線路製作之電路板。The invention relates to a circuit board with embedded components, in particular to a circuit board which is applied to an embedded component, can reduce the contact area, and is favorable for high density and fine circuit fabrication.
一般而言,線路基板主要是由多層經過圖案化的線路層(patterned circuit layer)以及介電層(dielectric layer)交替疊合所構成。其中,圖案化線路層是由銅箔層(copper foil)經過微影與蝕刻製程定義形成,而介電層配置於圖案化線路層之間,用以隔離圖案化線路層。此外,相疊之圖案化線路層之間是透過貫穿介電層的鍍通孔(Plating Through Hole,PTH)或導電孔道(conductive via)而彼此電性連接。最後,在線路基板的表面配置各種電子元件(主動元件、被動元件),並藉由內部線路之電路設計而達到電子訊號傳遞(electrical signal propagation)之目的。In general, the circuit substrate is mainly composed of a plurality of patterned patterned circuit layers and a dielectric layer alternately stacked. Wherein, the patterned circuit layer is formed by a copper foil layer through a lithography and etching process, and a dielectric layer is disposed between the patterned circuit layers for isolating the patterned circuit layer. In addition, the stacked patterned circuit layers are electrically connected to each other through a through hole (PTH) or a conductive via that penetrates the dielectric layer. Finally, various electronic components (active components, passive components) are disposed on the surface of the circuit substrate, and the circuit design of the internal circuit achieves the purpose of electrical signal propagation.
然而,隨著市場對於電子產品需具有輕薄短小且攜帶方便的需求,因此在目前的電子產品中,係將原先焊接於電路板的電子元件設計為可埋設於電路板之內部的一內埋元件;內埋元件電路板技術能提高被動元件效能、減少被動元件數量,並且降低被動元件佔用的電路板面積。因此,利用內埋元件電路板技術的構裝整合,可以用來取代傳統分離式被動元件,例如電容器、電阻及電感等,其優點為減少分離式被動元件的使用數量,進而降低產品的相關製作與檢測成本, 減少被動元件的銲點數目,提高產品構裝密度與可靠度等。However, as the market needs to be light, short, and portable for electronic products, in the current electronic products, the electronic components originally soldered to the circuit board are designed as an embedded component that can be buried inside the circuit board. Embedded component board technology improves passive component performance, reduces passive component count, and reduces board area occupied by passive components. Therefore, the integration of the embedded component circuit board technology can be used to replace the traditional discrete passive components, such as capacitors, resistors and inductors, which have the advantages of reducing the number of separate passive components and reducing the related production of the products. With the cost of testing, Reduce the number of solder joints of passive components, improve product density and reliability.
在內埋元件電路板技術中,為了增加佈線面積,多層電路板用上了更多的導電層及埋設被動元件用的孔洞,例如導孔(via)、埋孔(Buried vias)或盲孔(Blind vias)等。如第一圖為習有多層電路板之結構示意圖所示,該導孔11通常打穿埋設有內埋元件12之電路板13時,但因長度較長,使得填充這些導孔11而沒有形成空隙或鎖孔係有困難性的。傳統上,可使用化學鍍銅(Electroless copper),以使導孔被金屬如銅的種子層(seed layer)所襯裏,然後藉由電鍍來被覆該種子層。由於導孔的長度較長,故更難以使電鍍材料襯於或填充導孔而沒有空窩、空隙或鎖孔,該空窩、空隙或鎖孔對於導孔的導電性有不良影響,且為了維持一定的縱橫比(導孔之高度或長度與寬度或直徑的比例),其寬度或直徑相對較大,故外露於電路板之焊墊14亦相對面積較大,不利於高密度以及細線路製作。In the buried component circuit board technology, in order to increase the wiring area, the multilayer circuit board uses more conductive layers and holes for embedding passive components, such as vias, buried vias, or blind vias ( Blind vias) and so on. As shown in the first figure, the structure of the multi-layer circuit board is shown. The via hole 11 is usually pierced through the circuit board 13 in which the embedded component 12 is buried, but the length is long, so that the via holes 11 are not filled. Voids or keyholes are difficult. Conventionally, electroless copper may be used to align the via holes with a seed layer of a metal such as copper, and then coat the seed layer by electroplating. Since the length of the via hole is long, it is more difficult to make the plating material lining or filling the via hole without voids, voids or keyholes, and the void, void or keyhole has an adverse effect on the conductivity of the via hole, and Maintaining a certain aspect ratio (the height or length of the via hole and the ratio of the width or the diameter) is relatively large in width or diameter, so that the solder pads 14 exposed on the circuit board are also relatively large in area, which is disadvantageous for high density and fine lines. Production.
有鑑於此,本發明即在提供一種可應用於內埋元件,可縮小接點面積,有利於高密度以及細線路製作之電路板,為其主要目的者。In view of the above, the present invention provides a circuit board which can be applied to an embedded component, can reduce the contact area, and is advantageous for high density and fine circuit fabrication, and is its main purpose.
為達上揭目的,本發明電路板內設有至少一內埋元件,該電路板內並嵌入有至少一墊高結構體,該墊高結構體設有至少一導電通孔,可連接該電路板之接點,以解決習有因內埋元件所造成接點之距離較遠,造成導通之困難,而本發明並可縮小接孔孔徑及接點面積,有利於高密度以及細線路之 製作。In order to achieve the above, at least one embedded component is disposed in the circuit board of the present invention, and at least one pad structure is embedded in the circuit board, and the pad structure is provided with at least one conductive via hole, and the circuit can be connected The contact of the board is to solve the problem that the distance between the contacts caused by the embedded components is far, which causes the conduction, and the invention can reduce the aperture and the contact area of the hole, which is beneficial to the high density and the fine line. Production.
依據上述主要結構特徵,所述之電路板至少包含有:第一基板、第二基板、內埋元件以及墊高結構體,該第一基板相對之第一、第二表面分別設有第一、第二圖案化線路層,該第一、第二圖案化線路層設有至少一接點;該第二基板設有相對之第三、第四表面,該第四表面係設於該第一表面,並覆蓋於該第一圖案化線路層上,該第三表面並設有第三圖案化線路層,該第三圖案化線路層設有至少一接點;該內埋元件係埋設於該第二基板內,並與該接點連接;而該墊高結構體係埋設於該第二基板內,該墊高結構體設有至少一導電通孔,可連接該第一圖案化線路層與該第三圖案化線路層之接點。According to the above main structural features, the circuit board includes at least: a first substrate, a second substrate, a buried component, and a padded structure, wherein the first substrate is respectively provided with a first surface opposite to the first surface and the second surface a second patterned circuit layer, the first and second patterned circuit layers are provided with at least one contact; the second substrate is provided with opposite third and fourth surfaces, and the fourth surface is disposed on the first surface And covering the first patterned circuit layer, the third surface is provided with a third patterned circuit layer, the third patterned circuit layer is provided with at least one contact; the embedded component is embedded in the first The second substrate is embedded in the second substrate; the high structure is embedded in the second substrate, the high structure is provided with at least one conductive via, and the first patterned circuit layer and the first The junction of the three patterned circuit layers.
依據上述主要結構特徵,所述墊高結構體設有一基材,該基材相對之第五、第六表面分別設有導通線路,該導電通孔係電性連接第五、第六表面之導通線路,而該第五、第六表面之導通線路則分別與接點連接。According to the above main structural features, the pad structure is provided with a substrate, and the substrate is respectively provided with a conduction line opposite to the fifth and sixth surfaces, and the conductive via is electrically connected to the fifth and sixth surfaces. The lines, and the conductive lines of the fifth and sixth surfaces are respectively connected to the contacts.
上述之內埋元件可以為封裝完成之半導體或未封裝之裸晶片。The embedded components described above may be packaged semiconductor or unpackaged bare wafers.
依據上述主要結構特徵,所述第二基板之第三表面可進一步設有第三基板。According to the above main structural features, the third surface of the second substrate may further be provided with a third substrate.
依據上述主要結構特徵,所述內埋元件係與該第一圖案化線路層之接點相連接。According to the above main structural features, the embedded component is connected to a junction of the first patterned circuit layer.
依據上述主要結構特徵,所述第二基板可設有開口以供容置該內埋元件。According to the above main structural features, the second substrate may be provided with an opening for receiving the embedded component.
依據上述主要結構特徵,所述內埋元件以及墊高結構可 先設置於該第一表面上,再壓合一樹脂材料,覆蓋於該內埋元件以及墊高結構,而形成第二基板。According to the above main structural features, the embedded component and the height structure may be Firstly disposed on the first surface, and then press-bonding a resin material to cover the embedded component and the padding structure to form a second substrate.
本發明之特點,可參閱本案圖式及實施例之詳細說明而獲得清楚地瞭解。The features of the present invention can be clearly understood by referring to the drawings and the detailed description of the embodiments.
如第二圖本發明之電路板第一實施例結構示意圖所示,本發明之電路板20內設有至少一內埋元件21,該電路板20內並嵌入有至少一墊高結構體22,該墊高結構體22設有至少一導電通孔221,可連接該電路板上、下表面之接點30,以解決習有因上、下表面接點之距離較遠,造成導通之困難,而本發明並可縮小接點面積,有利於高密度以及細線路之製作。As shown in the second embodiment of the circuit board of the present invention, at least one embedded component 21 is disposed in the circuit board 20 of the present invention, and at least one pad structure 22 is embedded in the circuit board 20, The padded structure 22 is provided with at least one conductive through hole 221, and can be connected to the contact 30 on the upper and lower surfaces of the circuit board to solve the problem that the distance between the upper and lower surface contacts is long, and the conduction is difficult. The invention can reduce the contact area, and is advantageous for the production of high density and fine lines.
整體實施時,該電路板20至少包含有:第一基板23、第二基板24、內埋元件21以及墊高結構體22,該第一基板23相對之第一、第二表面231、232分別設有第一、第二圖案化線路層233、234,該第一、第二圖案化線路層設有至少一接點30;該第二基板24設有相對之第三、第四表面241、242,該第四表面242係設於該第一表面231,並覆蓋於該第一圖案化線路層233上,該第三表面241並設有第三圖案化線路層243,該第三圖案化線路層設有至少一接點30;該內埋元件21係埋設於該第二基板24內,並與該接點30連接;其中,該內埋元件21可以為封裝完成之半導體或未封裝之裸晶片,如圖所示之實施例中,該內埋元件21係與該第一圖案化線路層233之接點相連接。In the overall implementation, the circuit board 20 includes at least a first substrate 23, a second substrate 24, a buried component 21, and a pad structure 22, wherein the first substrate 23 is opposite to the first and second surfaces 231 and 232, respectively. The first and second patterned circuit layers are provided with at least one contact 30; the second substrate 24 is provided with opposite third and fourth surfaces 241, 242, the fourth surface 242 is disposed on the first surface 231 and covers the first patterned circuit layer 233. The third surface 241 is further provided with a third patterned circuit layer 243. The circuit layer is provided with at least one contact 30; the embedded component 21 is embedded in the second substrate 24 and connected to the contact 30; wherein the embedded component 21 can be a packaged semiconductor or unpackaged The bare wafer, as shown in the embodiment, is connected to the junction of the first patterned wiring layer 233.
而該墊高結構體22係埋設於該第二基板24內,請 同時參閱第三圖所示,該墊高結構體22設有一基材222,該基材222相對之第五、第六表面223、224分別設有導通線路225,該導電通孔221係電性連接第五、第六表面之導通線路225,該第五、第六表面之導通線路225則分別可連接該第一圖案化線路層與該第三圖案化線路層之接點30;當然,亦可如圖所示,該導通線路225與該接點30間設有導電通孔221。The pad structure 22 is embedded in the second substrate 24, please Referring to the third embodiment, the pad structure 22 is provided with a substrate 222. The substrate 222 is respectively provided with a conduction line 225 opposite to the fifth and sixth surfaces 223 and 224. The conductive via 221 is electrically connected. Connecting the fifth and sixth surface conduction lines 225, the fifth and sixth surface conduction lines 225 respectively connecting the first patterned circuit layer and the third patterned circuit layer contact 30; As shown in the figure, a conductive via 221 is defined between the conductive line 225 and the contact 30.
再者,如第四圖之第二實施例所示,該第二基板之第三表面241可進一步設有第三基板25,可增加線路配置;當然,該第一基板之第二表面或第二基板之第三表面可進一步設有其他電子元件,如第五圖之第三實施例所示,該第一基板之第二表面232可設有其他電子元件40,;亦或者該第一基板之第二表面可進一步具有內埋元件之第四基板(圖未示)。Furthermore, as shown in the second embodiment of the fourth figure, the third surface 241 of the second substrate may further be provided with a third substrate 25, which may increase the line configuration; of course, the second surface of the first substrate or the first The third surface of the second substrate may further be provided with other electronic components. As shown in the third embodiment of the fifth figure, the second surface 232 of the first substrate may be provided with other electronic components 40, or the first substrate. The second surface may further have a fourth substrate (not shown) of the embedded component.
本發明製作時,可於該第二基板特定位置處形成有開口以供容置該內埋元件;亦或者,該內埋元件以及墊高結構可先設置於該第一表面上,再壓合一樹脂材料或膠片(prepreg),覆蓋於該內埋元件以及墊高結構,而形成第二基板。When the invention is formed, an opening may be formed at a specific position of the second substrate for receiving the embedded component; or the embedded component and the height-up structure may be first disposed on the first surface, and then pressed A resin material or prepreg covers the buried component and the padding structure to form a second substrate.
本發明相較於習有電路板係具有下列優點:The present invention has the following advantages over the conventional circuit board system:
1.可解決習有因內埋元件所造成接點之距離較遠,造成導通之困難。1. It can solve the problem that the distance between the contacts caused by the embedded components is far away and the conduction is caused.
2.本發明在固定之縱橫比下可縮小接點面積,有利於高密度以及細線路之製作。2. The invention can reduce the contact area under the fixed aspect ratio, which is beneficial to the production of high density and fine lines.
3.該墊高結構體可於壓合樹脂材料形成第二基板過程中,可形成擋牆以保護內埋元件。3. The pad structure may form a retaining wall to protect the embedded component during the process of forming the second substrate by pressing the resin material.
4.該墊高結構可與元件以相同組裝方式同時以焊接或其 他導通方式安裝於第一基板之第一表面。4. The padding structure can be soldered simultaneously with the component in the same assembly manner He is mounted in a first manner on the first surface of the first substrate.
綜上所述,本發明提供內埋元件一較佳可行之多層電路板製造方法,爰依法提呈發明專利之申請;本發明之技術內容及技術特點巳揭示如上,然而熟悉本項技術之人士仍可能基於本發明之揭示而作各種不背離本案發明精神之替換及修飾。因此,本發明之保護範圍應不限於實施例所揭示者,而應包括各種不背離本發明之替換及修飾,並為以下之申請專利範圍所涵蓋。In summary, the present invention provides a method for manufacturing a multilayer circuit board which is preferably a buried component, and an application for an invention patent according to the law; the technical content and technical features of the present invention are disclosed above, but those skilled in the art It is still possible to make various substitutions and modifications without departing from the spirit of the invention. Therefore, the scope of the present invention should be construed as being limited by the scope of the appended claims
11‧‧‧導孔11‧‧‧ Guide hole
12‧‧‧內埋元件12‧‧‧ embedded components
13‧‧‧電路板13‧‧‧Circuit board
14‧‧‧焊墊14‧‧‧ solder pads
20‧‧‧電路板20‧‧‧ boards
21‧‧‧內埋元件21‧‧‧ embedded components
22‧‧‧墊高結構體22‧‧‧High structure
221‧‧‧導電通孔221‧‧‧ conductive through holes
222‧‧‧基材222‧‧‧Substrate
223‧‧‧第五表面223‧‧‧ fifth surface
224‧‧‧第六表面224‧‧‧ sixth surface
225‧‧‧導通線路225‧‧‧Connected lines
23‧‧‧第一基板23‧‧‧First substrate
231‧‧‧第一表面231‧‧‧ first surface
232‧‧‧第二表面232‧‧‧ second surface
233‧‧‧第一圖案化線路層233‧‧‧First patterned circuit layer
234‧‧‧第二圖案化線路層234‧‧‧Second patterned circuit layer
24‧‧‧第二基板24‧‧‧second substrate
241‧‧‧第三表面241‧‧‧ third surface
242‧‧‧第四表面242‧‧‧ fourth surface
243‧‧‧第三圖案化線路層243‧‧‧ Third patterned circuit layer
25‧‧‧第三基板25‧‧‧ Third substrate
30‧‧‧接點30‧‧‧Contacts
40‧‧‧電子元件40‧‧‧Electronic components
第一圖係為習有多層電路板之結構示意圖。The first figure is a schematic diagram of the structure of a multi-layer circuit board.
第二圖係為本發明中電路板之第一實施例結構示意圖。The second figure is a schematic structural view of a first embodiment of a circuit board in the present invention.
第三圖係為本發明中墊高結構體之結構放大示意圖。The third figure is an enlarged schematic view of the structure of the high structure of the present invention.
第四圖係為本發明中電路板之第二實施例結構示意圖。The fourth figure is a schematic structural view of a second embodiment of the circuit board of the present invention.
第五圖係為本發明中電路板之第三實施例結構示意圖。The fifth figure is a schematic structural view of a third embodiment of the circuit board of the present invention.
22‧‧‧墊高結構體22‧‧‧High structure
221‧‧‧導電通孔221‧‧‧ conductive through holes
222‧‧‧基材222‧‧‧Substrate
223‧‧‧第五表面223‧‧‧ fifth surface
224‧‧‧第六表面224‧‧‧ sixth surface
225‧‧‧導通線路225‧‧‧Connected lines
23‧‧‧第一基板23‧‧‧First substrate
24‧‧‧第二基板24‧‧‧second substrate
30‧‧‧接點30‧‧‧Contacts
Claims (6)
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TW101126000A TWI505757B (en) | 2012-07-19 | 2012-07-19 | A circuit board with embedded components |
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TW101126000A TWI505757B (en) | 2012-07-19 | 2012-07-19 | A circuit board with embedded components |
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TWI288592B (en) * | 2004-03-30 | 2007-10-11 | Nec Tokin Corp | Printed circuit board and manufacturing method thereof |
TWI334761B (en) * | 2007-06-14 | 2010-12-11 | Unimicron Technology Corp | Circuit connecting process and structure thereof |
TWM443934U (en) * | 2012-07-19 | 2012-12-21 | Boardtek Electronics Corp | Carrier board structure with buried electronic components |
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TW201406232A (en) | 2014-02-01 |
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