TWI632647B - Packaging process and package substrate for use in the process - Google Patents

Packaging process and package substrate for use in the process Download PDF

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Publication number
TWI632647B
TWI632647B TW105101365A TW105101365A TWI632647B TW I632647 B TWI632647 B TW I632647B TW 105101365 A TW105101365 A TW 105101365A TW 105101365 A TW105101365 A TW 105101365A TW I632647 B TWI632647 B TW I632647B
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layer
dielectric layer
patent application
scope
item
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TW105101365A
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Chinese (zh)
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TW201727840A (en
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范植文
陳嘉成
邱士超
白裕呈
洪祝寶
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矽品精密工業股份有限公司
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Priority to TW105101365A priority Critical patent/TWI632647B/en
Priority to CN201610078223.9A priority patent/CN106981469B/en
Publication of TW201727840A publication Critical patent/TW201727840A/en
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Publication of TWI632647B publication Critical patent/TWI632647B/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49579Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4821Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4839Assembly of a flat lead with an insulating support, e.g. for TAB

Abstract

一種封裝基板係包括:介電層、設於該介電層上之第一線路層、以及藉由絕緣層結合至該介電層與該第一線路層上之支撐板,以藉由該絕緣層具有浸泡溶劑後可恢復黏性之特性,故於該封裝基板完成封裝製程後,能重複使用該支撐板與該絕緣層,以避免浪費該支撐板。 A package substrate system includes a dielectric layer, a first circuit layer provided on the dielectric layer, and a support plate coupled to the dielectric layer and the first circuit layer through an insulating layer to pass the insulation through The layer has the property of recovering the viscosity after being soaked in a solvent, so after the packaging substrate completes the packaging process, the supporting board and the insulating layer can be reused to avoid wasting the supporting board.

Description

封裝製程及其所用之封裝基板 Packaging process and packaging substrate used therefor

本發明係有關一種封裝製程,尤指一種節省資源之封裝製程及其封裝基板。 The present invention relates to a packaging process, and more particularly to a packaging process and a packaging substrate that save resources.

隨著電子產業的蓬勃發展,電子產品也逐漸邁向多功能、高性能的趨勢。為了提高多層電路板之佈線精密度,業界遂發展出一種增層技術(Build-up),亦即在一核心板(Core board)之兩表面上分別以線路增層技術交互堆疊多層之介電層及線路層,並於該介電層中開設導電盲孔(Conductive via)以供上下層線路之間電性連接。進一步地,為了滿足微型化(miniaturization)的需求,係發展出無核心板(coreless)之封裝技術。 With the vigorous development of the electronics industry, electronic products are gradually moving towards the trend of multifunctional and high performance. In order to improve the wiring accuracy of multi-layer circuit boards, the industry has developed a build-up technology, that is, multiple layers of dielectric are stacked alternately on the two surfaces of a core board using line build-up technology. Layer and circuit layer, and a conductive via is provided in the dielectric layer for electrical connection between upper and lower layers. Further, in order to meet the needs of miniaturization, a coreless packaging technology has been developed.

第1圖係為習知無核心層(coreless)之封裝基板1之剖面示意圖。如第1圖所示,該封裝基板1係包括一介電層10、形成於該介電層10上、下側之第一線路層11與第二線路層12、以及形成於該介電層10上側及該第二線路層12上之防銲層13,其中,形成複數導電盲孔100於該介電層10中,以電性連接該第一與第二線路層11,12,且 該防銲層13形成有複數開孔130以露出該第二線路層12之電性接觸墊120。 FIG. 1 is a schematic cross-sectional view of a conventional coreless package substrate 1. As shown in FIG. 1, the package substrate 1 includes a dielectric layer 10, a first circuit layer 11 and a second circuit layer 12 formed on the dielectric layer 10 and a lower side thereof, and a dielectric layer formed on the dielectric layer 10. 10 and a solder mask layer 13 on the second circuit layer 12, wherein a plurality of conductive blind holes 100 are formed in the dielectric layer 10 to electrically connect the first and second circuit layers 11 and 12, and A plurality of openings 130 are formed in the solder resist layer 13 to expose the electrical contact pads 120 of the second circuit layer 12.

由於該封裝基板1係無核心層,因而其板厚較薄,故於進行封裝製程(即設置晶片)前,容易產生運送不易及板體彎翹等問題。因此,該封裝基板1之下側會保留製程耗品(即具有銅層30之硬質板3,如銅箔基板)與用以製作該第一線路層11之導電層110,以增加該封裝基板1之結構強度,而避免該封裝基板1運送不易、發生翹曲或破裂等問題。 Since the package substrate 1 has no core layer, its plate thickness is relatively thin. Therefore, problems such as difficulty in transportation and warpage of the board are easy to occur before the packaging process (that is, setting the wafer). Therefore, process consumables (that is, a hard board 3 with a copper layer 30, such as a copper foil substrate) and a conductive layer 110 used to make the first circuit layer 11 are reserved on the lower side of the package substrate 1 to increase the package substrate. The structural strength of 1 prevents the package substrate 1 from being difficult to transport, warping or cracking.

惟,習知封裝基板1於封裝製程後,會利用移除該銅層30以分離該硬質板3與該封裝基板1,故分離後之硬質板3需丟棄,因而造成該硬質板3浪費的問題。 However, it is known that after the packaging substrate 1 is packaged, the copper layer 30 is removed to separate the hard board 3 from the packaging substrate 1. Therefore, the separated hard board 3 needs to be discarded, thus causing the hard board 3 to be wasted. problem.

因此,如何克服上述習知技術的問題,實已成目前亟欲解決的課題。 Therefore, how to overcome the problems of the above-mentioned conventional technologies has become an urgent problem to be solved.

鑑於上述習知技術之種種缺失,本發明係提供一種封裝基板,係包括:介電層,係具有相對之第一表面與第二表面;第一線路層,係設於該介電層之第一表面上;以及支撐板,係藉由絕緣層以結合至該介電層之第一表面上。 In view of the various shortcomings of the above-mentioned conventional technologies, the present invention provides a package substrate including: a dielectric layer having a first surface and a second surface opposite to each other; and a first circuit layer provided in a first layer of the dielectric layer. A surface; and a support plate, which is bonded to the first surface of the dielectric layer through an insulating layer.

本發明復提供一種封裝製程,係包括:提供一前述之封裝基板;將至少一電子元件結合至該介電層之第二表面上;以及將該支撐板與該絕緣層自該介電層之第一表面上分離。 The present invention further provides a packaging process, which includes: providing a packaging substrate as described above; bonding at least one electronic component to a second surface of the dielectric layer; and supporting the support plate and the insulating layer from the dielectric layer. Separated on the first surface.

前述之封裝製程中,該封裝基板之製法係包括:提供 表面上形成有該第一線路層之一承載件;形成該介電層於該承載件及該第一線路層上,其中,該介電層係以其第一表面結合該承載件;以及將該支撐板利用該絕緣層結合於該介電層之第一表面上。 In the aforementioned packaging process, the manufacturing method of the packaging substrate includes: providing A carrier of the first circuit layer is formed on the surface; the dielectric layer is formed on the carrier and the first circuit layer, wherein the dielectric layer is bonded to the carrier by its first surface; and The supporting plate is bonded to the first surface of the dielectric layer by using the insulating layer.

前述之封裝製程中,該電子元件係為主動元件、被動元件或其二者組合。 In the aforementioned packaging process, the electronic component is an active component, a passive component, or a combination thereof.

前述之封裝製程中,該電子元件藉由複數導電元件結合至該第二表面上。 In the aforementioned packaging process, the electronic component is bonded to the second surface through a plurality of conductive components.

前述之封裝製程中,復包括自該介電層上分離該支撐板後,將該支撐板結合至另一介電層上。例如,該絕緣層浸泡於溶劑中,使該絕緣層具有黏性,以結合該另一介電層。 In the aforementioned packaging process, the method further includes separating the supporting plate from the dielectric layer, and then bonding the supporting plate to another dielectric layer. For example, the insulating layer is immersed in a solvent to make the insulating layer tacky to bind the other dielectric layer.

前述之封裝基板及封裝製程中,該第一線路層之表面係齊平或低於該介電層之第一表面。 In the aforementioned packaging substrate and packaging process, the surface of the first circuit layer is flush or lower than the first surface of the dielectric layer.

前述之封裝基板及封裝製程中,形成該支撐板之材質係為紙質基材、複合基材或FR-4基材。 In the aforementioned packaging substrate and packaging process, the material forming the supporting plate is a paper substrate, a composite substrate, or a FR-4 substrate.

前述之封裝基板及封裝製程中,形成該絕緣層之材質係為膠體,且形成該絕緣層之材質係為彈性體。 In the aforementioned packaging substrate and packaging process, the material forming the insulating layer is gel, and the material forming the insulating layer is elastomer.

前述之封裝基板及封裝製程中,該封裝基板復包括設於該介電層之第二表面上的第二線路層。該封裝基板又包括形成於該介電層中之複數導電盲孔,以藉由該些導電盲孔電性連接該第一與第二線路層。該封裝基板另包括絕緣保護層,係設於該介電層之第二表面及該第二線路層上,且該第二線路層係部分外露於該絕緣保護層。 In the aforementioned packaging substrate and packaging process, the packaging substrate further includes a second circuit layer disposed on the second surface of the dielectric layer. The package substrate further includes a plurality of conductive blind holes formed in the dielectric layer, so as to electrically connect the first and second circuit layers through the conductive blind holes. The package substrate further includes an insulation protection layer, which is disposed on the second surface of the dielectric layer and the second circuit layer, and the second circuit layer is partially exposed on the insulation protection layer.

由上可知,本發明之封裝基板及封裝製程中,係藉由該絕緣層之設計,使該絕緣層浸泡溶劑後即可恢復黏性,故相較於習知技術,本發明能重複使用該支撐板與該絕緣層,以避免習知使用支撐板後即丟棄所造成之浪廢問題。 It can be known from the above that, in the packaging substrate and the packaging process of the present invention, the design of the insulating layer allows the insulating layer to recover its viscosity after being soaked in a solvent, so the present invention can reuse the The support plate and the insulation layer are used to avoid the problem of wasting caused by the conventional use of the support plate and discarding it.

1,2‧‧‧封裝基板 1,2‧‧‧package substrate

10,20,20’‧‧‧介電層 10,20,20’‧‧‧Dielectric layer

100,200‧‧‧導電盲孔 100,200‧‧‧ conductive blind hole

11,21‧‧‧第一線路層 11,21‧‧‧First circuit layer

110‧‧‧導電層 110‧‧‧ conductive layer

12,22‧‧‧第二線路層 12,22‧‧‧Second circuit layer

120,220‧‧‧電性接觸墊 120,220‧‧‧electric contact pad

13‧‧‧防銲層 13‧‧‧Solder Mask

130,230‧‧‧開孔 130,230‧‧‧opening

20a‧‧‧第一表面 20a‧‧‧first surface

20b‧‧‧第二表面 20b‧‧‧Second surface

23‧‧‧絕緣保護層 23‧‧‧Insulation protective layer

24‧‧‧支撐板 24‧‧‧ support plate

240‧‧‧絕緣層 240‧‧‧ Insulation

3‧‧‧硬質板 3‧‧‧ rigid board

30‧‧‧銅層 30‧‧‧ Copper

4‧‧‧承載件 4‧‧‧ Bearing

40‧‧‧金屬層 40‧‧‧metal layer

40’‧‧‧銅箔 40’‧‧‧ copper foil

9‧‧‧電子封裝結構 9‧‧‧electronic package structure

90‧‧‧電子元件 90‧‧‧Electronic components

91‧‧‧導電元件 91‧‧‧ conductive element

第1圖係為習知封裝基板的剖視示意圖;第2A至2E圖係為本發明之封裝基板之製法的剖視示意圖;以及第3A至3C圖係為本發明之封裝製程的剖視示意圖。 Figure 1 is a schematic sectional view of a conventional packaging substrate; Figures 2A to 2E are schematic sectional views of a method for manufacturing a packaging substrate of the present invention; and Figures 3A to 3C are schematic sectional views of a packaging process of the present invention .

以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The following describes the implementation of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如“上”、“第一”、“第二”及“一”等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。 It should be noted that the structures, proportions, sizes, etc. shown in the drawings in this specification are only used to match the content disclosed in the specification for the understanding and reading of those skilled in the art, and are not intended to limit the implementation of the present invention. The limited conditions are not technically significant. Any modification of the structure, change of the proportional relationship, or adjustment of the size should still fall within the scope of this invention without affecting the effects and goals that can be achieved by the present invention. The technical content disclosed by the invention can be covered. At the same time, the terms such as "upper", "first", "second", and "one" cited in this specification are only for the convenience of description, and are not intended to limit the scope of the present invention. Changes or adjustments in their relative relationships shall be considered to be the scope of the present invention without substantial changes in the technical content.

第2A至2E圖係為本發明封裝基板2之製法的剖面示意圖。 Figures 2A to 2E are schematic cross-sectional views of a method for manufacturing a package substrate 2 according to the present invention.

如第2A圖所示,提供一承載件4,其中,該承載件4係為絕緣板、陶瓷板、銅箔基板或玻璃板等。 As shown in FIG. 2A, a supporting member 4 is provided. The supporting member 4 is an insulating plate, a ceramic plate, a copper foil substrate, a glass plate, or the like.

於本實施例中,該承載件4係為銅箔基板,其上、下表面具有一銅箔40’,且於各該銅箔40’上形成一金屬層40以作為導電層(seed layer),其中,該金屬層40之厚度係為2微米(μm),且該銅箔40’之厚度則為18微米(μm)。 In this embodiment, the carrier 4 is a copper foil substrate, a copper foil 40 'is provided on the upper and lower surfaces, and a metal layer 40 is formed on each of the copper foils 40' as a conductive layer. The thickness of the metal layer 40 is 2 micrometers (μm), and the thickness of the copper foil 40 'is 18 micrometers (μm).

如第2B圖所示,利用該金屬層40電鍍形成一第一線路層21於該承載件4之上、下側。 As shown in FIG. 2B, a first circuit layer 21 is formed by electroplating on the metal layer 40 above and below the carrier 4.

如第2C圖所示,形成一介電層20於該承載件4及該第一線路層21上,且該介電層20具有相對之第一表面20a與第二表面20b,使該介電層20之第一表面20a接觸結合該金屬層40,並使該第一線路層21嵌埋於該介電層20中。接著,形成一第二線路層22於該介電層20之第二表面20b上,且形成複數導電盲孔200於該介電層20中,以電性連接該第一與第二線路層21,22。 As shown in FIG. 2C, a dielectric layer 20 is formed on the carrier 4 and the first circuit layer 21, and the dielectric layer 20 has a first surface 20a and a second surface 20b opposite to each other, so that the dielectric The first surface 20 a of the layer 20 is in contact with the metal layer 40, and the first circuit layer 21 is embedded in the dielectric layer 20. Next, a second circuit layer 22 is formed on the second surface 20 b of the dielectric layer 20, and a plurality of conductive blind holes 200 are formed in the dielectric layer 20 to electrically connect the first and second circuit layers 21. ,twenty two.

於本實施例中,該介電層20之材質係為預浸材(prepreg),且該第二線路層22具有複數電性接觸墊220。 In this embodiment, the material of the dielectric layer 20 is a prepreg, and the second circuit layer 22 has a plurality of electrical contact pads 220.

再者,形成一絕緣保護層23於該介電層20之第二表面20b及該第二線路層22上,且該絕緣保護層23形成有複數開孔230,以令各該電性接觸墊220外露於各該開孔230。 Furthermore, an insulating protection layer 23 is formed on the second surface 20b of the dielectric layer 20 and the second circuit layer 22, and the insulating protection layer 23 is formed with a plurality of openings 230 so that each of the electrical contact pads 220 is exposed at each of the openings 230.

如第2D圖所示,移除該承載件4及其金屬層40與銅箔40’,以外露該介電層20之第一表面20a與該第一線路層21。 As shown in FIG. 2D, the carrier 4 and its metal layer 40 and copper foil 40 'are removed, and the first surface 20a of the dielectric layer 20 and the first circuit layer 21 are exposed.

如第2E圖所示,將一支撐板24利用一絕緣層240結合於該介電層20之第一表面20a與該第一線路層21上。 As shown in FIG. 2E, a supporting plate 24 is bonded to the first surface 20 a of the dielectric layer 20 and the first circuit layer 21 by using an insulating layer 240.

於本實施例中,形成該支撐板24之材質係為聚合物,例如,聚乙烯、聚丙烯、聚對苯二甲酸乙二酯(polyethylene terephthalate,簡稱PET)或紙質基材、複合基材或FR-4基材,且形成該絕緣層240之材質係為膠體或彈性體(elastomer),例如,丁腈橡膠(NBR)、氯丁橡膠(Neoprene)或聚矽氧橡膠聚合物(Silicone rubber compound)。具體地,該支撐板24可為PET,且該絕緣層240可為聚矽氧橡膠彈性體。 In this embodiment, the material forming the support plate 24 is a polymer, for example, polyethylene, polypropylene, polyethylene terephthalate (PET for short), a paper substrate, a composite substrate, or FR-4 substrate, and the material forming the insulating layer 240 is a colloid or an elastomer (for example, nitrile rubber (NBR), neoprene, or a silicone rubber compound) ). Specifically, the supporting plate 24 may be PET, and the insulating layer 240 may be a silicone rubber elastomer.

於後續封裝製程中,係使用第2E圖所示之封裝基板2進行如第3A至3C圖所示之本發明之封裝製程。 In the subsequent packaging process, the packaging substrate 2 shown in FIG. 2E is used to perform the packaging process of the present invention shown in FIGS. 3A to 3C.

如第3A圖所示,將至少一電子元件90藉由複數導電元件91結合至該些電性接觸墊220上,再形成固定該電子元件90之封裝膠體(圖略),以形成一電子封裝結構9。 As shown in FIG. 3A, at least one electronic component 90 is coupled to the electrical contact pads 220 through a plurality of conductive components 91, and then a packaging gel (not shown) for fixing the electronic component 90 is formed to form an electronic package. Structure 9.

於本實施例中,該導電元件91係例如銅柱或銲錫凸塊,且該電子元件90係為主動元件、被動元件或其二者組合,其中,該主動元件係例如半導體晶片,而該被動元件係例如電阻、電容及電感。 In this embodiment, the conductive component 91 is, for example, a copper pillar or a solder bump, and the electronic component 90 is an active component, a passive component, or a combination of both. The active component is, for example, a semiconductor wafer, and the passive component is The components are, for example, resistors, capacitors, and inductors.

如第3B圖所示,利用機械方式或物理方式將該絕緣層240自該介電層20之第一表面20a上脫離,使該支撐板 24與該絕緣層240自該介電層20之第一表面20a上分離,即分離該支撐板24與該電子封裝結構9。 As shown in FIG. 3B, the insulating layer 240 is detached from the first surface 20a of the dielectric layer 20 mechanically or physically, so that the supporting plate 24 and the insulation layer 240 are separated from the first surface 20a of the dielectric layer 20, that is, the support plate 24 and the electronic packaging structure 9 are separated.

如第3C圖所示,回收該支撐板24與該絕緣層240,並重複使用該支撐板24與該絕緣層240。 As shown in FIG. 3C, the support plate 24 and the insulation layer 240 are recovered, and the support plate 24 and the insulation layer 240 are reused.

於本實施例中,將分離後之絕緣層240浸泡於溶劑中,使該絕緣層240重新恢復黏性,以令該支撐板24可藉由該絕緣層240結合至另一介電層20’上。 In this embodiment, the separated insulating layer 240 is immersed in a solvent to restore the viscosity of the insulating layer 240 so that the supporting plate 24 can be bonded to another dielectric layer 20 'through the insulating layer 240. on.

於本實施例中,該溶劑之種類可配合該絕緣層240,以重新恢復該絕緣層240之黏性,故該溶劑可選擇非極性有機(non-polar organic)溶劑,例如,汽油(Gasoline)、機油(Motor oil)、柴油(Diesel fuel)、苯(Benzene)、或甲苯(Toluene)等。 In this embodiment, the type of the solvent can be matched with the insulating layer 240 to restore the viscosity of the insulating layer 240. Therefore, the solvent can be a non-polar organic solvent, such as gasoline (Gasoline). , Motor oil, Diesel fuel, Benzene, or Toluene.

本發明提供一種封裝基板2係包括:一介電層20、一第一線路層21以及一支撐板24。 The present invention provides a package substrate 2 including: a dielectric layer 20, a first circuit layer 21 and a support plate 24.

所述之介電層20係具有相對之第一表面20a與第二表面20b。 The dielectric layer 20 has a first surface 20a and a second surface 20b opposite to each other.

所述之第一線路層21係設於該介電層20之第一表面20a上,且其表面齊平或低於該介電層20之第一表面20a。 The first circuit layer 21 is disposed on the first surface 20 a of the dielectric layer 20, and its surface is flush or lower than the first surface 20 a of the dielectric layer 20.

所述之支撐板24係具有一絕緣層240以結合至該介電層20之第一表面20a與該第一線路層21上,且形成該絕緣層240之材質係為膠體。 The supporting plate 24 has an insulating layer 240 to be bonded to the first surface 20 a of the dielectric layer 20 and the first circuit layer 21, and the material forming the insulating layer 240 is gel.

於一實施例中,形成該支撐板24之材質係為紙質基材、複合基材或FR-4基材。 In one embodiment, the material forming the supporting plate 24 is a paper substrate, a composite substrate or a FR-4 substrate.

於一實施例中,該封裝基板2復包括設於該介電層20 之第二表面20b上的第二線路層22。該封裝基板2又包括形成於該介電層20中之複數導電盲孔200,以電性連接該第一與第二線路層21,22。該封裝基板2另包括一絕緣保護層23,其設於該介電層20之第二表面20b及該第二線路層22上,且該絕緣保護層23形成有複數露出部分該第二線路層22之開孔230。 In one embodiment, the package substrate 2 further includes a dielectric layer 20. The second circuit layer 22 on the second surface 20b. The package substrate 2 further includes a plurality of conductive blind holes 200 formed in the dielectric layer 20 to electrically connect the first and second circuit layers 21 and 22. The package substrate 2 further includes an insulating protection layer 23 disposed on the second surface 20b of the dielectric layer 20 and the second circuit layer 22, and the insulating protection layer 23 is formed with a plurality of exposed portions of the second circuit layer. 22 的 开孔 230。 22 of the opening 230.

綜上所述,本發明之封裝基板及封裝製程中,主要藉由該絕緣層之設計,使該絕緣層浸泡溶劑後即可恢復黏性,故能重複使用該支撐板與該絕緣層,以避免習知使用支撐板後即丟棄所造成之浪廢問題。 In summary, in the packaging substrate and the packaging process of the present invention, the design of the insulating layer is mainly used to restore the viscosity of the insulating layer after soaking the solvent, so the supporting board and the insulating layer can be reused to Avoid the problem of waste caused by discarding after using the support plate.

上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。 The above embodiments are used to exemplify the principle of the present invention and its effects, but not to limit the present invention. Anyone skilled in the art can modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be listed in the scope of patent application described later.

Claims (20)

一種封裝基板,係包括:介電層,係具有相對之第一表面與第二表面;第一線路層,係設於該介電層之第一表面上;以及支撐板,係藉由一浸泡過非極性有機(non-polar organic)溶劑後可重新恢復黏性的絕緣層結合至該介電層之第一表面上,其中,該絕緣層為橡膠聚合物。A package substrate includes: a dielectric layer having a first surface and a second surface opposite to each other; a first circuit layer provided on the first surface of the dielectric layer; and a support plate provided by an immersion After passing through a non-polar organic solvent, the insulating layer capable of restoring viscosity can be bonded to the first surface of the dielectric layer, wherein the insulating layer is a rubber polymer. 如申請專利範圍第1項所述之封裝基板,其中,該第一線路層之表面係齊平或低於該介電層之第一表面。The package substrate according to item 1 of the scope of patent application, wherein the surface of the first circuit layer is flush or lower than the first surface of the dielectric layer. 如申請專利範圍第1項所述之封裝基板,其中,形成該支撐板之材質係為紙質基材、複合基材或FR-4基材。The package substrate according to item 1 of the scope of the patent application, wherein the material forming the support plate is a paper substrate, a composite substrate or a FR-4 substrate. 如申請專利範圍第1項所述之封裝基板,其中,形成該絕緣層之材質係為膠體。The package substrate according to item 1 of the scope of patent application, wherein the material forming the insulating layer is gel. 如申請專利範圍第1項所述之封裝基板,其中,形成該絕緣層之材質係為彈性體。The package substrate according to item 1 of the scope of patent application, wherein the material forming the insulating layer is an elastomer. 如申請專利範圍第1項所述之封裝基板,復包括設於該介電層之第二表面上的第二線路層。The package substrate according to item 1 of the patent application scope, further comprising a second circuit layer provided on the second surface of the dielectric layer. 如申請專利範圍第6項所述之封裝基板,復包括形成於該介電層中之複數導電盲孔,以藉由該些導電盲孔電性連接該第一與第二線路層。The package substrate according to item 6 of the patent application scope, further comprising a plurality of conductive blind holes formed in the dielectric layer, so as to electrically connect the first and second circuit layers through the conductive blind holes. 如申請專利範圍第6項所述之封裝基板,復包括絕緣保護層,係設於該介電層之第二表面及該第二線路層上,且該第二線路層係部分外露於該絕緣保護層。The package substrate according to item 6 of the scope of patent application, which includes an insulating protection layer, is provided on the second surface of the dielectric layer and the second circuit layer, and the second circuit layer system is partially exposed to the insulation. The protective layer. 一種封裝製程,係包括:提供一如申請專利範圍第1項所述之封裝基板;將至少一電子元件結合至該介電層之第二表面上;以及將該支撐板與該絕緣層自該介電層之第一表面上分離。A packaging process includes: providing a packaging substrate as described in item 1 of the scope of patent application; bonding at least one electronic component to a second surface of the dielectric layer; and the supporting plate and the insulating layer from the The first surface of the dielectric layer is separated. 如申請專利範圍第9項所述之封裝製程,其中,該封裝基板之製法係包括:提供表面上形成有該第一線路層之一承載件;形成該介電層於該承載件及該第一線路層上,其中,該介電層係以其第一表面結合該承載件;移除該承載件;以及將該支撐板藉由該絕緣層結合於該介電層之第一表面上。The packaging process according to item 9 of the scope of patent application, wherein the manufacturing method of the package substrate includes: providing a carrier with the first circuit layer formed on the surface; forming the dielectric layer on the carrier and the first On a circuit layer, wherein the dielectric layer is bonded to the carrier with its first surface; the carrier is removed; and the support plate is bonded to the first surface of the dielectric layer through the insulating layer. 如申請專利範圍第9項所述之封裝製程,其中,該第一線路層之表面係齊平或低於該介電層之第一表面。The packaging process according to item 9 of the scope of patent application, wherein the surface of the first circuit layer is flush or lower than the first surface of the dielectric layer. 如申請專利範圍第9項所述之封裝製程,其中,形成該支撐板之材質係為紙質基材、複合基材或FR-4基材。According to the encapsulation process described in item 9 of the scope of patent application, wherein the material forming the support plate is a paper substrate, a composite substrate, or a FR-4 substrate. 如申請專利範圍第9項所述之封裝製程,其中,形成該絕緣層之材質係為膠體。The encapsulation process according to item 9 of the scope of the patent application, wherein the material forming the insulating layer is gel. 如申請專利範圍第9項所述之封裝製程,其中,形成該絕緣層之材質係為彈性體。The packaging process as described in item 9 of the scope of patent application, wherein the material forming the insulating layer is an elastomer. 如申請專利範圍第9項所述之封裝製程,其中,該封裝基板復包括設於該介電層之第二表面上的第二線路層。The packaging process according to item 9 of the scope of patent application, wherein the package substrate further includes a second circuit layer disposed on the second surface of the dielectric layer. 如申請專利範圍第15項所述之封裝製程,其中,該封裝基板復包括形成於該介電層中之複數導電盲孔,以藉由該些導電盲孔電性連接該第一與第二線路層。The packaging process according to item 15 of the scope of patent application, wherein the package substrate further comprises a plurality of conductive blind holes formed in the dielectric layer, so as to electrically connect the first and second via the conductive blind holes. Line layer. 如申請專利範圍第15項所述之封裝製程,該封裝基板復包括絕緣保護層,係設於該介電層之第二表面及該第二線路層上,且該第二線路層係部分外露於該絕緣保護層。According to the encapsulation process described in claim 15 of the patent application scope, the package substrate further includes an insulation protection layer, which is disposed on the second surface of the dielectric layer and the second circuit layer, and the second circuit layer is partially exposed. On the insulation protection layer. 如申請專利範圍第9項所述之封裝製程,其中,該電子元件係為主動元件、被動元件或其二者組合。The packaging process according to item 9 of the scope of patent application, wherein the electronic component is an active component, a passive component, or a combination thereof. 如申請專利範圍第9項所述之封裝製程,其中,該電子元件藉由複數導電元件結合至該第二表面上。The packaging process according to item 9 of the scope of patent application, wherein the electronic component is bonded to the second surface by a plurality of conductive components. 如申請專利範圍第9項所述之封裝製程,復包括自該介電層上分離該支撐板後,將該支撐板結合至另一介電層上。According to the encapsulation process described in item 9 of the scope of patent application, the method further includes separating the supporting plate from the dielectric layer, and then bonding the supporting plate to another dielectric layer.
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201314853A (en) * 2011-09-30 2013-04-01 Unimicron Technology Corp Package substrate having holder and fabricating method thereof, package structure having holder and fabricating method thereof
TW201410096A (en) * 2012-08-27 2014-03-01 Zhen Ding Technology Co Ltd Package substrate, package structure and methods for manufacturing same
TW201414372A (en) * 2012-09-25 2014-04-01 Zhen Ding Technology Co Ltd Package substrate, package structure and methods for manufacturing same
TW201427522A (en) * 2012-12-21 2014-07-01 Zhen Ding Technology Co Ltd Package circuit board, method for manufacturing same, and package structure
TW201505507A (en) * 2013-07-22 2015-02-01 Zhen Ding Technology Co Ltd Package substrate, package structure and method for manufacturing package structure
TW201546912A (en) * 2014-02-13 2015-12-16 Adl Engineering Inc Electronic package, package carrier, and methods of manufacturing electronic package and package carrier

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009117767A (en) * 2007-11-09 2009-05-28 Shinko Electric Ind Co Ltd Manufacturing method of semiconductor device, and semiconductor device manufacture by same
CN102054714B (en) * 2009-11-06 2012-10-03 欣兴电子股份有限公司 Method for manufacturing packaging structure
CN105097558A (en) * 2014-04-21 2015-11-25 富葵精密组件(深圳)有限公司 Chip packaging structure and manufacture method thereof, and chip packaging substrate

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201314853A (en) * 2011-09-30 2013-04-01 Unimicron Technology Corp Package substrate having holder and fabricating method thereof, package structure having holder and fabricating method thereof
TW201410096A (en) * 2012-08-27 2014-03-01 Zhen Ding Technology Co Ltd Package substrate, package structure and methods for manufacturing same
TW201414372A (en) * 2012-09-25 2014-04-01 Zhen Ding Technology Co Ltd Package substrate, package structure and methods for manufacturing same
TW201427522A (en) * 2012-12-21 2014-07-01 Zhen Ding Technology Co Ltd Package circuit board, method for manufacturing same, and package structure
TW201505507A (en) * 2013-07-22 2015-02-01 Zhen Ding Technology Co Ltd Package substrate, package structure and method for manufacturing package structure
TW201546912A (en) * 2014-02-13 2015-12-16 Adl Engineering Inc Electronic package, package carrier, and methods of manufacturing electronic package and package carrier

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