CN105097558A - Chip packaging structure and manufacture method thereof, and chip packaging substrate - Google Patents
Chip packaging structure and manufacture method thereof, and chip packaging substrate Download PDFInfo
- Publication number
- CN105097558A CN105097558A CN201410159581.3A CN201410159581A CN105097558A CN 105097558 A CN105097558 A CN 105097558A CN 201410159581 A CN201410159581 A CN 201410159581A CN 105097558 A CN105097558 A CN 105097558A
- Authority
- CN
- China
- Prior art keywords
- dielectric layer
- layer
- conductive circuit
- conductive
- circuit layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
A manufacturing method of a chip packaging structure comprises the steps that a loading plate is provided, a first conductive line layer, a first dielectric layer and a second conductive line layer are successively formed at one side at least of the loading plate, and the first conductive line layer is connected with the second conductive line layer via first conductive poles; a second dielectric layer is formed at one side, far from the loading plate, of the second conductive line layer, openings of the second dielectric layer are formed in the second conductive dielectric layer, and form second conductive poles via electroplating, the second conductive line layer is electrically connected with the second conductive poles, and the surfaces, far from the first dielectric layer, of the second conductive poles are approximately leveled with the surface, far from the first dielectric layer, of the second dielectric layer; and the loading plate is removed, and a chip is welded to form the chip packaging structure. The invention also relates to a chip packaging substrate and structure.
Description
Technical field
The present invention relates to circuit board making field, particularly relate to a kind of chip-packaging structure, manufacture method and chip package base plate.
Background technology
Chip package base plate can be chip and provides the effects such as electrical connection, protection, support, heat radiation, assembling, to realize many pinizations, reduces encapsulating products volume, improves the object of electrical property and thermal diffusivity, super-high density or multi-chip module.Usually, chip package base plate connects chip side and forms welding resisting layer opening putting, and to expose weld pad, and then can form soldered ball and and chips welding on weld pad surface.Under the demand of high-density wiring, circuit is more and more thinner, welding resisting layer opening is also more and more less, thus the size of the weld pad defined by welding resisting layer opening is also more and more less, thus failure welding is occurred again and again, on the one hand, soldered ball is not easily packed into welding resisting layer opening and then can causes missing solder, on the other hand, Diameter of Solder Ball diminishes with welding resisting layer opening size and diminishes, to such an extent as to welding and assembling height is not enough, causes the distance between chip and base plate for packaging inadequate, be difficult to fill packing colloid, and then cause chip not to be encapsulated on base plate for packaging securely.
Summary of the invention
Therefore, be necessary that providing a kind of can improve the chip-packaging structure, manufacture method and the chip package base plate that weld yield.
A kind of manufacture method of chip-packaging structure, comprise step: provide a loading plate, at least the first conductive circuit layer, the first dielectric layer, the second conductive circuit layer is formed successively in side at described loading plate, wherein, multiple first dielectric layer opening is formed in described first dielectric layer, multiple first conductive stud is formed in described first dielectric layer opening, and described first conductive circuit layer and described second conductive circuit layer that are positioned at described loading plate homonymy are electrically connected by multiple first conductive pole; Form the second dielectric layer in described second conductive circuit layer away from the side of described loading plate, in described second dielectric layer, be formed with multiple second dielectric layer opening; Plating forms multiple second conductive pole in described second dielectric layer opening, wherein, described second conductive circuit layer and described second conductive pole are electrically connected, and described second conductive pole roughly flushes away from the surface of described first dielectric layer and the surface away from described first dielectric layer of described second dielectric layer; Remove described loading plate; At surface formation one first soldered ball of each described second conductive pole away from described first conductive circuit layer; And weld a chip at multiple described first solder ball surface, described chip is electrically connected with described second conductive pole, thus forms described chip-packaging structure.
A kind of manufacture method of chip-packaging structure, comprise step: provide a loading plate, at least the first conductive circuit layer, the first dielectric layer, the second conductive circuit layer is formed successively in side at described loading plate, wherein, multiple first dielectric layer opening is formed in described first dielectric layer, multiple first conductive stud is formed in described first dielectric layer opening, and described first conductive circuit layer and described second conductive circuit layer that are positioned at described loading plate homonymy are electrically connected by multiple first conductive pole; Electroplate thus form multiple second conductive pole on described second conductive circuit layer surface, described second conductive circuit layer and described second conductive pole are electrically connected; The second dielectric layer is formed away from the side of described loading plate in described second conductive circuit layer, multiple second dielectric layer opening is formed in described second dielectric layer, wherein, described multiple second conductive pole is all formed in described second dielectric layer opening, and described second conductive pole roughly flushes away from the surface of described first dielectric layer and the surface away from described first dielectric layer of described second dielectric layer; Remove described loading plate; At surface formation one first soldered ball of each described second conductive pole away from described first conductive circuit layer; And weld a chip at multiple described first solder ball surface, described chip is electrically connected with described second conductive pole, thus forms described chip-packaging structure.
A kind of chip-packaging structure, comprises one first dielectric layer, one first conductive circuit layer, one second conductive circuit layer, one second dielectric layer, multiple second conductive pole and at least one chip.Described first dielectric layer comprises relative first surface and second surface.Described first conductive circuit layer is formed at the first surface of described first dielectric layer and side is embedded in described first dielectric layer, and described first conductive circuit layer flushes away from the face of described second surface and described first surface.Described second conductive circuit layer is formed at described second surface, and described second conductive circuit layer and described first conductive circuit layer are electrically connected by multiple first conductive pole.Described second dielectric layer is formed at the surface of described second surface and described second conductive circuit layer.Described second dielectric layer is provided with multiple second dielectric layer opening.Described multiple second conductive pole is formed in described second dielectric layer opening by plating, described multiple second conductive pole is all electrically connected with described second conductive circuit layer, and described second conductive pole roughly flushes away from the surface of described first dielectric layer and the surface away from described first dielectric layer of described second dielectric layer.Described chip is electrically connected by multiple first soldered ball and described second conductive pole.
A kind of chip package base plate, comprises one first dielectric layer, one first conductive circuit layer, one second conductive circuit layer, one second dielectric layer and multiple second conductive pole.Described first dielectric layer comprises relative first surface and second surface.Described first conductive circuit layer is formed at the first surface of described first dielectric layer and side is embedded in described first dielectric layer, and described first conductive circuit layer flushes away from the face of described second surface and described first surface.Described second conductive circuit layer is formed at described second surface, and described second conductive circuit layer and described first conductive circuit layer are electrically connected by multiple first conductive pole.Described second dielectric layer is formed at the surface of described second surface and described second conductive circuit layer.Described second dielectric layer is provided with multiple second dielectric layer opening.Described multiple second conductive pole is formed in described second dielectric layer opening by plating, described multiple second conductive pole is all electrically connected with described second conductive circuit layer, and described second conductive pole roughly flushes away from the surface of described first dielectric layer and the surface away from described first dielectric layer of described second dielectric layer.
Relative to prior art, the embodiment of the present invention is at chip-packaging structure, described second conductive pole of its manufacture method and chip package base plate roughly flushes away from the surface of described first dielectric layer and the surface away from described first dielectric layer of described second dielectric layer, therefore, during at the second conductive pole surface formation soldered ball and with chips welding, soldered ball does not need to fill welding resisting layer opening, therefore, not easily there is missing solder to connect, and ball height is the distance between chip bottom and base plate for packaging, thus make the distance between chip bottom and base plate for packaging enough fill up packing colloid, and then make chip be encapsulated on base plate for packaging securely, also be, the chip-packaging structure of this case, its manufacture method and chip package base plate can improve welding yield, further, this case utilizes loading plate to be formed without sandwich layer chip-packaging structure and chip package base plate, and what can make is thinner.
Accompanying drawing explanation
Fig. 1 is the cutaway view of the chip-packaging structure that first embodiment of the invention provides.
Fig. 2 is the cutaway view after second embodiment of the invention is provided in Copper Foil that loading plate fits.
Copper Foil in Fig. 2 is made the cutaway view after formation first conductive circuit layer by Fig. 3.
Fig. 4 is the cutaway view after the first conductive circuit layer surface of Fig. 3 forms the first dielectric layer.
Fig. 5 is the cutaway view after the first dielectric layer surface in the diagram forms the first patterning photoresist layer.
Fig. 6 forms the first conductive pole and cutaway view after the first dielectric layer surface forms the second conductive circuit layer in the first dielectric layer in Figure 5.
Fig. 7 is the cutaway view after being removed by the first patterning photoresist layer in Fig. 6.
Fig. 8 is that the second conductive circuit layer surface pressing in the figure 7 forms the second dielectric layer and cutaway view after forming the second dielectric layer opening.
Fig. 9 is that the second conductive circuit layer surface injection mo(u)lding in the figure 7 forms the schematic diagram of the second dielectric layer.
Figure 10 is the cutaway view after forming the second conductive pole in the second dielectric layer opening in fig. 8.
Loading plate 110 in Figure 10 is removed and forms the schematic diagram of two chip package base plates by Figure 11.
Figure 12 is the cutaway view after the first conductive circuit layer surface of the chip package base plate of Figure 11 forms welding resisting layer.
Figure 13 is the cutaway view after the surface with similar first dielectric layer of second embodiment Fig. 4 forms the first patterning photoresist layer and forms the first conductive pole and the second conductive circuit layer that this case the 3rd embodiment provides.
Figure 14 is that the first patterning photoresist layer surface in fig. 13 forms the second patterning photoresist layer and cutaway view after forming the second conductive pole.
Figure 15 is the cutaway view after being removed by first and second patterning photoresist layer in Figure 14.
Figure 16 is the cutaway view after the second conductive pole side in fig .15 forms the second dielectric layer.
Figure 17 is to expose the cutaway view after described second conductive pole by the second dielectric layer grinding in Figure 16.
Main element symbol description
Chip-packaging structure 100
First dielectric layer 126,926
First surface 1261
Second surface 1262
First conductive circuit layer 124,924
Second conductive circuit layer 134,934
First conductive pole 132,932
Second dielectric layer 136,936
Second dielectric layer opening 138,938
Second conductive pole 140,940
Chip 148
First soldered ball 150
Packing colloid 154
Welding resisting layer 142
Welding resisting layer opening 144
Weld pad 146
Second soldered ball 152
Loading plate 110,910
Copper Foil 120
First dielectric layer opening 128,928
First circuit board intermediate 200,900
First patterning photoresist layer 130,930
Mould 300
Die cavity 310
Glue injection channel 320
Second circuit board intermediate 210,901
Second patterning photoresist layer 960
Following embodiment will further illustrate the present invention in conjunction with above-mentioned accompanying drawing.
Embodiment
Refer to Fig. 1, first embodiment of the invention provides a kind of chip-packaging structure 100, comprising: one first dielectric layer 126, and described first dielectric layer 126 comprises relative first surface 1261 and second surface 1262; One first conductive circuit layer 124, described first conductive circuit layer 124 is formed at the first surface 1261 of described first dielectric layer 126 and side is embedded in described first dielectric layer 126, and described first conductive circuit layer 124 flushes away from the face of described second surface 1262 and described first surface 1261; One second conductive circuit layer 134, described second conductive circuit layer 134 is formed at described second surface 1262, and described second conductive circuit layer 134 is electrically connected by multiple first conductive pole 132 with described first conductive circuit layer 124; One second dielectric layer 136, described second dielectric layer 136 is formed at the surface of described second surface 1262 and described second conductive circuit layer 134, described second dielectric layer 136 is provided with multiple second dielectric layer opening 138, and described second conductive circuit layer 134 of part comes out from described second dielectric layer opening 138; Multiple second conductive pole 140, described multiple second conductive pole 140 is formed in described second dielectric layer opening 138, and is all electrically connected with described second conductive circuit layer 134; At least one chip 148, described chip 148 is electrically connected with described second conductive pole 140 by multiple first soldered ball 150, and side and the bottom of described chip 148 are formed with packing colloid 154; One welding resisting layer 142, described welding resisting layer 142 is formed at the surface of described first surface 1261 and the first conductive circuit layer 124, described welding resisting layer 142 is formed with welding resisting layer opening 144, described first conductive circuit layer 124 of part comes out from described welding resisting layer opening 144, form multiple weld pad 146, described multiple weld pad 146 is for being electrically connected with other circuit boards, and described weld pad 146 surface is formed with the second soldered ball 152.
In the present embodiment, described multiple first conductive pole 132 is roughly truncated cone-shaped; Described multiple first conductive pole 132, second conductive pole 140 and described second conductive circuit layer 134 are all formed by plating; Described second conductive pole 140 roughly flushes away from the surface of described first dielectric layer 126 and the surface away from described first dielectric layer 126 of described second dielectric layer 136.
Refer to Fig. 2-14, second embodiment of the invention provides a kind of manufacture method of said chip encapsulating structure 100, comprises the steps:
The first step, refers to Fig. 2, provides a loading plate 110, and a Copper Foil 120 of fitting respectively in the relative both sides of described loading plate 110.
Described loading plate 110 is in tabular.Described loading plate 110 can be the rigid support materials such as resin plate, ceramic wafer, metallic plate.In the present embodiment, described loading plate 110 is double-sided copper-clad substrate.
In the present embodiment, Copper Foil 120 described in two fits in the relative both sides of described loading plate 110 respectively by a thermoplasticity colloid layer 122.Wherein, thermoplastic cement is adopted to show consideration for the reason of conjunction Copper Foil for ease of removing described loading plate 110 in subsequent step.
Second step, refers to Fig. 3, and the described Copper Foil 120 of both sides is all made formation first conductive circuit layer 124.
In present embodiment, form described first conductive circuit layer 124 by image transfer technique and etch process.
3rd step, refer to Fig. 4, every layer described, the side away from described loading plate 110 of the first conductive circuit layer 124 all forms one first dielectric layer 126, and on two-layer described first dielectric layer 126, all forms multiple first dielectric layer opening 128, to expose part first conductive circuit layer 124.
In the present embodiment, first, by the side away from described loading plate 110 of first conductive circuit layer 124 every layer described laminating film and hot pressing solidifies described film forms described first dielectric layer 126, the thermoplasticity colloid layer 122 that described first dielectric layer 126 covers described first conductive circuit layer 124 and exposes from described first conductive circuit layer 124; Afterwards, on described first dielectric layer 126, form multiple described first dielectric layer opening 128 by the mode of laser pit, described first conductive circuit layer 124 of part is come out from described first dielectric layer opening 128.
4th step, refer to Fig. 5-7, the first conductive pole 132 is all formed in each described first dielectric layer opening 128, and form the second conductive circuit layer 134 at the part surface of described first dielectric layer 126, described first conductive circuit layer 124 and described second conductive circuit layer 134 that make to be positioned at described loading plate 110 homonymy are electrically connected by described first conductive pole 132 of homonymy, thus obtain a first circuit board intermediate 200.
In the present embodiment, form described first conductive pole 132 and described second conductive circuit layer 134 by the mode of selective electroplating simultaneously.
Particularly, first, refer to Fig. 5, form the first patterning photoresist layer 130 on the surface of described first dielectric layer 126 of both sides, wherein, described first dielectric layer 126 around each described first dielectric layer opening 128 is all exposed in described first patterning photoresist layer 130; Then, refer to Fig. 6, plating, thus in described first dielectric layer opening 128 fill electroplating metal material thus formed the first conductive pole 132, and at the first dielectric layer 126 surface coverage electroplating metal material exposed from described first patterning photoresist layer 130 thus formed the second conductive circuit layer 134; Afterwards, refer to Fig. 7, remove described first patterning photoresist layer 130.
5th step, refer to Fig. 8, every layer described, the side away from described loading plate 110 of the second conductive circuit layer 134 forms the second dielectric layer 136, and on two-layer described second dielectric layer 136, all forms multiple second dielectric layer opening 138, to expose part second conductive circuit layer 134.
In the present embodiment, first, by the side away from described loading plate 110 of second conductive circuit layer 134 every layer described laminating film and hot pressing solidifies described film forms described second dielectric layer 136; Then, on described second dielectric layer 136, form described second dielectric layer opening 138 by the mode of laser pit, described second conductive circuit layer 134 of part is come out from described second dielectric layer opening 138.
In other embodiments, also described second dielectric layer 136 can be formed by the mode of injection mo(u)lding, be specially: refer to Fig. 9, first, one mould 300 is provided, described mould 300 comprises die cavity 310 and a glue injection channel 320, is contained in described die cavity 310 by described first circuit board intermediate 200, and the equal opposing mold in side away from described loading plate 110 of every layer of described second conductive circuit layer 134 leaves space; Then, in described die cavity 310, colloid is injected by described glue injection channel 320; Then, solidifying described colloid makes described colloid be coated on the second conductive circuit layer 134 surface of the relative both sides of described first circuit board intermediate 200 and be coated on the surface of the first dielectric layer 126 be exposed in the second conductive circuit layer 134, thus makes described colloid become described second dielectric layer 136; Afterwards, the described first circuit board intermediate 200 being coated with the second dielectric layer 136 is taken out from die cavity and can carry out following process to described second dielectric layer 136, comprise formation second dielectric layer opening 138.
In addition, photosensitive material also can be adopted to form described second dielectric layer 136, now, described second dielectric layer opening 138 is formed by exposure and visualization way.
6th step, refer to Figure 10, in each described second dielectric layer opening 138, all form the second conductive pole 140, thus obtain a second circuit board intermediate 210, wherein, be electrically connected with described second conductive circuit layer 134 of described loading plate 110 homonymy and described second conductive pole 140.
In the present embodiment, form described second conductive pole 140 by the mode of plating.Preferably, plating makes described second conductive pole 140 roughly flush away from the surface of described loading plate 110 and the surface away from described loading plate 110 of described second dielectric layer 136.The material of described second conductive pole 140 can be copper, tin or both combinations.Certainly, also can after plating by grind or the mode such as etching makes described second conductive pole 140 roughly flush away from the surface of described loading plate 110 and the surface away from described loading plate 110 of described second dielectric layer 136.
7th step, refers to Figure 11, described loading plate 110 and two thermoplasticity colloid layers 122 is separated removal from described second circuit board intermediate 210, thus obtains two chip package base plates 220.
In the present embodiment, heat the fusing point of described second circuit board intermediate 210 to described thermoplasticity colloid layer 122, afterwards described loading plate 110 and two thermoplasticity colloid layers 122 are separated removal from described second circuit board intermediate 210.
Each described chip package base plate 220 includes: one first dielectric layer 126, and described first dielectric layer 126 comprises relative first surface 1261 and second surface 1262; One first conductive circuit layer 124, described first conductive circuit layer 124 is formed at the first surface 1261 of described first dielectric layer 126 and side is embedded in described first dielectric layer 126, and, because of described first conductive circuit layer 124 and described first dielectric layer 126 all with described loading plate 110 for benchmark formed and be all affixed with described loading plate 110, therefore described first conductive circuit layer 124 flushes away from the face of described second surface 1262 and described first surface 1261; One second conductive circuit layer 134, described second conductive circuit layer 134 is formed at described second surface 1262, and described second conductive circuit layer 134 is electrically connected by multiple first conductive pole 132 with described first conductive circuit layer 124; One second dielectric layer 136, described second dielectric layer 136 is formed at the surface of described second surface 1262 and described second conductive circuit layer 134, described second dielectric layer 136 is provided with multiple second dielectric layer opening 138, and described second conductive circuit layer 134 of part comes out from described second dielectric layer opening 138; Multiple second conductive pole 140, described multiple second conductive pole 140 is formed in described second dielectric layer opening 138, and is all electrically connected with described second conductive circuit layer 134.
In the present embodiment, described multiple first conductive pole 132 is roughly truncated cone-shaped; Described multiple first conductive pole 132, second conductive pole 140 and described second conductive circuit layer 134 are all formed by plating; Described second conductive pole 140 roughly flushes away from the surface of described first dielectric layer 126 and the surface away from described first dielectric layer 126 of described second dielectric layer 136.
8th step, refers to Figure 12, forms a welding resisting layer 142, and form multiple welding resisting layer opening 144 at described welding resisting layer 142 in the first conductive circuit layer 124 side of described chip package base plate 220, to expose described first conductive circuit layer 124 of part.
In the present embodiment, form described welding resisting layer opening 144 by exposure and developing manufacture process.Described first conductive circuit layer 124 that definition comes out from described welding resisting layer 142 is weld pad 146, and described weld pad 146 is for being electrically connected described chip package base plate 220 with other circuit boards.
Described welding resisting layer 142 to act as protection first conductive circuit layer 124 not oxidized, be appreciated that and also can not form described welding resisting layer 142.
Certainly, described chip package base plate 220 can comprise multiple circuit board unit, also only can comprise a circuit board unit, in the present embodiment, anticipate as shown by the dashed lines of figure 12, described chip package base plate 220 comprises multiple circuit board unit, and between each circuit board unit, circuit is separate.
9th step, refers to Fig. 1, at described second conductive pole 140 surface soldered one chip 148, described chip 148 is electrically connected with described second conductive pole 140, thus forms described chip-packaging structure 100.
In the present embodiment, first the first soldered ball 150 is formed at each described second conductive pole 140 away from the surface of described first conductive circuit layer 124, afterwards described chip 148 is welded on described first soldered ball 150, thus described chip 148 is electrically connected with described second conductive pole 140.
In the present embodiment, also form the second soldered ball 152 on described weld pad 146 surface; Further, after welding described chip 148, also packing colloid 154 is injected in chip 148 side and bottom, with fixing described chip 148.
Because the chip package base plate 220 of this case comprises multiple circuit board unit, therefore, in the present embodiment, after welding chip, cut along each circuit board unit border, thus form multiple independently described chip-packaging structure 100.Certainly, if the chip package base plate of this case 220 only comprises a circuit board unit, then this is not needed to cut process.
Refer to Figure 13-17, third embodiment of the invention provides the another kind of manufacture method of said chip encapsulating structure, the manufacture method of the chip-packaging structure in the present embodiment is roughly the same with the second embodiment, and difference is that the 4th step is to the 6th step, and the 4th step of the present embodiment is as follows to the 6th step:
4th step, refer to Figure 13, the first patterning photoresist layer 930 is formed on the surface of described first dielectric layer 926, plating, thus the first conductive pole 932 is all formed in each described first dielectric layer opening 928, and form the second conductive circuit layer 934 on described first dielectric layer 926 surface be exposed in the first patterning photoresist layer 930, make to be electrically connected by described first conductive pole 932 of homonymy with described first conductive circuit layer 924 of described loading plate 910 homonymy and described second conductive circuit layer 934, thus obtain a first circuit board intermediate 900.Also namely, described first patterning photoresist layer 930 is not removed by this step.
5th step, refers to Figure 14-15, forms the second patterning photoresist layer 960 in the both sides of described first circuit board intermediate 900; Plating, thus form the second conductive pole 940 on the surface be exposed in the second patterning photoresist layer 960 of described second conductive circuit layer 934, make to be electrically connected with described second conductive pole 942 with described second conductive circuit layer 934 of described loading plate 910 homonymy; Afterwards, described first patterning photoresist layer 930 and the second patterning photoresist layer 960 is removed.
Wherein, described second patterning photoresist layer 960 is formed in described first patterning photoresist layer 930 surface and part second conductive circuit layer 934 surface of described first circuit board intermediate 900 both sides.
6th step, refers to Figure 16-17, forms the second dielectric layer 936 in described first circuit board intermediate 900 both sides forming described second conductive pole 940, and grinding makes to expose described second conductive pole 940, thus obtains a second circuit board intermediate 901.
In the present embodiment, refer to Figure 16, by the side away from described loading plate 110 of described second conductive pole 940 laminating film and hot pressing solidifies described film forms described second dielectric layer 136; Refer to Figure 17, by grinding make to expose described second conductive pole 940, and make described second conductive pole 940 away from the surface of described loading plate 910 and the surface away from described loading plate 910 of described second dielectric layer 936 substantially flush.
In other embodiments, also can join embodiment two and form described second dielectric layer 936 by the mode of injection mo(u)lding; Injection mo(u)lding refers to Figure 17 after forming described second dielectric layer 936, and the mode of same grinding exposes described second conductive pole 940.
Be appreciated that each embodiment of this case all can comprise more conductive circuit layer and dielectric layer and making thereof, thus obtain the chip package base plate 220 and the chip-packaging structure 100 that comprise more multi-layered line layer; Also only can form the first conductive circuit layer, the first dielectric layer increase layer in loading plate side in the present embodiment.
Relative to prior art, the chip-packaging structure of the embodiment of the present invention, described second conductive pole of manufacture method and chip package base plate roughly flushes away from the surface of described first dielectric layer and the surface away from described first dielectric layer of described second dielectric layer, during at the second conductive pole surface formation soldered ball and with chips welding, soldered ball does not need to fill welding resisting layer opening, therefore, not easily there is missing solder to connect, and ball height is the distance between chip bottom and base plate for packaging, thus make the distance between chip bottom and base plate for packaging enough fill up packing colloid, and then make chip be encapsulated on base plate for packaging securely, also be, the chip-packaging structure of this case, its manufacture method and chip package base plate can improve welding yield, and, this case a loading plate realizes two chip package base plates makes simultaneously by being fitted in by two chip package base plates, thus can cost be saved, further, chip package base plate fits on loading plate by thermoplastic glue layer by this case, only need heating that thermoplastic glue layer is melted and do not need to destroy loading plate and separable described loading plate, loading plate can being reused, also can save cost, further, this case utilizes loading plate to be formed without sandwich layer chip package base plate and chip-packaging structure, and what can make is thinner.
Be understandable that, for the person of ordinary skill of the art, other various corresponding change and distortion can be made by technical conceive according to the present invention, and all these change the protection range that all should belong to the claims in the present invention with distortion.
Claims (21)
1. a manufacture method for chip-packaging structure, comprises step:
One loading plate is provided, at least the first conductive circuit layer, the first dielectric layer, the second conductive circuit layer is formed successively in side at described loading plate, wherein, multiple first dielectric layer opening is formed in described first dielectric layer, multiple first conductive stud is formed in described first dielectric layer opening, and described first conductive circuit layer and described second conductive circuit layer that are positioned at described loading plate homonymy are electrically connected by multiple first conductive pole;
Form the second dielectric layer in described second conductive circuit layer away from the side of described loading plate, in described second dielectric layer, be formed with multiple second dielectric layer opening;
Plating forms multiple second conductive pole in described second dielectric layer opening, wherein, described second conductive circuit layer and described second conductive pole are electrically connected, and described second conductive pole roughly flushes away from the surface of described first dielectric layer and the surface away from described first dielectric layer of described second dielectric layer;
Remove described loading plate;
At surface formation one first soldered ball of each described second conductive pole away from described first conductive circuit layer; And
Weld a chip at multiple described first solder ball surface, described chip is electrically connected with described second conductive pole, thus forms described chip-packaging structure.
2. the manufacture method of chip-packaging structure as claimed in claim 1, it is characterized in that, the formation method of described first conductive circuit layer comprises: at least to fit a Copper Foil and to be made by described Copper Foil by image transfer technique and etch process and form described first conductive circuit layer side at described loading plate.
3. the manufacture method of chip-packaging structure as claimed in claim 2, it is characterized in that, described Copper Foil closes the surface in described loading plate by a thermoplasticity colloid laminating; Remove in the step of described loading plate, make described thermoplasticity colloid layer arrive fusing point by heating, described loading plate is separated with described first conductive circuit layer, thus removes described loading plate.
4. the manufacture method of chip-packaging structure as claimed in claim 1, it is characterized in that, the formation method of described first dielectric layer comprises: at the side away from described loading plate of described first conductive circuit layer laminating film, and hot pressing solidifies described film, forms described first dielectric layer; On described first dielectric layer, multiple described first dielectric layer opening is formed by laser pit.
5. the manufacture method of chip-packaging structure as claimed in claim 4, is characterized in that, after forming described first dielectric layer, form a patterning photoresist layer on the surface of described first dielectric layer; Pass through selective electroplating, thus the first conductive pole is all formed in each described first dielectric layer opening, and form the second conductive circuit layer at the part surface of described first dielectric layer, described first conductive circuit layer and described second conductive circuit layer are electrically connected by described first conductive pole; Remove described patterning photoresist layer.
6. the manufacture method of chip-packaging structure as claimed in claim 5, it is characterized in that, after removing described patterning photoresist layer, at the side away from described loading plate of described second conductive circuit layer laminating film, and hot pressing solidifies described film, form described second dielectric layer; On described second dielectric layer, multiple described second dielectric layer opening is formed by laser pit.
7. the manufacture method of chip-packaging structure as claimed in claim 5, is characterized in that, after removing described patterning photoresist layer, form described second dielectric layer in the mode of injection mo(u)lding in the side away from described loading plate of described second conductive circuit layer; On described second dielectric layer, multiple described second dielectric layer opening is formed by laser pit.
8. the manufacture method of chip-packaging structure as claimed in claims 6 or 7, is characterized in that, plating, thus forms described second conductive pole in described second dielectric layer opening.
9. the manufacture method of chip-packaging structure as claimed in claim 1, is characterized in that, also form the second soldered ball on described first conductive circuit layer surface, described soldered ball is used for described chip-packaging structure and a circuit board to be electrically connected.
10. a manufacture method for chip-packaging structure, comprises step:
One loading plate is provided, at least the first conductive circuit layer, the first dielectric layer, the second conductive circuit layer is formed successively in side at described loading plate, wherein, multiple first dielectric layer opening is formed in described first dielectric layer, multiple first conductive stud is formed in described first dielectric layer opening, and described first conductive circuit layer and described second conductive circuit layer that are positioned at described loading plate homonymy are electrically connected by multiple first conductive pole;
Electroplate thus form multiple second conductive pole on described second conductive circuit layer surface, described second conductive circuit layer and described second conductive pole are electrically connected;
The second dielectric layer is formed away from the side of described loading plate in described second conductive circuit layer, multiple second dielectric layer opening is formed in described second dielectric layer, wherein, described multiple second conductive pole is all formed in described second dielectric layer opening, and described second conductive pole roughly flushes away from the surface of described first dielectric layer and the surface away from described first dielectric layer of described second dielectric layer;
Remove described loading plate;
At surface formation one first soldered ball of each described second conductive pole away from described first conductive circuit layer; And
Weld a chip at multiple described first solder ball surface, described chip is electrically connected with described second conductive pole, thus forms described chip-packaging structure.
The manufacture method of 11. chip-packaging structures as claimed in claim 10, it is characterized in that, the formation method of described first conductive circuit layer comprises: at least to fit a Copper Foil and to be made by described Copper Foil by image transfer technique and etch process and form described first conductive circuit layer side at described loading plate.
The manufacture method of 12. chip-packaging structures as claimed in claim 11, is characterized in that, described Copper Foil closes the surface in described loading plate by a thermoplasticity colloid laminating; Remove in the step of described loading plate, make described thermoplasticity colloid layer arrive fusing point by heating, described loading plate is separated with described first conductive circuit layer, thus removes described loading plate.
The manufacture method of 13. chip-packaging structures as claimed in claim 10, it is characterized in that, the formation method of described first dielectric layer comprises: at the side away from described loading plate of described first conductive circuit layer laminating film, and hot pressing solidifies described film, forms described first dielectric layer; On described first dielectric layer, multiple described first dielectric layer opening is formed by laser pit.
The manufacture method of 14. chip-packaging structures as claimed in claim 13, is characterized in that, after forming described first dielectric layer, forms the first patterning photoresist layer on the surface of described first dielectric layer; Pass through selective electroplating, thus the first conductive pole is all formed in each described first dielectric layer opening, and form the second conductive circuit layer at the part surface of described first dielectric layer, described first conductive circuit layer and described second conductive circuit layer are electrically connected by described first conductive pole.
The manufacture method of 15. chip-packaging structures as claimed in claim 14, is characterized in that, after forming described first conductive pole and the second conductive circuit layer, forms the second patterning photoresist layer at described first patterning photoresist layer away from the side of described loading plate; Selective electroplating, thus form the second conductive pole on the surface being exposed to the second patterning photoresist layer of described second conductive circuit layer, described second conductive circuit layer and described second conductive pole are electrically connected; Remove described first patterning photoresist layer and the second patterning photoresist layer.
The manufacture method of 16. chip-packaging structures as claimed in claim 15, it is characterized in that, after removing described first patterning photoresist layer and the second patterning photoresist layer, at the side away from described loading plate of described second conductive circuit layer laminating film, and hot pressing solidifies described film, form described second dielectric layer.
The manufacture method of 17. chip-packaging structures as claimed in claim 15, it is characterized in that, after removing described first patterning photoresist layer and the second patterning photoresist layer, with the side away from described loading plate of the mode of injection mo(u)lding in described second conductive circuit layer, form described second dielectric layer.
The manufacture method of 18. chip-packaging structures as described in claim 16 or 17, it is characterized in that, after forming described second dielectric layer, grind described second dielectric layer, to expose described second conductive pole, and make described second conductive pole away from the surface of described loading plate and the surface away from described loading plate of described second dielectric layer substantially flush.
The manufacture method of 19. chip-packaging structures as claimed in claim 10, is characterized in that, also form the second soldered ball on described first conductive circuit layer surface, described soldered ball is used for described chip-packaging structure and a circuit board to be electrically connected.
20. 1 kinds of chip-packaging structures, comprising:
One first dielectric layer, described first dielectric layer comprises relative first surface and second surface;
One first conductive circuit layer, described first conductive circuit layer is formed at the first surface of described first dielectric layer and side is embedded in described first dielectric layer, and described first conductive circuit layer flushes away from the face of described second surface and described first surface;
One second conductive circuit layer, described second conductive circuit layer is formed at described second surface, and described second conductive circuit layer and described first conductive circuit layer are electrically connected by multiple first conductive pole;
One second dielectric layer, described second dielectric layer is formed at the surface of described second surface and described second conductive circuit layer, and described second dielectric layer is provided with multiple second dielectric layer opening;
Multiple second conductive pole, described multiple second conductive pole is formed in described second dielectric layer opening by plating, described multiple second conductive pole is all electrically connected with described second conductive circuit layer, and described second conductive pole roughly flushes away from the surface of described first dielectric layer and the surface away from described first dielectric layer of described second dielectric layer; And
At least one chip, described chip is electrically connected by multiple first soldered ball and described second conductive pole.
21. 1 kinds of chip package base plates, comprising:
One first dielectric layer, described first dielectric layer comprises relative first surface and second surface;
One first conductive circuit layer, described first conductive circuit layer is formed at the first surface of described first dielectric layer and side is embedded in described first dielectric layer, and described first conductive circuit layer flushes away from the face of described second surface and described first surface;
One second conductive circuit layer, described second conductive circuit layer is formed at described second surface, and described second conductive circuit layer and described first conductive circuit layer are electrically connected by multiple first conductive pole;
One second dielectric layer, described second dielectric layer is formed at the surface of described second surface and described second conductive circuit layer, and described second dielectric layer is provided with multiple second dielectric layer opening; And
Multiple second conductive pole, described multiple second conductive pole is formed in described second dielectric layer opening by plating, described multiple second conductive pole is all electrically connected with described second conductive circuit layer, and described second conductive pole roughly flushes away from the surface of described first dielectric layer and the surface away from described first dielectric layer of described second dielectric layer.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410159581.3A CN105097558A (en) | 2014-04-21 | 2014-04-21 | Chip packaging structure and manufacture method thereof, and chip packaging substrate |
| TW103123077A TW201541588A (en) | 2014-04-21 | 2014-07-03 | Package structure, method for manufacturing same, and package substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410159581.3A CN105097558A (en) | 2014-04-21 | 2014-04-21 | Chip packaging structure and manufacture method thereof, and chip packaging substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105097558A true CN105097558A (en) | 2015-11-25 |
Family
ID=54577707
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410159581.3A Pending CN105097558A (en) | 2014-04-21 | 2014-04-21 | Chip packaging structure and manufacture method thereof, and chip packaging substrate |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN105097558A (en) |
| TW (1) | TW201541588A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106981469A (en) * | 2016-01-18 | 2017-07-25 | 矽品精密工业股份有限公司 | Packaging process and packaging substrate used by same |
| CN107924847A (en) * | 2016-02-29 | 2018-04-17 | 株式会社藤仓 | Mounting structure and module |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101989592A (en) * | 2009-07-30 | 2011-03-23 | 全懋精密科技股份有限公司 | Packaging substrate as well as manufacturing method and base material thereof |
| CN102054710A (en) * | 2009-11-06 | 2011-05-11 | 欣兴电子股份有限公司 | Coreless layer capsulation substrate and manufacturing method thereof |
| CN102088015A (en) * | 2010-12-03 | 2011-06-08 | 日月光半导体制造股份有限公司 | Semiconductor packaging piece and manufacture method thereof |
| CN102867806A (en) * | 2011-07-08 | 2013-01-09 | 欣兴电子股份有限公司 | Package substrate and method for manufacturing the same |
-
2014
- 2014-04-21 CN CN201410159581.3A patent/CN105097558A/en active Pending
- 2014-07-03 TW TW103123077A patent/TW201541588A/en unknown
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101989592A (en) * | 2009-07-30 | 2011-03-23 | 全懋精密科技股份有限公司 | Packaging substrate as well as manufacturing method and base material thereof |
| CN102054710A (en) * | 2009-11-06 | 2011-05-11 | 欣兴电子股份有限公司 | Coreless layer capsulation substrate and manufacturing method thereof |
| CN102088015A (en) * | 2010-12-03 | 2011-06-08 | 日月光半导体制造股份有限公司 | Semiconductor packaging piece and manufacture method thereof |
| CN102867806A (en) * | 2011-07-08 | 2013-01-09 | 欣兴电子股份有限公司 | Package substrate and method for manufacturing the same |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106981469A (en) * | 2016-01-18 | 2017-07-25 | 矽品精密工业股份有限公司 | Packaging process and packaging substrate used by same |
| CN106981469B (en) * | 2016-01-18 | 2019-10-11 | 矽品精密工业股份有限公司 | Packaging process and packaging substrate used by same |
| CN107924847A (en) * | 2016-02-29 | 2018-04-17 | 株式会社藤仓 | Mounting structure and module |
| CN107924847B (en) * | 2016-02-29 | 2020-08-07 | 株式会社藤仓 | Mounting structure and module |
| US10763200B2 (en) | 2016-02-29 | 2020-09-01 | Fujikura Ltd. | Mounting structure and module |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201541588A (en) | 2015-11-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103579128B (en) | Chip package base plate, chip-packaging structure and preparation method thereof | |
| US8956918B2 (en) | Method of manufacturing a chip arrangement comprising disposing a metal structure over a carrier | |
| CN101989592B (en) | Packaging substrate as well as manufacturing method | |
| US8590147B2 (en) | Method for fabricating circuit board structure with concave conductive cylinders | |
| CN103906372A (en) | Circuit board having embedded components and manufacturing method thereof | |
| JP2008103615A (en) | Electronic component mounting multilayer wiring board and its manufacturing method | |
| JP5289832B2 (en) | Semiconductor device and manufacturing method of semiconductor device | |
| CN101499445A (en) | Semiconductor device and manufacturing method thereof | |
| JP2008218979A (en) | Electronic packaging and manufacturing method thereof | |
| CN103681365A (en) | Package-on-package (POP) structure and manufacturing method for POP structure | |
| CN104241231A (en) | Chip packaging substrate and manufacturing method thereof | |
| CN103794515A (en) | Chip packaging substrate, chip packaging structure, and method for manufacturing same | |
| CN103889168A (en) | Bearing circuit board, manufacturing method of bearing circuit board and packaging structure | |
| JP5803997B2 (en) | Manufacturing method of electronic parts | |
| CN102376678B (en) | Chip scale package and manufacturing method thereof | |
| CN104299919B (en) | Coreless package structure and method for manufacturing the same | |
| CN105590914A (en) | Electronic component packaging structure and manufacturing method | |
| KR20070068268A (en) | Method for manufacturing wiring board | |
| CN105448856A (en) | Chip package structure, method of making same and chip package substrate | |
| JP5397012B2 (en) | Component built-in wiring board, method of manufacturing component built-in wiring board | |
| CN105097558A (en) | Chip packaging structure and manufacture method thereof, and chip packaging substrate | |
| CN105448883A (en) | Chip package substrate, chip package structure and method for manufacturing both the two | |
| JP2007059588A (en) | Method of manufacturing wiring board, and wiring board | |
| JP5539453B2 (en) | Electronic component-mounted multilayer wiring board and manufacturing method thereof | |
| JP2010098021A (en) | Component built-in circuit substrate and method of producing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20161226 Address after: 066004 Qinhuangdao economic and Technological Development Zone, Hebei Tengfei Road, No. 18 Applicant after: Acer Qinhuangdao Ding Technology Co. Ltd. Applicant after: Zhen Ding Tech. Co.,Ltd. Address before: 518103 Shenzhen Province, Baoan District Town, Fuyong Tong tail Industrial Zone, factory building, building 5, floor, 1 Applicant before: Fukui Precision Component (Shenzhen) Co. Ltd. Applicant before: Zhen Ding Tech. Co.,Ltd. |
|
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20151125 |
|
| WD01 | Invention patent application deemed withdrawn after publication |