KR20180072395A - Printed circuit board and package - Google Patents

Abstract

Disclosed is a printed circuit board capable of reducing damage to a conductive pattern when forming a surface treatment layer. According to one aspect of the present invention, the printed circuit board comprises: an insulating unit; an outer layer conductive pattern layer including a first conductive pattern and a second conductive pattern individually buried in one surface of the insulating unit; a first surface treatment layer formed on the first conductive pattern and protruding from one surface of the insulating unit; a seed layer formed between the first conductive pattern and the first surface treatment layer and protruding from one surface of the insulating unit; a second surface treatment layer formed on the second conductive pattern and containing an organic matter; and a recess unit formed on both sides of the first conductive pattern and/or the seed layer.

Description

[0001] PRINTED CIRCUIT BOARD AND PACKAGE [0002]

The present invention relates to a printed circuit board and a package.

Typically, a printed circuit board is produced by sequentially laminating a plurality of buildup layers on a core substrate. The production of the printed circuit board by sequentially stacking the build-up layers can be referred to as a sequential layer construction method.

When a printed circuit board is manufactured by a sequential lamination method, the number of lamination steps increases as the number of printed circuit boards increases. Such a lamination process may cause unnecessary and unpredictable deformation because heat is applied to a portion already existing in the lamination process. The more such deformation, the more difficult the interlayer matching becomes.

Accordingly, a batch lamination method has been developed in which a plurality of unit substrates are collectively laminated at the same time after the respective buildup layers are separated and produced as a unit substrate to produce a printed circuit board.

Korean Patent Publication No. 10- 2011-0066044 (June 16, 2011)

According to the embodiment of the present invention, a printed circuit board and a package that can reduce the loss of the conductor pattern in forming the surface treatment layer can be provided.

1 shows a printed circuit board according to an embodiment of the invention.
Figure 2 shows a package according to an embodiment of the invention;
3 to 14 sequentially illustrate a method of manufacturing a printed circuit board according to an embodiment of the present invention.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprises" or "having" and the like are used to specify that there is a feature, a number, a step, an operation, an element, a component or a combination thereof described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof. In the specification, "on" means to be located above or below the object portion, and does not necessarily mean that the object is located on the upper side with respect to the gravitational direction.

In addition, the term " coupled " is used not only in the case of direct physical contact between the respective constituent elements in the contact relation between the constituent elements, but also means that other constituent elements are interposed between the constituent elements, Use them as a concept to cover each contact.

The sizes and thicknesses of the respective components shown in the drawings are arbitrarily shown for convenience of explanation, and thus the present invention is not necessarily limited to those shown in the drawings.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Hereinafter, embodiments of a printed circuit board and a package according to the present invention will be described in detail with reference to the accompanying drawings, wherein like reference numerals refer to like or corresponding components throughout. A duplicate description will be omitted.

Printed Circuit Boards and Packages

(Printed circuit board)

1 is a view illustrating a printed circuit board according to an embodiment of the present invention.

Referring to FIG. 1, a printed circuit board 1000 according to an embodiment of the present invention includes an insulating portion 20, outer conductor pattern layers 110 and 610, a first surface treatment layer 40, a seed layer 30 The second surface treatment layer 50 and the recess portion R and may further include the inner conductor pattern layers 210, 310, 410 and 510 and the vias 60. [

The insulating portion 20 is formed by laminating a plurality of insulating layers 120, 220, 320, 420, 520, and 620 to each other. The insulation portion 20 electrically insulates the first to sixth conductive pattern layers 120, 210, 310, 410, 510, and 610 from each other.

In the following description, a plurality of insulating layers 120, 220, 320, 420, 520, and 620 will be referred to as a first insulating layer 120, The second insulating layer 220, the third insulating layer 320, the fourth insulating layer 420, the fifth insulating layer 520, and the sixth insulating layer 620, respectively. However, when it is unnecessary to distinguish each other, the insulating layers 120, 220, 320, 420, 520, and 620 are collectively referred to as insulating layers.

When a plurality of conductor pattern layers 110, 210, 310, 410, 510, and 610 are to be distinguished from each other, a first conductor pattern layer Referred to as a first conductor pattern layer 110, a second conductor pattern layer 210, a third conductor pattern layer 310, a fourth conductor pattern layer 410, a fifth conductor pattern layer 510 and a sixth conductor pattern layer 610 . However, if it is unnecessary to distinguish each other, the first to sixth conductive pattern layers 110, 210, 310, 410, 510, and 610 or the conductive pattern layers 110, 210, 310, 410, 510, .

Each of the insulating layers 120, 220, 320, 420, 520 and 620 and the conductor pattern layers 110, 210, 310, 410, 510 and 610 may be formed in a number other than six have. For example, each of the insulating layers 120, 220, 320, 420, 520 and 620 and the conductor pattern layers 110, 210, 310, 410, 510 and 610 may be formed of four layers.

If necessary, the plurality of conductor pattern layers 110, 210, 310, 410, 510, and 610 may be formed on the outer conductor pattern layer 110 (corresponding to the outermost conductor pattern layer of the printed circuit board 1000 according to the present embodiment) And inner conductor pattern layers 210, 310, 410, and 510 formed between the inner conductor pattern layers 110 and 610 and the outer conductor pattern layers 110 and 610, respectively. 1, the outer conductor pattern layer corresponds to the first conductor pattern layer 110 and the sixth conductor pattern layer 610, and the inner conductor pattern layer corresponds to the second to fifth conductor pattern layers 210, 310, 410, 510). Hereinafter, for the sake of convenience, the outer conductor pattern refers to the first conductor pattern layer 110 unless otherwise noted.

Each of the insulating layers 120, 220, 320, 420, 520, and 620 may include any one of the conductor pattern layers 120, 210, 310, 410, 510, and 610, , 500, 600). That is, the first insulating layer 120 is included in the first unit substrate 100 together with the first conductor pattern layer 110. The first to sixth unit substrates 100, 200, 300, 400, 500, and 600 are formed separately from each other and then stacked at the same time, unlike the sequential layering method.

Each of the insulating layers 120, 220, 320, 420, 520, and 620 may be a photosensitive insulating layer made of a material that reacts with light including a photocurable resin.

Hereinafter, only the first insulating layer 120 among the insulating layers 120, 220, 320, 420, 520, and 620 will be described for convenience of explanation. In addition, the first insulating layer 120 will be referred to as a photosensitive insulating layer. At least one of the first to sixth insulating layers 120, 220, 320, 420, 520, and 620 may be a non-photosensitive insulating material such as a general prepreg or an ABF (Ajinomoto Build- It does not exclude that it is formed of a material.

The degree of curing of the photosensitive insulating layer 120 can be controlled by light. However, the photosensitive insulating layer 120 is also thermosetting, and the degree of curing can be controlled by heat.

Since the photosensitive insulating layer 120 is capable of a photolithography process, it is more advantageous to realize fine holes than a hole is formed in a non-photosensitive insulating layer such as a prepreg, and a plurality of Holes can be simultaneously formed, so that the hole forming process can be simplified. Further, the photosensitive insulating layer 120 can be formed into various shapes in a hole shape more easily due to the photolithography process. For example, the shape of the vertical cross-section of the hole may be an inverted trapezoid, an orthogonal trapezoid, a rectangle, or the like.

The photosensitive insulating layer 120 may be a positive type or a negative type. In the case of the positive type photosensitive insulating layer 120, the photopolymer polymer bond of the exposed portion is broken. Thereafter, when the developing process is performed, a portion where the photopolymer polymer bond breaks due to light is removed. In the case of the negative type photosensitive insulating layer 120, the exposed portions cause a photopolymerization reaction to form a three-dimensional network structure of a chain structure in a single structure. When a developing process is performed, do.

The photosensitive insulating layer 120 may contain an inorganic filler in the photocurable resin. The inorganic filler improves the rigidity of the photosensitive insulating layer 120 and reduces the thermal expansion coefficient. As the inorganic filler, silica (SiO ₂ ), alumina (Al ₂ O ₃ ), silicon carbide (SiC), barium sulfate (BaSO ₄ ), talc, clay, mica powder, aluminum hydroxide (AlOH ₃ ), magnesium hydroxide OH) ₂ ), calcium carbonate (CaCO ₃ ), magnesium carbonate (MgCO ₃ ), magnesium oxide (MgO), boron nitride (BN), aluminum borate (AlBO ₃ ), barium titanate (BaTiO ₃ ) and calcium zirconate ₃ ) may be used.

The outer conductor pattern layers 110 and 610 are formed on the outermost insulating layers 120 and 620, respectively. That is, the first conductor pattern layer 110 is formed on the first insulation layer 120 and the sixth conductor pattern layer 610 is formed on the sixth insulation layer 620. The outer layer conductor pattern layers 110 and 610 may include at least one of a signal pattern, a power pattern, a ground pattern, and an external connection terminal, which are conductor patterns of a conventional printed circuit board.

The outer conductor pattern layer 110 includes a first conductor pattern 111 and a second conductor pattern 112 which are respectively embedded in one surface of the insulation part 100. The first conductor pattern 111 and the second conductor pattern 112 correspond to the external connection terminals of the printed circuit board 1000 according to the present embodiment, unlike the conventional circuit patterns. Specifically, the first conductor pattern 111 is connected to an active element such as a die (700 in FIG. 2), and the second conductor pattern 112 is connected to another substrate such as a passive element such as an MLCC or a main board Can be connected.

1, the first conductor pattern 111 includes a seating pad 111-1 on which a die (700 in FIG. 2) is seated, and an external connecting terminal And a bonding pad 111-2 electrically connected through a wire (W in Fig. 2). In addition, the first conductor pattern 111 may further include a flip chip bonding pad (not shown) for flip chip bonding.

A passive element such as an MLCC may be electrically connected to the second conductor pattern 112 through SMT (Surface Mounting Technology). By way of example, the second conductor pattern may be electrically coupled to the MLCC by being coupled to an external electrode of the MLCC.

The first surface treatment layer 40 is formed on the first conductor pattern 111 and protrudes from one surface of the insulating portion 20. [ That is, the first surface treatment layer 40 is formed on the first conductor pattern 111 so as to protrude from the upper surface of the first insulating layer 120 with reference to FIG.

The first surface treatment layer 40 is formed on the first conductor pattern 111 so that signal transmission and heat transfer between the first conductor pattern 111 and the die 700 are facilitated. Specifically, the first surface treatment layer 40 formed on the seating pad 111-1 facilitates heat transfer between the die (700 in FIG. 2) and the seating pad 111-1, and the bonding pad 111 The first surface treatment layer 40 formed on the first bonding pad-2 facilitates signal transmission between the die (700 in FIG. 2) and the bonding pad 111-2. The first surface treatment layer 40 may include a material having excellent electrical conductivity and thermal conductivity. By way of example, the first surface treatment layer may comprise gold (Au).

The seed layer 30 is formed between the first conductor pattern 111 and the first surface treatment layer 40 and protrudes from one surface of the insulating portion 20. [ The seed layer 40 may be formed from a copper foil (CF in Fig. 3) of a carrier (C in Fig. 3) to be described later.

The first surface treatment layer 40 includes a material having a standard reduction potential higher than the standard reduction potential of the material forming the first conductor pattern 111 and / or the seed layer 30. [ For example, when the first conductor pattern 111 and the seed layer 30 are formed of copper (Cu), the first surface treatment layer 40 is made of gold (Au) having a standard reduction potential higher than the standard reduction potential of copper, ).

The second surface treatment layer 50 is formed on the second conductor pattern 112 and includes organic matter. That is, the second surface treatment layer 50 may be a normal OSP layer.

At least a part of the second surface treatment layer (50) is embedded in the insulating portion (20). As will be described later, the second conductor pattern 112 before the formation of the second surface treatment layer 50 is soft-etched. Therefore, after the soft-etching, the second conductor pattern 112 is recessed from the upper surface of the insulation portion 20 in Fig. As a result of the second surface treatment layer 50 being formed in the second conductor pattern 112 after soft-etching, at least a portion of the second surface treatment layer 50 is embedded in the insulating portion 20. [

The recess portion R is formed on both sides of the first conductor pattern 111 and / or the seed layer 30. [ The recessed portion R is formed by soft etching for forming the second surface treatment layer 50. [ That is, since the first surface treatment layer 40 formed of the material having the standard reduction potential higher than the standard reduction potential of the first conductor pattern 111 is formed on the first conductor pattern 111 at the time of soft etching, A recess R is formed by galvanic corrosion of the first conductor pattern 40.

And the etching phenomenon are conspicuous on both sides of the first conductor pattern 111 and / or the seed layer 30 not covered by the first surface treatment layer 40. However, in the case of the printed circuit board 1000 according to an embodiment of the present invention, the first conductor pattern 111 is formed in a state of being buried from one side of the insulating part 20. In the soft etching, The area of the conductor pattern 111 can be minimized. Therefore, the over-etching phenomenon of the first conductor pattern 111 which occurs during the soft etching for forming the second surface treatment layer 50 can be minimized.

The recessed portion R formed in the first conductor pattern 111 has a smaller sectional area from one surface of the insulating portion 20 toward the inside of the insulating portion 20. [ That is, the size of the recess portion R decreases from one surface of the insulating portion 20 to the inside of the insulating portion 20.

The inner conductor pattern layers 210, 310, 410, and 510 are formed inside the insulation portion 20. That is, each of the inner conductor pattern layers 210, 310, 410, and 510 is formed in each of the second to fifth insulation layers 220, 320, 420, and 520 and is located inside the insulation portion 20.

Each of the conductor pattern layers 110, 210, 310, 410, 510, and 610 is formed of copper (Cu), silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni) ), Gold (Au), platinum (Pt), or the like. The pattern shapes of the conductor pattern layers 110, 210, 310, 410, 510, and 610 may be all the same, but may be formed differently according to design needs.

The vias 60 connect the inner conductor pattern layers 210, 310, 410, 510 and the outer conductor pattern layers 110, 610 to each other. In addition, the vias 60 connect adjacent inner conductor pattern layers 210, 310, 410, and 510 to each other. In addition, the vias 60 may be stacked in a form similar to the stack vias, such as formed at the bottom of the seating pads 111-1 of Fig.

The vias 60 can be distinguished by a heat radiation via formed in the lower part of the seating pad 111-1 in FIG. 1 and a signal via formed in the lower part of the bonding pad 111-2 in FIG. The heat radiation vias can quickly remove the heat generated in the die (700 in Fig. 2) that is seated on the seating pad 111-1 toward the printed circuit board 1000 side according to this embodiment. The heat radiation vias may have a larger cross-sectional area than normal signal vias for rapid heat dissipation.

The via 60 includes a low melting point metal layer 62 having a melting point lower than the melting point of the high melting point metal layer 61 and the high melting point metal layer 61.

The high melting point metal layer 61 is made of copper (Cu), silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni), or the like, which has excellent electrical characteristics and has a melting point higher than the melting point of the low melting point metal layer 62 Titanium (Ti), gold (Au), platinum (Pt), or the like. For example, both the refractory metal layer 61 and the conductor pattern layers 110, 210, 310, 410, 510, and 610 may be formed of copper. In this case, both are formed of the same material, . Further, the process can be simplified and the production cost can be reduced as compared with the case where the two materials are formed of different materials. However, the above-mentioned examples are illustrative and the scope of the present invention is not limited thereto.

The melting point of the low melting point metal layer (62) is lower than the melting point of the high melting point metal layer (61). The low melting point metal layer 62 may be made of a solder material. Here, 'solder' means a metal material which can be used for solder, and may be an alloy including lead (Pb), but may not contain lead. For example, the solder may be tin (Sn), silver (Ag), copper (Cu), or an alloy of metals selected therefrom. Specifically, the solder used in the embodiment of the present invention may be an alloy containing tin, silver and copper having a tin (Sn) content of 90% or more with respect to the entire solder.

The low melting point metal layer 62 is formed by melting at least a part of a plurality of unit substrates 100, 200, 300, 400, 500, and 600 , 600).

Since the low melting point metal layer 62 is melted at least partly due to the temperature and pressure in the laminating process, the material and the material constituting the high melting point metal layer 61 or the conductor pattern layers 110, 210, 310, 410, 510 and 610 To form an Inter-Metallic Compound (IMC). The intermetallic compound layer improves the physical coupling force between the conductor pattern layers 110, 210, 310, 410, 510 and 610.

(package)

2 is a view of a package according to an embodiment of the present invention.

The package 2000 according to an embodiment of the present invention shown in FIG. 2 includes a printed circuit board 1000, a die 700, a passive element 800, and a coupling member 900.

Since the printed circuit board 1000 has been described above, a detailed description thereof will be omitted.

A die 700 is an electronic device formed through a semiconductor process as a semiconductor device. One surface of the die 700 is an active surface having external connection terminals and the other surface of the die 700 may be an inactive surface. In this embodiment, the other surface of the die 700 can be seated on the seating pad 111-1. The external connection terminal of the die 700 can be coupled with the bonding pad 111-2 of the printed circuit board 1000 through the wire W. [

The passive element 800 may be any one of an inductor, a capacitor, and a resistance element. That is, although the description herein has been made on the assumption that the passive element is an MLCC, the present invention is not limited thereto.

The coupling member 900 is a member that electrically couples the second conductor pattern 112 to the passive element 800 and / or another substrate such as a main board. The joining member 900 may be formed through an SMT process using solder. Due to the temperature during the SMT process, the second surface treatment layer 112 described above is removed.

Although not shown, the package 2000 according to the present embodiment includes a bonding layer or die formed between the seating pad 111-1 and the die 700 to fix the die 700, 700 to cover the die 700 to fix the die 700.

Manufacturing method of printed circuit board

3 to 14 are views sequentially illustrating a method of manufacturing a printed circuit board according to an embodiment of the present invention.

3 and 8 are views sequentially illustrating a process of manufacturing a unit substrate according to an embodiment of the present invention. FIGS. 9 and 10 are sectional views of FIGS. 3 to 8, 11 to 14 are views sequentially showing the post-batch lamination process. Fig.

(Manufacturing Method of Unit Substrate)

FIGS. 3 to 8 are views sequentially illustrating steps of manufacturing a unit substrate, which is applied to a method of manufacturing a printed circuit board according to an embodiment of the present invention. Hereinafter, a manufacturing process of the second unit substrate 200 shown in FIG. 9 will be described with reference to FIGS. 3 to 8. FIG.

First, referring to FIG. 3, a carrier C having a copper foil CF formed on both sides of a support portion SF is prepared. The support portion SF may be formed of any one of metal materials, inorganic materials, and organic materials having required rigidity. The copper foil CF can be formed on both sides of the support portion SF through a lamination process. Alternatively, the copper foil CF may be formed on both sides of the support portion SF through an electroless plating and an electrolytic plating process.

Next, referring to FIG. 4, a second conductor pattern layer 210 is selectively formed on the copper foil CF. The second conductor pattern layer 210 may be formed by a modified semi- additive process (MSAP) method in which a copper foil CF is used as a power supply layer for electrolytic plating. The second conductor pattern layer 210 is formed by forming a plating resist having a pattern opposite to that of the second conductor pattern layer 210 on the copper foil CF and performing electrolytic plating and removing the plating resist after completion of electrolytic plating . In the above example, the MSAP method in the conventional circuit pattern forming method is described. However, the second conductor pattern layer 210 may be formed by using any of Substrateive method, Full-Additive method, and Semi- .

Next, referring to FIG. 5, a second insulating layer 220 is formed on the second conductor pattern layer 210. The second insulating layer 220 may include a photocurable resin. The second insulating layer 220 may be formed by laminating an insulating film on the carrier C. [ That is, the second insulating layer 220 may be laminated to the second conductor pattern layer 210 using a vacuum laminator. Alternatively, the second insulating layer 220 may be formed by applying a liquid insulating material to the carrier C and curing it.

Next, referring to FIG. 6, a via hole VH is formed in the second insulating layer 220 to selectively expose a part of the second conductor pattern layer 210. The via hole VH can be formed by a photolithography method. That is, when the second insulating layer 220 is a photosensitive insulating layer, the via hole VH may be formed by selectively exposing and developing the second insulating layer 220. Alternatively, the via hole VH may be formed by laser drilling.

The second insulating layer 220 remains semi-cured (B-stage) before the collective lamination even if the second insulating layer 220 is subjected to the selective exposure process. For example, the second insulation layer 220, which has been subjected to the selective exposure process, may have a degree of curing of 10 to 20% as compared with the fully cured state (C-stage). If necessary, the second insulating layer 220 may be semi-cured through a separate process so as to have a 50% curability relative to the fully cured state (C-stage). The separate semi-curing process may be performed using UV light used in the photolithography process for forming the via hole VH. However, also in this case, the second insulating layer 220 is not completely cured until collectively laminated.

Next, referring to FIGS. 7 and 8, a refractory metal layer 61 and a refractory metal layer 62 are sequentially formed on the via hole VH.

The refractory metal layer 61 is formed through electrolytic plating. In the case of electrolytic plating, it includes both anisotropic and isotropic plating. The refractory metal layer 61 may be formed through copper electroplating to include copper (Cu). In forming the refractory metal layer 61 by electrolytic plating, the second conductor pattern layer 210 may function as a feed layer.

The low melting point metal layer 62 may be formed by selectively plating a low melting point metal such as solder or selectively applying a low melting point metal paste such as a solder paste and then drying the low melting point metal paste. The solder or solder paste may be based on tin, silver, copper or an alloy of the metals selected here. In addition, the solder paste used in the present invention may not contain flux. Solder pastes are sintered at relatively high temperatures (eg 800 ° C) and hardened at relatively low temperatures (eg 200 ° C). The solder paste used in this embodiment may be curable at a relatively low temperature to prevent complete curing of the second insulation layer 220 during curing of the solder paste.

The low melting point metal paste may have a relatively high viscosity and may maintain its shape after being formed on the high melting point metal layer 61. Further, the low melting point metal paste has low melting point metal particles, and the surface of the low melting point metal layer 62 formed by hardening the low melting point metal paste by these particles can be rugged.

Next, the second unit substrate 200 is separated from the carrier C by separating the support portion SF and the copper foil CF. At this time, although not shown, a cover film may be formed on the low melting point metal layer 20 and the second insulating layer 220. The cover film is configured to protect the low melting point metal layer 20 and the second insulating layer 220 until collectively laminated, and is separated from the second unit substrate 200 immediately before the batch lamination process.

The first unit substrate 100 and the third to sixth unit substrates 300, 400, 500, and 600 may be manufactured through the same process, although the second unit substrate 200 has been described above.

In the above description and FIGS. 3 to 8, the process for forming a unit substrate on only one side of the carrier C has been described and shown. However, a process for forming the same unit substrate on the other side of the carrier, May be applied.

(Step of collectively laminating unit substrates)

Figs. 9 and 10 are views showing the lamination of a plurality of unit substrates manufactured through Figs. 3 to 8 collectively.

Referring to FIG. 9, a plurality of unit substrates 100, 200, 300, 400, 500, and 600 are vertically arranged. At this time, a plurality of unit substrates 100, 200, 300, 400, 500, and 600 are aligned with each other through alignment marks formed on the plurality of unit substrates 100, 200, 300, 400, The second to fifth unit substrates 200, 300, 400, and 500 except for the first and sixth unit substrates 100 and 600 are aligned after the copper foil CF is removed. The copper foil CF remaining on the first and sixth unit substrates 100 and 600 becomes a power supply layer when plating the first surface treatment layer 40 to be described later.

Referring to FIG. 10, a plurality of aligned unit substrates 100, 200, 300, 400, 500, and 600 are bonded together at a high temperature using a V-press laminator or the like. In the batch lamination, the temperature may be set at 180 to 200 DEG C and the press pressure may be set to 30 to 50 kg / cm < ² > (120, 220, 320, 420, 520, 620) or a component of the low melting point metal layer (62). In particular, the temperature at the time of laminating may be more than the melting point of the low melting point metal layer 62.

The low melting point metal layer 20 is spread toward the insulating layers 120, 220, 320, 420, 520, and 620 by the pressure during the laminating operation, 20 may be different from each other.

The first to sixth insulating layers 120, 220, 320, 420, 520, and 620 in the semi-cured state are completely cured by the temperature and the pressure at the time of the laminating.

Next, referring to FIG. 11, a first surface treatment layer 40 is formed on the first insulating layer 120 and / or the sixth insulating layer 620. As described above, the copper foil CF remains in the first and sixth unit substrates 100 and 600. When the first surface treatment layer 40 is plated, .

The first surface treatment layer 40 may be formed by forming a plating resist having a reverse pattern with the first surface treatment layer 40 on the copper foil CF, performing electrolytic plating, and then removing the plating resist. The first surface treatment layer 40 may comprise gold (Au) having good electrical conductivity and thermal conductivity for rapid signal transmission and heat transfer to a die (700 of FIG. 2). In addition, although not shown, a bonding layer may be formed between the first surface treatment layer 40 and the copper foil CF. The bonding layer may include nickel (Ni) having a relatively good bonding strength with the copper foil (CF). The bonding layer may be formed through electrolytic plating using a copper foil (CF) as a power supply layer.

Next, referring to FIG. 12, the seed layer 30 is formed by selectively removing the copper foil CF. That is, the seed layer 30 is formed by removing the area of the copper foil CF where the first surface treatment layer 40 is not formed. The seed layer 30 can be removed by selectively etching (e.g., quick-etching and half-etching) the copper foil CF. At this time, the first surface treatment layer 40 functions as an etching resist. By selectively etching the copper foil CF, the second conductor pattern 112 is exposed to the outside.

Next, referring to FIG. 13, soft etching is performed. The soft etching process is performed before the second surface treatment layer 50 is formed on the second conductor pattern 112 and the roughness is formed on the surface of the second conductor pattern 112 to form the second conductor pattern 112 Is a step for improving the bonding force with the second surface treatment layer (50).

The soft etch is performed using an etchant that chemically reacts with the constituent material of the second conductor pattern 112. If the second conductor pattern 112 is formed of copper (Cu), soft etching may be performed with a copper etchant. The first surface treatment layer 40 is formed on the first conductor pattern 111 and the first surface treatment layer 40 is formed on the surface of the first conductor pattern 111 and / Recessed portions R are formed on both sides of the first conductor pattern 111 and / or the seed layer 30 by bar soft etching, which is formed of a material having a standard reduction potential higher than the potential.

Next, referring to FIG. 14, a second surface treatment layer 50 is formed on the second conductor pattern 112. The second surface treatment layer 50 may be a conventional OSP layer containing organic matter.

Meanwhile, although not shown, a pretreatment process may be performed to bond the functional groups to the surface of the second conductor pattern 112 before the second surface treatment layer 50 is formed after soft-etching.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

C: Carrier
CF: Copper foil
R: recessed part
SF: Support
W: Wire
VH: Via hole
20:
30: Seed layer
40: first surface treatment layer
50: second surface treatment layer
60: Via
61: Refractory metal layer
62: Low melting point metal layer
100, 200, 300, 400, 500, 600: unit substrate
110, 210, 310, 410, 510, 610:
120, 220, 320, 420, 520, 620: insulating layer
111: first conductor pattern
111-1: seat pad
111-2: Bonding pad
112: second conductor pattern
700: Die
800: Passive element
900: coupling member
1000: printed circuit board
2000: Package

Claims (10)

Insulating portion; And
An outer conductor pattern layer including a first conductor pattern and a second conductor pattern embedded in one surface of the insulation part;
A first surface treatment layer formed on the first conductor pattern and projecting from one surface of the insulating portion;
A seed layer formed between the first conductor pattern and the first surface treatment layer and protruding from one surface of the insulating portion;
A second surface treatment layer formed on the second conductor pattern and including an organic matter; And
And a recess portion formed on both sides of the first conductor pattern and / or the seed layer.
The method according to claim 1,
Wherein the first surface treatment layer comprises:
And a material having a standard reduction potential higher than a standard reduction potential of the material forming the first conductor pattern and / or the seed layer.
The method according to claim 1,
And at least a portion of the second surface treatment layer is embedded in the insulating portion.
The method according to claim 1,
The recess portion formed in the first conductor pattern,
Wherein the cross-sectional area decreases from one surface of the insulating portion toward the inside of the insulating portion.
The method according to claim 1,
An inner conductor pattern layer formed inside the insulation part; And
Further comprising vias connecting the inner conductor pattern layer and the outer conductor pattern layer to each other.
6. The method of claim 5,
The vias may include,
The high melting point metal layer and
Melting metal layer having a melting point lower than a melting point of the refractory metal layer.
The method according to claim 6,
Wherein the low melting point metal layer comprises tin (Sn).
The method according to claim 1,
Wherein the insulating portion comprises a photocurable resin.
A printed circuit board including a first pad portion and a second pad portion formed on one surface of the insulating portion;
A die coupled to the first pad portion; And
And a passive element coupled to the second pad portion,
Wherein the first pad portion comprises:
A conductor pattern embedded in one surface of the insulating portion,
A seed layer formed on the conductor pattern,
A surface treatment layer formed on the seed layer and protruding from one surface of the insulating portion and having a standard reduction potential higher than a standard reduction potential of the conductor pattern and /
And a recess portion formed on both sides of the conductor pattern and / or the seed layer.
10. The method of claim 9,
And a coupling member interposed between the second pad portion and the passive element to connect the second pad portion and the passive element, and at least a portion of which is embedded in one surface of the insulation portion.

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