CN115190701A - Embedded circuit packaging substrate and processing method thereof - Google Patents
Embedded circuit packaging substrate and processing method thereof Download PDFInfo
- Publication number
- CN115190701A CN115190701A CN202210523894.7A CN202210523894A CN115190701A CN 115190701 A CN115190701 A CN 115190701A CN 202210523894 A CN202210523894 A CN 202210523894A CN 115190701 A CN115190701 A CN 115190701A
- Authority
- CN
- China
- Prior art keywords
- copper layer
- circuit
- bonding pad
- embedded
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
The application discloses embedded line packaging substrate and a processing method thereof, wherein the processing method of the embedded line packaging substrate comprises the following steps: providing a circuit board with a pad embedded on the surface; the bonding pad and a circuit copper layer of the circuit board are arranged at intervals; sputtering a thin copper layer on the surface of the circuit board by using a sputtering process so as to form connection between the bonding pad and the circuit copper layer; removing part of the thin copper layer on the surface of the bonding pad to expose part of the surface of the bonding pad; thickening part of the surface of the bonding pad by using an electroplating process; and removing the thin copper layer to obtain the embedded type circuit packaging substrate. By the method, the thickness of the bonding pad is increased, and the welding quality between the bonding pad and a subsequent welding object is further guaranteed.
Description
Technical Field
The present disclosure relates to a package board, and more particularly, to an embedded circuit package substrate and a method for fabricating the same.
Background
An ETS (Embedded Trace Substrate) product is a circuit board with Embedded circuits, and is typically characterized in that the Embedded circuits are Embedded in a dielectric layer.
The embedded circuit and the bonding pad of the ETS product are embedded in the medium layer, and in the micro-etching processes of rapid etching, solder resistance and the like, a certain height difference is formed between the embedded circuit and the bonding pad and the PP medium layer, namely the embedded line depth.
In the product packaging process, the buried wire depth affects the welding of the solder ball and the bonding pad, and especially when the buried wire depth is large, the abnormal conditions such as poor welding and product failure can be caused.
Disclosure of Invention
The technical problem mainly solved by the application is to provide an embedded circuit packaging substrate and a processing method thereof, so that the thickness of a bonding pad is increased, and the welding quality between the bonding pad and a subsequent welding object is further ensured.
The application provides a processing method of an embedded line packaging substrate, which comprises the following steps: providing a circuit board with a pad embedded on the surface; the welding disc and a circuit copper layer of the circuit board are arranged at intervals; sputtering a thin copper layer on the surface of the circuit board by using a sputtering process so as to enable the bonding pad to be electrically connected with the circuit copper layer around the bonding pad; removing part of the thin copper layer on the surface of the bonding pad to expose part of the surface of the bonding pad; electroplating a copper layer on part of the surface of the bonding pad by using an electroplating process to thicken part of the bonding pad; and removing the thin copper layer to obtain the embedded circuit packaging substrate.
Wherein the surface of the pad is lower than the surface of the circuit board.
Wherein, the step of electroplating a copper layer on the surface of the partial bonding pad by using an electroplating process to thicken the partial bonding pad comprises the following steps: and electroplating a copper layer on the surface of the partial welding disc by utilizing an electroplating process to thicken the welding disc, so that the thickened surface of the welding disc is not lower than the surface of the circuit board.
Wherein the step of removing a portion of the thin copper layer from the surface of the pad to expose a portion of the surface of the pad comprises: attaching an anti-etching film on the surface of the thin copper layer, and exposing the thin copper layer on the first surface of the bonding pad; etching the thin copper layer of the first surface to expose a first surface of the pad.
Wherein, the step of thickening a part of the surface of the bonding pad by using an electroplating process comprises the following steps: pasting an anti-plating film on the surface of the thin copper layer, and exposing the second surface of the bonding pad; electroplating the second surface of the bonding pad to thicken the second surface of the bonding pad; wherein the area of the second surface is smaller than the area of the first surface.
The step of removing the thin copper layer to obtain the embedded circuit package substrate includes: and carrying out whole-board etching on the circuit board by using an etching process to remove the residual thin copper layer and expose the bonding pad to obtain the embedded circuit packaging substrate.
The step of providing the circuit board with the surface embedded with the pad comprises the following steps: providing a substrate; electroplating an auxiliary copper layer on the surface of the substrate by using a flash plating process; manufacturing a circuit copper layer on the surface of the auxiliary copper layer by utilizing a graphic manufacturing process; laminating a dielectric layer on the surface of the circuit copper layer to embed the circuit copper layer; and removing the substrate, and etching the auxiliary copper layer on the surface of the circuit copper layer to obtain the circuit board.
Wherein, after the step of laminating a dielectric layer on the surface of the circuit copper layer to embed the circuit copper layer, the method further comprises the following steps: performing laser drilling on the dielectric layer; plating thin copper on the surface of the dielectric layer and in the hole by using a flash plating process; manufacturing an outer layer circuit copper layer on the surface of the thin copper layer by using a graphic manufacturing process; the step of removing the substrate and etching away the auxiliary copper layer on the surface of the circuit copper layer to obtain the circuit board comprises the following steps: and etching away the auxiliary copper layer and the thin copper to obtain the circuit board.
The step of providing the circuit board with the surface embedded with the pad comprises the following steps: providing a substrate; electroplating auxiliary copper layers on the surfaces of two opposite sides of the substrate; respectively manufacturing a first circuit copper layer and a second circuit copper layer on the surface of the auxiliary copper layer; laminating a first dielectric layer and a second dielectric layer on the surfaces of the first circuit copper layer and the second circuit copper layer respectively; drilling holes in the surfaces of the first dielectric layer and the second dielectric layer; plating thin copper on the surface of the first dielectric layer, the surface of the second dielectric layer and the hole; respectively manufacturing a first outer layer circuit copper layer and a second outer layer circuit copper layer on the surface of the thin copper by using a graph manufacturing process; carrying out plate separation treatment on the substrate to obtain two identical plates to be etched; and etching the board to be etched to remove the auxiliary copper layer and the thin copper on the surface of the board to be etched, thereby obtaining the circuit board.
The application also provides an embedded circuit packaging substrate, wherein a bonding pad is embedded in the surface of one side of the embedded circuit packaging substrate; the bonding pad is exposed on the surface of the embedded circuit packaging substrate, and part of the bonding pad is not lower than the surface of the embedded circuit packaging substrate.
The beneficial effect of this application is: the embedded type circuit packaging substrate with the thickened bonding pad is obtained by sputtering a thin copper layer on the surface of the circuit board, removing the thin copper layer on the surface of the bonding pad to expose the region of the bonding pad to be thickened, thickening the region of the bonding pad to be thickened by utilizing an electroplating process, and removing the thin copper layer on other regions on the surface of the circuit board, so that the good contact between the bonding pad on the surface of the embedded type circuit packaging substrate and other plates is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic flow chart illustrating a method for processing an embedded circuit package substrate according to a first embodiment of the present invention;
fig. 2 is a schematic flow chart illustrating a second embodiment of a method for processing an embedded circuit package substrate according to the present application;
FIG. 3 is a schematic diagram illustrating a structural change of the circuit board in steps S21-S27 of FIG. 2;
FIG. 4 is a schematic flow chart of a first embodiment of a method for manufacturing a circuit board according to the present application;
FIG. 5 is a schematic structural diagram of a first embodiment of a circuit board according to the present application;
FIG. 6 is a schematic flow chart of a second embodiment of the method for manufacturing a circuit board according to the present application;
FIG. 7 is a schematic diagram of a second embodiment of a circuit board of the present application;
FIG. 8 is a schematic flow chart of a third embodiment of a method for manufacturing a circuit board according to the present application;
fig. 9 is a schematic structural diagram of an embedded circuit package substrate according to an embodiment of the present disclosure.
Detailed Description
The following describes in detail the embodiments of the present application with reference to the drawings attached hereto.
In the following description, for purposes of explanation and not limitation, specific details are set forth such as particular system structures, interfaces, techniques, etc. in order to provide a thorough understanding of the present application.
The terminology used in the embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the examples of this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise, the "plural" includes at least two in general, but does not exclude the presence of at least one.
It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
It should be understood that the terms "comprises," "comprising," or any other variation thereof, as used herein, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising 8230; \8230;" 8230; "does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.
It should be noted that if directional indications (such as up, down, left, right, front, back, 8230; \8230;) are referred to in the embodiments of the present application, the directional indications are only used to explain the relative positional relationship between the components, the motion situation, etc. in a specific posture (as shown in the attached drawings), and if the specific posture is changed, the directional indications are correspondingly changed.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein may be combined with other embodiments.
Referring to fig. 1, fig. 1 is a schematic flow chart of a first embodiment of a method for processing an embedded circuit package substrate according to the present application, and as shown in fig. 1, the method for processing an embedded circuit package substrate includes:
step S11: a circuit board with a pad buried in the surface thereof is provided.
The surface of the circuit board is provided with a bonding pad and a circuit copper layer, and the bonding pad and the circuit copper layer are arranged at intervals. The pads are also copper layers for electrical connection to other circuit boards.
In the embodiment, before the thickening, the bonding pad is embedded in the circuit board, and the surface of the bonding pad is exposed on the surface of the circuit board. Wherein, the surface of the bonding pad is lower than the surface of the circuit board, namely the bonding pad is sunken in the circuit board. In the present embodiment, the circuit copper layer is also recessed in the circuit board, and in other embodiments, the circuit copper layer may not be recessed in the circuit board, which is not limited herein.
Step S12: and sputtering a thin copper layer on the surface of the circuit board by using a sputtering process so as to connect the bonding pad with the circuit copper layer.
The thin copper layer covers the whole surface of the circuit board and comprises a bonding pad surface and a circuit copper layer surface which are covered in the circuit board, so that the bonding pad and the circuit copper layer are electrically connected through the thin copper layer. Thin copper layers are sputtered on the surface of the circuit board, so that the welding pad to be thickened is electrically connected with the circuit copper layer, and the copper layer can be electroplated on the surface of the welding pad when subsequent electroplating is facilitated. Wherein, electroplating the copper layer needs to make the area to be plated conductive.
Step S13: and removing part of the thin copper layer on the surface of the bonding pad to expose part of the surface of the bonding pad.
The method specifically comprises the following steps: pasting an anti-etching film on the surface of the thin copper layer, and exposing the thin copper layer on the first surface of the bonding pad; the thin copper layer of the first surface is etched to expose the first surface of the bonding pad. The first surface is a partial surface of the bonding pad.
Step S14: and thickening part of the surface of the bonding pad by using an electroplating process.
Specifically, a copper layer is electroplated on part of the surface of the bonding pad by an electroplating process, so that the surface of the copper layer is not lower than the surface of the circuit board, and poor contact or product failure caused by over-low bonding pad during subsequent welding with other plates is avoided. By thickening partial surface of the bonding pad, the yield of the bonding pad contacting with other plates is improved.
The method specifically comprises the following steps: coating an anti-plating film on the surface of the thin copper layer, and exposing the second surface of the bonding pad; electroplating the second surface of the bonding pad to thicken the second surface of the bonding pad. Wherein the second surface is also a partial surface of the bonding pad.
In this embodiment, the area of the second surface is smaller than that of the first surface, i.e. the coverage area of the anti-plating film is larger than that of the anti-etching film. In other embodiments, the area of the second surface may also be the same as, i.e. coincident with, the area of the first surface.
Step S15: and removing the thin copper layer to obtain the embedded circuit packaging substrate.
The method specifically comprises the following steps: and etching the whole surface of the circuit board by using an etching solution, namely etching the bonding pad and the circuit copper layer simultaneously to remove the circuit copper layer and the thin copper layer on the surface of the bonding pad and thin the thickened copper layer of the bonding pad. The surface of the thinned bonding pad is not lower than that of the circuit board, so that the yield of the embedded line packaging substrate is ensured.
The beneficial effect of this embodiment is: the embedded type circuit packaging substrate with the thickened pad is obtained by sputtering a thin copper layer on the surface of the circuit board, removing the thin copper layer on the surface of the pad to expose the area of the pad to be thickened, thickening the area of the pad to be thickened by utilizing an electroplating process, and removing the thin copper layer on other areas on the surface of the circuit board, so that the good contact between the pad on the surface of the embedded type circuit packaging substrate and other plates is improved.
Referring to fig. 2 and 3, fig. 2 is a schematic flow chart of a second embodiment of the method for processing an embedded circuit package substrate of the present application, and fig. 3 is a schematic structural change diagram of a circuit board in steps S21-S27 of fig. 2. As shown in fig. 2, includes:
step S21: a circuit board with a pad embedded in the surface is provided.
The surface of the circuit board is provided with a bonding pad and a circuit copper layer, and the bonding pad and the circuit copper layer are arranged at intervals.
In the present embodiment, the bonding pad is embedded in the circuit board, and the surface thereof is exposed on the surface of the circuit board. Wherein, the surface of the bonding pad is lower than the surface of the circuit board, namely the bonding pad is sunken in the circuit board. In the present embodiment, the circuit copper layer is also recessed in the circuit board, and in other embodiments, the circuit copper layer may not be recessed in the circuit board, which is not limited herein.
Specifically, referring to fig. 3 a, the surface of the circuit board includes a bonding pad 31 and a circuit copper layer 32, and the bonding pad 31 and the circuit copper layer 32 are spaced apart from each other.
Step S22: and sputtering a thin copper layer on the surface of the circuit board by using a sputtering process so as to connect the bonding pad with the circuit copper layer.
The thin copper layer covers the whole surface of the circuit board and comprises a bonding pad surface and a circuit copper layer surface which are covered in the circuit board, so that the bonding pad and the circuit copper layer are electrically connected through the thin copper layer. The thin copper layer is sputtered on the surface of the circuit board, so that the bonding pad to be thickened is electrically connected with the circuit copper layer, and the copper layer can be electroplated on the surface of the bonding pad when subsequent electroplating is facilitated. Wherein, electroplating the copper layer needs to make the area to be plated conductive.
Specifically, referring to fig. 3 b, a thin copper layer 33 is coated on the surface of the bonding pad 31 and the surface of the circuit copper layer 32 of the circuit board.
Step S23: and attaching an anti-etching film on the surface of the thin copper layer, and exposing the thin copper layer on the first surface of the bonding pad.
The method specifically comprises the steps of pasting an anti-etching film on the whole surface of a thin copper layer, covering the anti-etching film on part of the surface of the thin copper layer by using an exposure and development process, and exposing the thin copper layer on the first surface of the bonding pad, so that the thin copper layer on the first surface is conveniently etched. Specifically, as shown in fig. 3 c, the etching-resistant film 34 is attached to the surface of the circuit copper layer 32 and a portion of the surface of the bonding pad 31, exposing the first surface of the bonding pad 31, where the first surface is a surface to be thickened.
Step S24: the thin copper layer of the first surface is etched to expose the first surface of the bonding pad.
The method also comprises removing the etching-resistant dry film after the step. Specifically, referring to fig. 3 d, a portion of the surface of the bonding pad 31 is exposed, and another portion of the surface is electrically connected to the circuit copper layer 32 through the thin copper layer 33 for electroplating. Wherein the bonding pad 31 further comprises a lead copper layer (not shown in fig. 3) forming a connection with its surrounding line copper layer 32.
Step S25: and pasting an anti-plating film on the surface of the thin copper layer, and exposing the second surface of the bonding pad.
The area of the second surface is smaller than that of the first surface, so that the phenomenon that the thickened bonding pad is electrically connected with the circuit board through the thin copper layer due to the fact that the thin copper layer is not etched completely is avoided, and therefore product failure is caused.
Specifically, as shown in e of fig. 3, the plating resist film 35 covers a portion of the surfaces of the wiring copper layer 32 and the bonding pad 31, and exposes the second surface of the bonding pad 31. Wherein the second surface is smaller than the first surface, i.e. the second surface is part of the first surface. In other embodiments, the second surface and the first surface may also be the same.
Step S26: and electroplating the second surface of the bonding pad to thicken the second surface of the bonding pad.
And removing the anti-plating film on the surface of the circuit board after the step to obtain the circuit board with the thickened pad part.
Specifically, as shown in f of fig. 3, at least a portion of the surface of the bonding pad 31 is not lower than the surface of the circuit board, so as to improve the yield of the soldering between the bonding pad 31 and other boards, and avoid poor contact between the bonding pad and the other boards due to the bonding pad 31 being too lower than the surface of the circuit board.
Step S27: and removing the thin copper layer to obtain the embedded circuit packaging substrate.
The method specifically comprises the following steps: and etching the whole surface of the circuit board by using an etching solution, namely etching the bonding pad and the circuit copper layer simultaneously to remove the circuit copper layer and the thin copper layer on the surface of the bonding pad and thin the thickened copper layer of the bonding pad. The surface of the thinned bonding pad is not lower than the surface of the circuit board, so that the yield of the embedded circuit packaging substrate is ensured. Specifically, referring to fig. 3 g, at least a portion of the surface of the bonding pad 31 is not lower than the surface of the circuit board.
The beneficial effect of this embodiment is: the embedded type circuit packaging substrate with the thickened bonding pad is obtained by sputtering a thin copper layer on the surface of the circuit board, removing the thin copper layer on the surface of the bonding pad to expose the region of the bonding pad to be thickened, thickening the region of the bonding pad to be thickened by utilizing an electroplating process, and removing the thin copper layer on other regions on the surface of the circuit board, so that the good contact between the bonding pad on the surface of the embedded type circuit packaging substrate and other plates is improved.
Referring to fig. 4, fig. 4 is a schematic flow chart of a first embodiment of the method for manufacturing a circuit board according to the present application. As shown in fig. 4, includes:
step S41: a substrate is provided.
The substrate is an insulating medium layer.
Step S42: and electroplating an auxiliary copper layer on the surface of the substrate by using a flash plating process.
The auxiliary copper layer covers the whole surface of the substrate, so that the surface of the substrate can be electroplated with copper.
Step S43: and manufacturing a circuit copper layer on the surface of the auxiliary copper layer by using a graphic manufacturing process.
The method specifically comprises the steps of manufacturing a graphic dry film on the surface of the auxiliary copper layer by using a film pasting, exposing and developing process, and then electroplating a circuit copper layer on the surface of the auxiliary copper layer by using an electroplating process. Wherein, the circuit copper layer is distributed in a preset pattern.
Step S44: laminating a dielectric layer on the surface of the circuit copper layer to embed the circuit copper layer.
The dielectric layer covers the surface of the circuit copper layer and the surface of the auxiliary copper layer so as to bury the circuit copper layer between the dielectric layer and the auxiliary copper layer.
Step S45: and removing the substrate, and etching the auxiliary copper layer on the surface of the circuit copper layer to obtain the circuit board.
In this embodiment, when the auxiliary copper layer and the thin copper layer are etched, the circuit copper layer and the outer circuit copper layer are partially etched, so that the circuit copper layer embedded in the dielectric layer is recessed in the dielectric layer, thereby causing poor soldering.
Referring to fig. 5, fig. 5 is a schematic structural diagram of a circuit board according to a first embodiment of the present application. As shown in fig. 5, the circuit copper layer 51 is embedded in the dielectric layer 52 of the circuit board, and its surface is exposed on one side surface of the dielectric layer 52. The wiring copper layer 51 includes the pad 31 and the wiring copper layer 32 in the above embodiment.
Fig. 6 is a schematic flowchart illustrating a second embodiment of a method for manufacturing a circuit board according to the present application. As shown in fig. 6, includes:
step S61: a substrate is provided.
The substrate is an insulating medium layer.
Step S62: and electroplating an auxiliary copper layer on the surface of the substrate by using a flash plating process.
The auxiliary copper layer covers the whole surface of the substrate, so that the surface of the substrate can be electroplated with copper.
Step S63: and manufacturing a circuit copper layer on the surface of the auxiliary copper layer by using a graphic manufacturing process.
The method specifically comprises the steps of manufacturing a pattern dry film on the surface of the auxiliary copper layer by using a film pasting, exposure and developing process, and then electroplating a circuit copper layer on the surface of the auxiliary copper layer by using an electroplating process. Wherein, the circuit copper layer is distributed in a preset pattern.
Step S64: laminating a dielectric layer on the surface of the circuit copper layer to embed the circuit copper layer.
The dielectric layer covers the surface of the circuit copper layer and the surface of the auxiliary copper layer so as to bury the circuit copper layer between the dielectric layer and the auxiliary copper layer.
Step S65: and carrying out laser drilling on the dielectric layer.
And carrying out laser drilling on the dielectric layer to expose the surface of part of the circuit copper layer, so that the circuit copper layer is connected with the copper layers of other layers.
Step S66: and plating thin copper on the surface of the dielectric layer and in the hole by using a flash plating process.
The thin copper is coated on the surface of the dielectric layer and the side wall of the hole to facilitate copper plating on the dielectric layer and the hole wall.
Step S67: and manufacturing an outer circuit copper layer on the surface of the thin copper layer by using a graphic manufacturing process.
And manufacturing a pattern dry film on the surface of the thin copper by using a film pasting, exposing and developing process, and then electroplating an outer circuit copper layer on the surface of the thin copper by using an electroplating process.
Step S68: and removing the substrate, and etching away the auxiliary copper layer and the thin copper to obtain the circuit board.
In this embodiment, when the auxiliary copper layer and the thin copper layer are etched, the circuit copper layer and the outer circuit copper layer are partially etched, so that the circuit copper layer embedded in the dielectric layer is recessed in the dielectric layer, thereby causing poor soldering.
Specifically, please refer to fig. 7 for a structure of the circuit board, and fig. 7 is a schematic structural diagram of a circuit board according to a second embodiment of the present application. As shown in fig. 7, the circuit board includes a circuit copper layer 71 and an outer circuit copper layer 72, the circuit copper layer 71 is embedded in a dielectric layer 701 of the circuit board, and the outer circuit copper layer 72 is located on a side of the dielectric layer 701 away from the circuit copper layer 71. The circuit copper layer 71 is recessed in the dielectric layer 701, and the surface of the circuit copper layer 71 is lower than the surface of the dielectric layer 701.
Referring to fig. 8, fig. 8 is a schematic flow chart of a third embodiment of the method for manufacturing a circuit board according to the present application. As shown in fig. 8, includes:
step S81: a substrate is provided.
The substrate is an insulating medium layer.
Step S82: and electroplating auxiliary copper layers on the opposite side surfaces of the substrate.
The auxiliary copper layers are covered on the two opposite side surfaces of the substrate, so that the surface of the substrate can be electroplated with copper.
Step S83: and respectively manufacturing a first circuit copper layer and a second circuit copper layer on the surface of the auxiliary copper layer.
The method specifically comprises the steps of manufacturing a graphic dry film on the surface of the auxiliary copper layer by using a film pasting, exposing and developing process, and then electroplating a circuit copper layer on the surface of the auxiliary copper layer by using an electroplating process. Wherein, the circuit copper layer is distributed in a preset pattern.
Step S84: and laminating a first dielectric layer and a second dielectric layer on the surfaces of the first circuit copper layer and the second circuit copper layer respectively.
The first dielectric layer covers the surface of the first circuit copper layer, and the second dielectric layer covers the surface of the second circuit copper layer so as to embed the first circuit copper layer and the second circuit copper layer.
Step S85: and drilling holes on the surfaces of the first dielectric layer and the second dielectric layer.
And laser drilling is carried out on the dielectric layer to expose the surface of part of the circuit copper layer, so that the first circuit copper layer and the second circuit copper layer are connected with the copper layers of other layers.
Step S86: and plating thin copper on the surface of the first dielectric layer, the surface of the second dielectric layer and the hole.
Step S87: and respectively manufacturing a first outer layer circuit copper layer and a second outer layer circuit copper layer on the surface of the thin copper layer by using a graph manufacturing process.
Step S88: and carrying out plate separation treatment on the substrate to obtain two identical plates to be etched.
Step S89: and etching the board to be etched to remove the auxiliary copper layer and the thin copper on the surface of the board to be etched so as to obtain two identical circuit boards.
By the method, two identical circuit boards can be simultaneously manufactured, so that the production efficiency of the circuit boards is improved.
The present application further provides an embedded circuit package substrate, referring to fig. 9 in detail, fig. 9 is a schematic structural diagram of an embodiment of the embedded circuit package substrate of the present application. As shown in fig. 9, a pad 901 is embedded in a surface of one side of the buried circuit package substrate 91, the pad 901 is exposed on the surface of the buried circuit package substrate 91, and a part of the surface of the pad 901 is not lower than the surface of the buried circuit package substrate 91.
Through the structure, the embedded line packaging substrate can improve the contact area between the bonding pad and a subsequent welding object through the bonding pad which is not lower than the dielectric layer, and further ensures the welding quality between the bonding pad and the subsequent welding object.
The above embodiments are merely examples and are not intended to limit the scope of the present disclosure, and all modifications, equivalents, and flow charts using the contents of the specification and drawings of the present disclosure or those directly or indirectly applied to other related technical fields are intended to be included in the scope of the present disclosure.
Claims (10)
1. A processing method of an embedded line package substrate is characterized in that the processing method of the embedded line package substrate comprises the following steps:
providing a packaging substrate with a pad embedded on at least one side surface;
sputtering a thin copper layer on the surface of one side of the circuit board, in which the bonding pad is embedded, by using a sputtering process so as to form electric connection between the bonding pad and the circuit copper layer around the bonding pad;
removing part of the thin copper layer on the surface of the bonding pad to expose part of the surface of the bonding pad;
electroplating a copper layer on the surface of the part of the bonding pad by using an electroplating process to thicken the part of the bonding pad;
and removing the thin copper layer to obtain the embedded circuit packaging substrate.
2. The method of processing the embedded circuit package substrate as claimed in claim 1, wherein a portion of the surface of the pad is lower than the surface of the circuit board.
3. The method of processing the embedded circuit package substrate as claimed in claim 2, wherein the step of plating a copper layer on the surface of the partial bonding pad by using an electroplating process to thicken the partial bonding pad comprises:
and electroplating a copper layer on the surface of the partial welding disc by utilizing an electroplating process to thicken the welding disc, so that the thickened surface of the welding disc is not lower than the surface of the circuit board.
4. The method of processing the buried circuit package substrate of claim 1, wherein the step of removing a portion of the thin copper layer on the surface of the pad to expose a portion of the surface of the pad comprises:
attaching an anti-etching film on the surface of the thin copper layer, and exposing the thin copper layer on the first surface of the bonding pad;
etching the thin copper layer of the first surface to expose a first surface of the pad.
5. The method as claimed in claim 4, wherein the step of electroplating a copper layer on the surface of the pad to thicken the pad by using an electroplating process comprises:
pasting an anti-plating film on the surface of the thin copper layer, and exposing the second surface of the bonding pad;
electroplating the second surface of the bonding pad to thicken the second surface of the bonding pad; wherein the area of the second surface is smaller than the area of the first surface.
6. The method as claimed in claim 1, wherein the step of removing the thin copper layer to obtain the buried wiring package substrate comprises:
and carrying out whole-board etching on the circuit board by using an etching process to remove the residual thin copper layer and expose the bonding pad to obtain the embedded circuit packaging substrate.
7. The method as claimed in claim 1, wherein the step of providing a circuit board with embedded pads comprises:
providing a substrate;
electroplating an auxiliary copper layer on the surface of the substrate by using a flash plating process;
manufacturing a circuit copper layer on the surface of the auxiliary copper layer by using a graph manufacturing process;
laminating a dielectric layer on the surface of the circuit copper layer to embed the circuit copper layer;
and removing the substrate, and etching the auxiliary copper layer on the surface of the circuit copper layer to obtain the circuit board.
8. The method as claimed in claim 7, further comprising, after the step of laminating a dielectric layer on the copper layer to embed the copper layer, the steps of:
performing laser drilling on the dielectric layer;
plating thin copper on the surface of the dielectric layer and in the hole by using a flash plating process;
manufacturing an outer layer circuit copper layer on the surface of the thin copper layer by using a graph manufacturing process;
the step of removing the substrate and etching away the auxiliary copper layer on the surface of the circuit copper layer to obtain the circuit board comprises the following steps:
and removing the substrate, and etching away the auxiliary copper layer and the thin copper to obtain the circuit board.
9. The method of processing the embedded circuit package substrate as claimed in claim 1, wherein the step of providing a circuit board with embedded pads comprises:
providing a substrate;
electroplating auxiliary copper layers on the surfaces of two opposite sides of the substrate;
respectively manufacturing a first circuit copper layer and a second circuit copper layer on the surface of the auxiliary copper layer;
laminating a first dielectric layer and a second dielectric layer on the surfaces of the first circuit copper layer and the second circuit copper layer respectively;
drilling holes on the surfaces of the first dielectric layer and the second dielectric layer;
plating thin copper on the surface of the first dielectric layer, the surface of the second dielectric layer and the hole;
respectively manufacturing a first outer layer circuit copper layer and a second outer layer circuit copper layer on the surface of the thin copper by utilizing a graph manufacturing process;
carrying out plate separation treatment on the substrate to obtain two identical plates to be etched;
and etching the board to be etched to remove the auxiliary copper layer and the thin copper on the surface of the board to be etched, thereby obtaining the circuit board.
10. The embedded type circuit packaging substrate is characterized in that a bonding pad is embedded in the surface of one side of the embedded type circuit packaging substrate; the bonding pad is exposed on the surface of the embedded circuit packaging substrate, and the part of the bonding pad is not lower than the surface of the embedded circuit packaging substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210523894.7A CN115190701B (en) | 2022-05-13 | 2022-05-13 | Embedded circuit packaging substrate and processing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210523894.7A CN115190701B (en) | 2022-05-13 | 2022-05-13 | Embedded circuit packaging substrate and processing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115190701A true CN115190701A (en) | 2022-10-14 |
| CN115190701B CN115190701B (en) | 2023-06-02 |
Family
ID=83513286
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210523894.7A Active CN115190701B (en) | 2022-05-13 | 2022-05-13 | Embedded circuit packaging substrate and processing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115190701B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117320297A (en) * | 2023-10-23 | 2023-12-29 | 浙江晶引电子科技有限公司 | Preparation method of ultrathin flexible film packaging substrate combining photoetching and die cutting |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007165502A (en) * | 2005-12-13 | 2007-06-28 | Yamaichi Electronics Co Ltd | Element-incorporated circuit board and its manufacturing method |
| JP2008124339A (en) * | 2006-11-14 | 2008-05-29 | Shinko Electric Ind Co Ltd | Wiring substrate and manufacturing method therefor |
| CN101282622A (en) * | 2008-05-29 | 2008-10-08 | 日月光半导体制造股份有限公司 | Circuit board and method for manufacturing the same |
| US20140263168A1 (en) * | 2013-03-15 | 2014-09-18 | Unimicron Technology Corporation | Method for manufacturing package substrate |
| CN106998629A (en) * | 2016-01-25 | 2017-08-01 | 深南电路股份有限公司 | A kind of circuit board manufacturing method and circuit board |
| JP2018101776A (en) * | 2016-12-21 | 2018-06-28 | サムソン エレクトロ−メカニックス カンパニーリミテッド． | Printed circuit board and package |
-
2022
- 2022-05-13 CN CN202210523894.7A patent/CN115190701B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007165502A (en) * | 2005-12-13 | 2007-06-28 | Yamaichi Electronics Co Ltd | Element-incorporated circuit board and its manufacturing method |
| JP2008124339A (en) * | 2006-11-14 | 2008-05-29 | Shinko Electric Ind Co Ltd | Wiring substrate and manufacturing method therefor |
| CN101282622A (en) * | 2008-05-29 | 2008-10-08 | 日月光半导体制造股份有限公司 | Circuit board and method for manufacturing the same |
| US20140263168A1 (en) * | 2013-03-15 | 2014-09-18 | Unimicron Technology Corporation | Method for manufacturing package substrate |
| CN106998629A (en) * | 2016-01-25 | 2017-08-01 | 深南电路股份有限公司 | A kind of circuit board manufacturing method and circuit board |
| JP2018101776A (en) * | 2016-12-21 | 2018-06-28 | サムソン エレクトロ−メカニックス カンパニーリミテッド． | Printed circuit board and package |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117320297A (en) * | 2023-10-23 | 2023-12-29 | 浙江晶引电子科技有限公司 | Preparation method of ultrathin flexible film packaging substrate combining photoetching and die cutting |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115190701B (en) | 2023-06-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4607612B2 (en) | Wiring circuit board and manufacturing method thereof | |
| US7571540B2 (en) | Production method of suspension board with circuit | |
| KR100783340B1 (en) | Method for production of interposer for mounting semiconductor element | |
| JPH0758827B2 (en) | Method of manufacturing printed circuit | |
| EP1942711B1 (en) | Method of manufacturing a wiring board including electroplating | |
| US6977349B2 (en) | Method for manufacturing wiring circuit boards with bumps and method for forming bumps | |
| CN115190701B (en) | Embedded circuit packaging substrate and processing method thereof | |
| US8186043B2 (en) | Method of manufacturing a circuit board | |
| CN108024442B (en) | Wired circuit board and method for manufacturing the same | |
| CN102573289A (en) | Laminated printed circuit board module with conductive contact piece on side and manufacturing method thereof | |
| JP5539759B2 (en) | Printed circuit board manufacturing method | |
| JP3770895B2 (en) | Manufacturing method of wiring board using electrolytic plating | |
| CN115226301A (en) | Circuit board and manufacturing method thereof | |
| JPH10189805A (en) | Electronic component-mounting substrate and manufacture thereof | |
| JP2000091722A (en) | Printed wiring board and its manufacture | |
| KR20150083401A (en) | Method for manufacturing semiconductor package substrate and semiconductor package substrate manufactured using the same | |
| US11606862B2 (en) | Circuit board, method for manufacturing the same | |
| KR102671758B1 (en) | Printed circuit board and method thereof | |
| JP4566760B2 (en) | Method for manufacturing printed circuit board | |
| JP2004072027A (en) | Method of manufacturing wiring board with bump electrode | |
| CN118215213A (en) | Packaging substrate with conducting column and manufacturing method thereof | |
| JP2006013160A (en) | Wiring circuit substrate and semiconductor apparatus | |
| CN117042282A (en) | Metal substrate of thermoelectric separation boss and manufacturing method thereof | |
| JP2004281752A (en) | Single side circuit board and method for manufacturing it | |
| CN115988741A (en) | Circuit board and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |