JP6880432B2 - Multilayer printed circuit board - Google Patents

Description

The present invention relates to a printed circuit board.

Usually, a multilayer printed circuit board is produced by sequentially laminating a plurality of build-up layers on a core substrate. In this way, the build-up layers are sequentially laminated to produce a multilayer printed circuit board, which is called a sequential lamination method.

When a multilayer printed circuit board is manufactured by a sequential lamination method, the number of lamination steps increases as the number of layers of the multilayer printed circuit board increases. This laminating process also applies heat to the already laminated parts, which can cause unnecessary and unpredictable deformation. The more such deformations, the more difficult it is to align between layers.

For this reason, a batch lamination method has been developed in which each build-up layer is separately produced on a unit substrate, and then a plurality of unit substrates are laminated at the same time to produce a multilayer printed circuit board.

Korean Publication No. 10-2011-0066044

According to an embodiment of the present invention, a multilayer printed circuit board capable of preventing pressure variation during batch lamination is provided by including a buffer layer in the penetrating via.

It is a figure which shows the multilayer printed circuit board which concerns on one Example of this invention. It is a figure which shows schematic the cross section along the line AA' in FIG. It is a figure which shows one step in the manufacturing process of the metal unit substrate applied to the manufacturing method of the multilayer printed circuit board which concerns on one Example of this invention. It is a figure which shows the next process of FIG. It is a figure which shows the next process of FIG. It is a figure which shows the next process of FIG. It is a figure which shows the next process of FIG. It is a figure which shows the next process of FIG. It is a figure which shows the next process of FIG. It is a figure which shows one step in the manufacturing process of the general unit substrate applied to the manufacturing method of the multilayer printed circuit board which concerns on one Example of this invention. It is a figure which shows the next process of FIG. It is a figure which shows the next process of FIG. It is a figure which shows the next process of FIG. It is a figure which shows the next process of FIG. It is a figure which shows an example of laminating the metal unit substrate and the general unit substrate manufactured by the process of FIGS. 4 to 14 collectively. It is a figure which shows an example which laminated the metal unit substrate and the general unit substrate manufactured by the process of FIG. 4 to 14 collectively.

The terms used in the present application are used solely for the purpose of explaining a specific embodiment and do not limit the present invention. A singular expression includes multiple expressions unless explicitly expressed in a sentence. In the present application, terms such as "including" or "having" specify the existence of features, numbers, steps, actions, components, parts, or a combination thereof described in the specification. It must be understood that it does not preclude the existence or addability of one or more other features or numbers, steps, movements, components, parts, or combinations thereof.

Further, throughout the specification, "above" means that it is located above or below the target portion, and does not necessarily mean that it is located above or above the gravity direction.

Further, "bonding" does not mean only the case where each component is in direct physical contact with each other in the contact relationship between the components, and other components are interposed between the components. It is used as a concept that covers the cases where each component is in contact with other components.

The size and thickness of each configuration shown in the drawings are arbitrarily shown for convenience of explanation, and the present invention is not necessarily limited thereto.

Hereinafter, examples of the multilayer printed circuit board according to the present invention will be described in detail with reference to the accompanying drawings, and the same or corresponding components will be designated by the same drawing reference numerals in the description based on the attached drawings. The duplicate explanation about is omitted.

<Multilayer printed circuit board>
FIG. 1 is a diagram showing a multilayer printed circuit board according to an embodiment of the present invention, and FIG. 2 is a diagram schematically showing a cross section along a line AA'in FIG.

Referring to FIGS. 1 and 2, the multilayer printed circuit board 1000 according to the embodiment of the present invention has a plurality of conductor pattern layers 110, 210, 310, 410, 510, 610, a penetrating via TV, and a first connection. A via V1 may be included, and a second connecting via V2 and an internal via IV may be further included.

Each of the plurality of conductor pattern layers 110, 210, 310, 410, 510, and 610 is formed in an insulating portion so as to be separated from each other. Each of the plurality of conductor pattern layers 110, 210, 310, 410, 510, 610 can include at least one of a signal pattern, a power pattern, a ground pattern, or an external connection terminal.

Each of the plurality of conductor pattern layers 110, 210, 310, 410, 510, and 610 can be classified into an inner pattern layer and an outer pattern layer according to the position formed in the insulating portion. That is, a plurality of internal pattern layers can be formed and can be formed inside the insulating portion, and the first outer pattern layer and the second outer pattern layer formed on the outermost layer of the plurality of conductor pattern layers, respectively, , At least a part can be formed so as to be embedded in the upper surface and the lower surface of the insulating portion, respectively.

In the following, for convenience of explanation, the uppermost conductor pattern layer among the plurality of conductor pattern layers 110, 210, 310, 410, 510, and 610 is the first conductor pattern layer 110, and the lowermost conductor pattern layer 110, based on FIG. The layer is referred to as a second conductor pattern layer 210. Further, among the plurality of conductor pattern layers, the conductor pattern layers excluding the first conductor pattern layer 110 and the second conductor pattern layer 210 are moved from the upper part to the lower part of the insulating portion, respectively, with the third conductor pattern layer 310 and the fourth conductor pattern. It is referred to as a layer 410, a fifth conductor pattern layer 510, and a sixth conductor pattern layer 610. That is, the first conductor pattern layer 110 and the second conductor pattern layer 210 correspond to the first outer pattern layer and the second outer pattern layer described above, respectively, and the third conductor pattern layer to the sixth conductor pattern layers 310, 410, respectively. Each of 510 and 610 corresponds to each of the plurality of internal pattern layers described above.

The first conductor pattern layer 110 and the second conductor pattern layer 210 are conductor pattern layers formed in the outermost layers of the plurality of conductor pattern layers 110, 210, 310, 410, 510, and 610, and are described in the present embodiment. The rigidity of the multilayer printed circuit board 1000 can be reinforced. That is, the first conductor pattern layer 110 and the second conductor pattern layer 210 are substances that are relatively more rigid than the substances constituting the third conductor pattern layer to the sixth conductor pattern layers 310, 410, 510, and 610. Can include. Alternatively, the pattern formation area of each of the first conductor pattern layer 110 and the second conductor pattern layer 210 is larger than the pattern formation area of each of the third conductor pattern layer 310, 410, 510, and 610 from the third conductor pattern layer to the sixth conductor pattern layer 310. It can be formed, and the thickness of each of the first conductor pattern layer 110 and the second conductor pattern layer 210 is formed to be thicker than the thickness of each of the third conductor pattern layer to the sixth conductor pattern layer 310, 410, 510, 610. Can also be done.

The first conductor pattern layer 110 and the second conductor pattern layer 210 can include the rigid reinforcing layers 111 and 211, and the rigid reinforcing layers 111 and 211 can include Invar.

Since Invar is superior in rigidity to copper (Cu) used for forming a signal pattern or the like of a normal printed circuit board, it imparts rigidity to the multilayer printed circuit board 1000 according to the present embodiment and causes warpage. Can be suppressed.

The first conductor pattern layer 110 and the second conductor pattern layer 210 further include first metal layers 112 and 212 formed on the upper and lower portions of the rigid reinforcing layers 111 and 211, respectively, and second metal layers 113 and 213. be able to.

The first metal layers 112, 212 and the second metal layers 113, 213 can contain copper. When the first conductor pattern layer 110 and the second conductor pattern layer 210 are formed only by the rigid reinforcing layers 111 and 211 including the inverse, the bonding force with the refractory metal layer 30 described later may decrease. By forming copper layers on the upper and lower parts of the rigid reinforcing layers 111 and 211, respectively, the first conductor pattern layer 110 and the second conductor pattern layer 210 can be connected to an external connecting means such as a refractory metal layer 30 or a solder ball. The binding force can be improved.

The third conductor pattern layer to the sixth conductor pattern layer 310, 410, 510, 610 are copper (Cu), silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni) having excellent electrical characteristics. , Titanium (Ti), gold (Au), platinum (Pt) and the like.

The pattern shapes of the first conductor pattern layer to the sixth conductor pattern layer 110, 210, 310, 410, 510, and 610 may all be the same, or may be different from each other as required by design.

On the other hand, in FIG. 1 and the like, all of the first conductor pattern layer 110 and the second conductor pattern layer 210 have a three-layer structure, but this is only an example. As another example, the first conductor pattern layer 110 and the second conductor pattern layer 210 are formed in a two-layer structure including the rigid reinforcing layers 111 and 211 or a structure having four or more layers including the rigid reinforcing layers 111 and 211. Is also possible.

Further, in FIG. 1 and the like, the first conductor pattern layer 110 and the second conductor pattern layer 210 are shown to have a so-called CIC structure (copper-invar-copper), which is the first conductor pattern layer. It does not preclude the 110 and the second conductor pattern layer 210 from being formed in an ICI structure (invar-copper-invar).

Further, in FIG. 1 and the like, all of the first conductor pattern layer 110 and the second conductor pattern layer 210 are shown to include the rigidity reinforcing layers 111 and 211, respectively, but this is merely an example, and the first Rigidity reinforcing layers 111 and 211 may be formed on only one of the conductor pattern layer 110 and the second conductor pattern layer 210. As described above, the rigidity reinforcing layers 111 and 211 suppress the occurrence of warpage, and it is necessary to suppress the warpage of the first conductor pattern layer 110 and the second conductor pattern layer 210 in the manufacturing process. This is because the rigidity reinforcing layers 111 and 211 need only be formed in a certain portion.

Further, in FIG. 1 and the like, four internal pattern layers 310, 410, 510, and 610 are shown, but these are merely examples. That is, the numbers of the internal pattern layers 310, 410, 510, and 610 can be variously changed according to design needs and the like.

The insulating portion is formed by laminating a plurality of insulating layers 120, 220, 320, 420, 520, and 620. Each of the plurality of insulating layers 120, 220, 320, 420, 520, and 620 together with any one of the first conductor pattern layer to the sixth conductor pattern layer 110, 210, 310, 410, 510, 610. It is included in the general unit substrates 300, 400, 500, 600 or the metal unit substrates 100, 200, which will be described later. That is, according to the present invention in which the printed circuit board is manufactured by the batch lamination method, unlike the sequential lamination method, the plurality of insulating layers 120, 220, 320, 420, 520, and 620 are separated from each other and formed separately. Later, they are collectively laminated at the same time.

Each of the plurality of insulating layers 120, 220, 320, 420, 520, and 620 may be a photosensitive insulating layer containing a photocurable resin and made of a substance that reacts with light.

Each of the plurality of insulating layers 120, 220, 320, 420, 520, and 620 can embed the first conductor pattern layer to the sixth conductor pattern layer 110, 210, 310, 410, 510, and 610, respectively. For example, the first insulating layer 120 embeds the first conductor pattern layer 110 and constitutes the first metal unit substrate 100 together with the first conductor pattern layer 110.

Hereinafter, for convenience of explanation, only the first insulating layer 120 among the plurality of insulating layers 120, 220, 320, 420, 520, and 620 will be described. However, this description can be similarly applied to the sixth insulating layers 220, 320, 420, 520, and 620 from the second insulating layer excluding the first insulating layer 120.

When the first insulating layer is a photosensitive insulating layer, a photolithography step, that is, an exposure and development step can be performed without a separate photoresist. When holes are machined in the photosensitive insulating layer 120 by a photolithography process, it is more advantageous to realize finer holes than when holes are machined in a non-photosensitive insulating layer such as a prepreg using a laser. .. Further, in forming a plurality of holes, when a laser is used, a plurality of laser steps are required, but when the photolithography step is used, it can be realized by only one step, so that the step is simplified.

Further, when the photolithography process is used, it is possible to form a wider variety of hole shapes as compared with laser machining. For example, the vertical cross-sectional shape of the hole can be formed into an inverted trapezoid, a regular trapezoid, a rectangle, or the like.

The photosensitive insulating layer can be a positive type or a negative type.

In the case of a positive type photosensitive insulating layer, the polymer bond of the photopolymer in the exposed portion is broken. After that, when the developing step is performed, it receives light and the portion where the photopolymer polymer bond is broken is removed.

In the case of the negative type photosensitive insulating layer, the exposed portion undergoes a photopolymerization reaction to change from a single structure to a chain structure three-dimensional network structure, and when the developing step is performed, the portion that does not receive light is removed.

The first insulating layer 120 may be a photocurable resin containing an inorganic filler. The inorganic filler improves the rigidity of the first insulating layer 120. Inorganic fillers include silica (SiO ₂ ), alumina (Al ₂ O ₃ ), silicon carbide (SiC), barium sulfate (BaSO ₄ ), talc, clay, mica powder, aluminum hydroxide (AlOH ₃ ), magnesium hydroxide. (Mg _(OH) 2), calcium carbonate (CaCO _3), magnesium carbonate (MgCO _3), magnesium oxide (MgO), boron nitride (BN), aluminum borate (alBO _3), barium titanate (BaTiO ₃₎ and zircon At least one selected from the group composed of calcium acid (CaZrO _{3) can be used.}

On the other hand, the above description does not exclude the non-photosensitive first insulating layer 120. That is, unlike the above description, the first insulating layer can be a prepreg containing a thermosetting resin.

The first connecting via V1 connects the uppermost conductor pattern layer and another conductor pattern layer adjacent thereto. That is, the first connecting via V1 penetrates the third insulating layer 320, and both ends thereof are coupled to the first conductor pattern layer 110 and the third conductor pattern layer 310, respectively, and the first conductor pattern layer 110 and the third conductor pattern It is electrically connected to the layer 310.

The penetrating via TV connects the uppermost layer and the lowest layer of the plurality of conductor pattern layers 110, 210, 310, 410, 510, and 610 to each other. That is, both ends of the penetrating via TV are coupled to the first conductor pattern layer 110 and the second conductor pattern layer 210, respectively, and electrically connect the first conductor pattern layer 110 and the second conductor pattern layer 210.

Each of the first connecting via V1 and the penetrating via TV is located between the refractory metal layer 30 formed in each of the plurality of conductor pattern layers 110, 210, 310, 410, 510, and 610 and the refractory metal layer 30. It includes a buffer layer 40 that is interposed to disperse the pressure and has a melting point lower than the melting point of the refractory metal layer 30. That is, the first connecting via V1 has a refractory metal layer 30 formed on the first conductor pattern layer 110 and the third conductor pattern layer 310, respectively, and a buffer layer 40 interposed between the refractory metal layers 30. Including. Further, the penetrating via TV includes a refractory metal layer 30 formed in the first conductor pattern layer 110 and the second conductor pattern layer 210, respectively, and a buffer layer 40 interposed between the refractory metal layers 30.

The refractory metal layer 30 has excellent electrical properties and a melting point higher than that of the buffer layer 40. Copper (Cu), silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni). ), Titanium (Ti), gold (Au), platinum (Pt) and the like.

The buffer layer 40 has a melting point lower than the melting point of the refractory metal layer 30. Therefore, when a plurality of unit substrates 100, 200, 300, 400, 500, 600, which will be described later, are laminated together, at least a part of the buffer layer 40 is melted, whereby the plurality of unit substrates 100, 200 are melted. , 300, 400, 500, 600 pressure variations are eliminated. Further, the molten buffer layer 40 is easily intermetallic compound (Inter-Metallic Compound, IMC) with the refractory metal layer 30, the conductor pattern layer 110, 210, 310, 410, 510, 610, or the conductor filler 50 described later. Therefore, the bonding force between the refractory metal layer 30 or the conductor filler 50 and the buffer layer 40 is improved.

The buffer layer 40 can be made of a solder material. Here, "solder" means a metal material that can be used for soldering, and may be an alloy containing lead (Pb) or may not contain lead. For example, the solder may be an alloy of tin (Sn), silver (Ag), copper (Cu) or a metal selected from these. Specifically, the solder used in the examples of the present invention can be a tin, silver, or copper alloy having a tin (Sn) content of 90% or more with respect to the entire solder.

The penetrating via TV further includes a conductor filler 50 formed between the buffer layer 40 and the refractory metal layer 30, respectively. That is, the penetrating via TV is formed in a five-layer structure, and the refractory metal layer 30-conductor filler 50-buffer layer 40-conductor filler 50-melting point metal layer 30 is formed in this order from the upper part to the lower part of FIG. Can be

In the case of the conventional batch laminating method, the penetrating vias are formed by collectively laminating the vias formed on all of the respective unit substrates, but in the case of this embodiment, the first part TV'and the second penetrating vias of the penetrating vias are formed. The "partial TV" is formed only on the uppermost layer 100 and the lowermost layer 200 of the plurality of unit substrates 100, 200, 300, 400, 500, 600, respectively. That is, in this embodiment, the conductor filler 50 is used as the first portion. By forming the TV'and the second portion TV', the coupling portion can be minimized at the time of forming the penetrating via TV (combination of the first portion TV'and the second portion TV'). Then, when the batch stacking is performed, the location where the pressure variation occurs is reduced, and in this embodiment, since the first portion TV'and the second portion TV' include the buffer layer 40 described above, the penetrating via TV It is possible to eliminate the pressure variation that can occur during formation (combination of the first portion TV'and the second portion TV').

The conductor filler 50 has a melting point higher than the melting point of the buffer layer 40. The conductor filler 50 has excellent electrical properties and a melting point higher than that of the buffer layer 40. Copper (Cu), silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni), It can be formed of titanium (Ti), gold (Au), platinum (Pt) or the like.

Here, at least one of the conductor fillers 50 includes an internal hollow 51 extending from one end bonded to the refractory metal layer 30 to the other end bonded to the buffer layer 40, and the buffer layer 40 includes an internal hollow 51. Can be filled with at least a portion of.

FIG. 2 is a view showing a cross section taken along the line AA in FIG. 1, and as shown in FIG. 2, an internal hollow 51 is formed inside the conductor filler 50, and a part of the internal hollow 51 is formed. It can be filled with the buffer layer 40. The sum of the lengths of the first part TV'and the second part TV'of the penetrating via TV described above may be larger than the length of the designed penetrating via TV due to process error or the like. It may cause pressure variation during stacking.

In this embodiment, the inner hollow 51 is formed in the conductor filler 50, and at least a part of the unnecessary buffer layer can flow into the inner hollow 51. As a result, it is possible to eliminate the pressure variation during batch lamination that occurs due to process errors and the like. Further, in the case of this embodiment, since the buffer layer 40 fills at least a part of the inner hollow 51 of the conductor filler 50, the bonding force is improved as compared with the case where the buffer layer 40 and the conductor filler 50 are bonded face-to-face. To do.

On the other hand, in FIG. 2, the cross sections of the conductor filler 50 and the inner hollow 51 are shown as rectangles and circles, respectively, but this is only an example. That is, the cross section of the conductor filler 50 can be variously changed to a circular shape, an elliptical shape, a polygonal shape, or the like, and the cross section of the inner hollow 51 can also be changed to a polygonal shape, an elliptical shape, or the like.

Further, in FIG. 2, two internal hollows 51 are formed inside the conductor filler 50, and similarly, the number of internal hollows 51 formed inside the conductor filler 50 can be changed in various ways.

Each of the refractory metal layer 30 and the conductor filler 50 can contain copper (Cu). As an example, each of the refractory metal layer 30 and the conductor filler 50 can be formed by copper electroplating. In this case, since both are formed of the same substance, the binding force between them is improved. In addition, the process can be simplified and the cost can be reduced as compared with the case where both are formed of different substances.

The multilayer printed circuit board 1000 according to the present embodiment excludes the second connection via V2 for connecting the lowermost conductor pattern layer 210 to another conductor pattern layer 610 adjacent thereto, and the uppermost layer and the lowermost conductor pattern layer. It can further include an internal via IV that connects adjacent conductor pattern layers of the plurality of conductor pattern layers to each other. That is, the second connecting via V2 connects the second conductor pattern layer 210 formed in the lowermost layer and the sixth conductor pattern layer 610 adjacent to the second conductor pattern layer 210. The internal via IV is a plurality of internal pattern layers excluding the first conductor pattern layer 110 and the second conductor pattern layer 210, that is, among the third conductor pattern layer to the sixth conductor pattern layer 310, 410, 510, 610. Any one is connected to the other adjacent internal pattern layers 310, 410, 510, 610.

Here, each of the second connecting via V2 and the inner via IV includes the refractory metal layer 30 and the buffer layer 40, and the refractory metal layer 30 is formed in any one of the adjacent conductor pattern layers. A buffer layer 40 is formed on the other one of the adjacent conductor pattern layers and is bonded to the refractory metal layer 30. As an example, in the case of the internal via IV connecting the third conductor pattern layer 310 and the fourth conductor pattern layer 410, the refractory metal layer 30 is formed in the fourth conductor pattern layer 410, and the buffer layer 40 is the third conductor pattern layer 410. It is formed on the conductor pattern layer 410.

The refractory metal layer 30 and the buffer layer 40 will be omitted because they have been described above.

<Manufacturing method of multilayer printed circuit board>
3 to 16 are diagrams sequentially showing a method for manufacturing a multilayer printed circuit board according to an embodiment of the present invention.

Specifically, FIGS. 3 to 9 are diagrams sequentially showing a manufacturing process of a metal unit substrate applied to the method for manufacturing a multilayer printed circuit board according to an embodiment of the present invention, and FIGS. 10 to 14 are the present invention. It is a figure which sequentially shows the manufacturing process of the general unit board applied to the manufacturing method of the multilayer printed circuit board which concerns on one Example of the invention, and FIGS. It is a figure which shows that the general unit substrate is laminated together.

Hereinafter, the manufacturing process of the metal unit substrate and the manufacturing process of the general unit substrate will be sequentially described, and then the process of laminating a plurality of unit substrates will be described.

Unless it is necessary to distinguish between a metal unit substrate and a general unit substrate, it is commonly referred to as a unit substrate.

(Manufacturing method of metal unit substrate)
3 to 9 are diagrams sequentially showing a manufacturing process of a metal unit substrate applied to the method for manufacturing a multilayer printed circuit board according to an embodiment of the present invention.

First, referring to FIG. 3, the first original plate is laminated on the first carrier C1. The first original plate is a raw material that becomes the first conductor pattern layer 110 described above by the process described later. As described above, since the first conductor pattern layer 110 includes the first metal layer 112, the rigid reinforcing layer 111, and the second metal layer 113, the first original plate corresponds to the first metal plate 112. ', Rigidity reinforcing plate 111' and second metal plate 113' are included.

A release layer can be formed between the first carrier C1 and the first original plate. Further, metal plates are formed on both sides of the first carrier C1, and the first original plate can be formed on the metal plates.

Next, referring to FIG. 4, at least a part of the first original plate is removed to form the first conductor pattern layer 110. The first conductor pattern layer 110 can be formed by forming a patterned etching resist corresponding to the first conductor pattern layer 110 on the first original plate and then etching. The patterned etching resist can be formed by forming an etching resist on the entire upper surface of the first original plate and then by photolithography.

On the other hand, in the above, it has been described that at least a part of the first original plate is removed to form the first conductor pattern layer 110, but this has been described based on the so-called subtrackive method during the normal pattern forming process. It is clear that the first conductor pattern layer 110 can be formed by using other pattern forming steps. As an example, the first conductor pattern layer 110 can be formed by forming metal foils on both sides of the first carrier C1 and using the MSAP (Modified Semi-Adaptive Process) method in which the metal foils are used as seed layers. That is, unlike FIGS. 3 and 4, the first conductor pattern layer 110 can be formed on the first carrier C1 by selective plating.

Next, referring to FIG. 5, the first insulating layer 120 is formed so that at least a part of the first conductor pattern layer 110 is embedded, and an opening is formed in the first insulating layer 120. The first insulating layer 120 is a photosensitive insulating layer, and the openings of the first insulating layer 120 can be formed by a photolithography step. Alternatively, the openings can be formed by laser drilling. The above-mentioned refractory metal layer 30 is formed in the opening by a step described later.

The first insulating layer 120 can be laminated on the first carrier C1 using a vacuum laminator. However, since the first insulating layer 120 that has been laminated and has undergone the selective exposure step does not undergo the post-curing step, it is in a semi-cured state (B-stage) until before the batch laminating step. As an example, the first insulating layer 120 that has undergone the selective exposure step can have a degree of curing of 10 to 20% as compared with the fully cured state (C-stage). On the other hand, if necessary, the first insulating layer 120 can be semi-cured by another step so as to have a degree of curing of 50% as compared with the fully cured state (C-stage). Another semi-curing step can be performed using UV light used in the photolithography step to form the aperture. However, even in this case, the first insulating layer 120 is not completely cured until before the batch laminating process.

After that, referring to FIG. 6, the refractory metal layer 30 is formed in the opening of the first insulating layer 120. The refractory metal layer 30 is commonly formed on the first portion TV'of the penetrating vias, the second portion TV'of the penetrating vias, the first connecting via V1 and the second connecting via V2 of the metal unit substrates 100 and 200. By this step, the refractory metal layer 30 of the first portion TV'of the penetrating via, the refractory metal layer 30 of the first connecting via V1 and the refractory metal layer 30 of the second connecting via V2 are formed at the same time.

The refractory metal layer 30 is formed by electrolytic plating. In the case of electrolytic plating, all anisotropic or isotropic plating is included. The refractory metal layer 30 is formed by copper electrolytic plating and can contain copper (Cu). In forming the refractory metal layer 30 by electroplating, the seed layer can be the second metal layer 113 of the first conductor pattern layer 110. Alternatively, the seed layer may be formed by another step instead of the second metal layer 113. As an example of the latter, after the first conductor pattern layer 110 is formed, a seed layer can be further formed along the surface of the first conductor pattern layer 110, and the first insulating layer 120 can be formed on the seed layer.

Then, referring to FIG. 7, the conductor filler 50 is formed on at least a part of the refractory metal layer 30. That is, the conductor filler 50 is formed only on the refractory metal layer 30 which is the first portion TV'of the penetrating via among the plurality of refractory metal layers 30.

The conductor filler 50 can be formed by electrolytic plating. In this case, in order to form the conductor filler 50, a patterned plating resist is formed on the refractory metal layer 30 and the first insulating layer 120, and the patterned plating resist is removed after the formation of the conductor filler 50. .. The plating resist can be a dry film. The conductor filler 50 can be formed by copper electroplating and contain copper (Cu) in the same manner as the refractory metal layer 30 described above.

On the other hand, although not clearly shown in FIG. 7, the above-mentioned internal hollow 51 can be formed inside the conductor filler 50. The inner hollow 51 can be formed by forming a plating resist at a position corresponding to the inner hollow 51 on the upper surface of the refractory metal layer 30, forming a conductor filler 50 by plating, and then removing the plating resist.

Next, referring to FIG. 8, the buffer layer 40 is formed on the conductor filler 50 and the refractory metal layer 30 on which the conductor filler is not formed. The buffer layer 40 is formed by selectively plating an i) low melting point metal, for example, a low melting point metal such as solder, or ii) selectively applying a low melting point metal paste such as solder paste and then applying the low melting point metal paste. Can be formed by drying.

The solder or solder paste can be mainly composed of an alloy of tin, silver, copper or a metal selected from these. Further, the solder paste used in the present invention does not have to contain flux.

The solder paste has a sintered type that hardens at a relatively high temperature (ex. 800 ° C.) and a cured type that hardens at a relatively low temperature (ex. 200 ° C.). The solder paste used in this embodiment can be a curing type that hardens at a relatively low temperature in order to prevent the first insulating layer 120 from being completely cured when the solder paste is cured.

The low melting point metal paste may have a relatively high viscosity and can maintain its shape after being formed on the high melting point metal layer 30 or the conductor filler 50. Further, the low melting point metal paste has low melting point metal particles, and the surface of the buffer layer 40 formed by solidifying the low melting point metal paste by these particles can have an uneven shape.

Next, referring to FIG. 9, the first metal unit substrate 100 can be manufactured by removing the first carrier C1 from the first insulating layer 120. At this time, in order to easily remove the first carrier C1 and support the first metal unit substrate 100 until the batch stacking, the first surface facing the first insulating layer 120 bonded to the first carrier C1. A support layer can be laminated on the other surface of the insulating layer 120. By supporting the first metal unit substrate 100 until the batch lamination, this support layer prevents the first metal unit substrate 100 from being deformed, and the first metal unit substrate 100 can be easily handled until the subsequent steps. .. The support layer can be laminated on the other surface of the first insulating layer 120 in the form of a film. Further, a non-adhesive region can be selectively formed on the support layer so that it can be easily removed from the first metal unit substrate 100 at the time of batch lamination.

On the other hand, in FIGS. 3 to 9, the first metal unit substrate 100 is formed on both sides of the first carrier C1, but the first metal unit substrate 100 may be formed only on one surface of the first carrier C1. it can. Further, the first metal unit substrate 100 can be formed on one surface of the first carrier C1, and the second metal unit substrate 200 can be formed on the other surface of the first carrier C1.

In the above, the first metal unit substrate 100 has been described, but since the same description applies to the second metal unit substrate 200, the description of the second metal unit substrate 200 will be omitted.

(Manufacturing method of general unit substrate)
10 to 14 are views showing sequentially the manufacturing process of a general unit substrate applied to the method for manufacturing a multilayer printed circuit board according to an embodiment of the present invention.

First, referring to FIG. 10, the second original plate is laminated on the second carrier C2. The second original plate is a raw material that becomes the third conductor pattern layer 310 described above by the process described later. The second master plate can be a copper overnight. The copper anchor can be laminated on the second carrier C2 in the form of a film, and can also be formed on the second carrier C2 by electroless plating and electrolytic plating. The second carrier C2 includes a first metal foil F1 and a second metal foil F2 formed on both sides of a base (B) and a base (B) that impart rigidity to the second carrier C2, respectively. In this embodiment, since the copper anchor, which is the second original plate, is selectively etched to form the third conductor pattern layer 310, the first metal leaf F1 and the second metal leaf F2 do not react with the copper etching solution. It can be made of metal. As an example, the first metal leaf F1 and the second metal leaf F2 can contain nickel (Ni).

Next, referring to FIG. 11, at least a part of the second original plate is selectively removed to form the third conductor pattern layer 310. At this time, a patterned etching resist corresponding to the third conductor pattern layer 310 is formed on the second original plate, and then etching is performed to remove the patterned etching resist, thereby forming the patterned etching resist on the second carrier C2. The third conductor pattern layer 310 can be formed.

On the other hand, in the above, it has been explained that the third conductor pattern layer 310 is formed by the subtrackive method, but unlike this, the third conductor pattern layer 310 is modified semi-additive. It can also be formed using a method, a semi-additive method, or a full-additive method.

Next, referring to FIG. 12, after forming the third insulating layer 320 on the third conductor pattern layer 310 and the second carrier C2, an opening for opening at least a part of the third conductor pattern layer 310 is formed. .. Since the third insulating layer 320 is a photosensitive insulating layer, the openings can be formed by a photolithography step. The opening can also be formed by laser drilling. The third insulating layer 320 maintains a semi-cured state until before the batch laminating step, similarly to the first insulating layer 120 described above. Since the opening is a region where the refractory metal layer 30 and the buffer layer 40 on the lower side of the first connecting via V1 described above are formed, the first connecting via V1 of the third conductor pattern layer 310 is formed. Only the area can be opened.

Next, referring to FIG. 13, a refractory metal layer 30 and a buffer layer 40 are formed in the openings. The refractory metal layer 30 can be formed by forming a patterned plating resist on the third insulating layer 320 in which the openings are formed, and then plating. The buffer layer 40 can be formed by plating a low melting point metal or applying a low melting point metal paste and drying it.

On the other hand, the refractory metal layer 30 and the buffer layer 40 of the general unit substrates 300, 400, 500 and 600 can be formed by the same method as the refractory metal layer 30 and the buffer layer 40 of the metal unit substrates 100 and 200 described above. , Detailed description is omitted.

Next, referring to FIG. 14, the first general unit substrate 300 can be manufactured by removing the second carrier C2 from the third insulating layer 320. At this time, in order to easily remove the second carrier C2 and support the first general unit substrate 300 until the batch stacking, the second carrier C2 faces one surface of the third insulating layer 320 bonded to the second carrier C2. A support layer can be laminated on the other surface of the third insulating layer 320. Since this support layer has been described above, the description thereof will be omitted.

On the other hand, in FIGS. 10 to 14, the first general unit substrate 300 is formed on both sides of the second carrier C2, but the first general unit substrate 300 is formed only on one surface of the second carrier C2. You can also do it. Further, the first general unit substrate 300 can be formed on one surface of the second carrier C2, and the second general unit substrate 400 can be formed on the other surface of the second carrier C2.

Although the first general unit substrate 300 has been described above, the same description applies to the second general unit substrate 400, the third general unit substrate 500, and the fourth general unit substrate 600. Detailed description of these will be omitted.

<Step of batch stacking unit boards>
15 and 16 are views showing that the metal unit substrate and the general unit substrate manufactured according to FIGS. 4 to 14 are laminated together.

Referring to FIG. 15, a plurality of unit substrates 100, 200, 300, 400, 500, 600 are arranged one above the other, and these are laminated together.

At this time, the alignment marks formed on the plurality of unit substrates 100, 200, 300, 400, 500, and 600 are used to align the plurality of unit substrates 100, 200, 300, 400, 500, and 600. , V-press laminating machine or the like is used for high temperature pressure bonding to join all the layers at once.

The temperature can be set to 180 to 200 ° C. and the press pressure can be set to 30 to 50 kg / cm2 at the time of batch lamination, but the temperature and pressure at the time of batch lamination are not limited to this, and are the first to sixth. It can be set differently depending on the components of the insulating layers 120, 220, 320, 420, 520, 620, the components of the buffer layer 40, and the like. In particular, the temperature at the time of batch lamination is preferably equal to or higher than the melting point of the buffer layer 40.

At the time of batch lamination, the buffer layer 40 can be joined to the adjacent conductor pattern layers 110, 210, 310, 410, 510, 610 or the conductor filler 50 while being melted. In this case, the upper cross-sectional area of the buffer layer 40 and the lower cross-sectional area of the buffer layer 40 may have different sizes due to the spread of the buffer layer 40 after the batch lamination.

Further, the first to sixth insulating layers 120, 220, 320, 420, 520, and 620, which were in the semi-cured state, are fully cured after being laminated together.

Next, referring to FIG. 16, a solder resist layer SR is formed on each of the first conductor pattern layer 110 and the second conductor pattern layer 210. The solder resist layer SR forms a solder resist on the entire surfaces of the first conductor pattern layer 110 and the second conductor pattern layer 210, and then a part of each of the first conductor pattern layer 110 and the second conductor pattern layer 210. Can be formed open. Alternatively, in order to open a part of each of the first conductor pattern layer 110 and the second conductor pattern layer 210, a patterned solder resist layer SR is applied to each of the first conductor pattern layer 110 and the second conductor pattern layer 210, respectively. It can also be laminated.

On the other hand, in FIGS. 15 and 16, the solder resist layer SR is formed after the batch laminating step, but the solder resist layer SR is a plurality of unit substrates 100, 200, 300, 400, in the batch laminating step. It can also be formed with 500, 600. Further, unlike FIG. 16, the solder resist layer SR may be formed on only one of the first conductor pattern layer 110 and the second conductor pattern layer 210.

Although one embodiment of the present invention has been described above, if a person having ordinary knowledge in the technical field is to add components within the scope of the invention described in the claims. The present invention can be variously modified and changed by modification or deletion, and it can be said that this is also included in the scope of the present invention.

C1 1st carrier C2 2nd carrier B Base F1 1st metal foil F2 2nd metal foil TV Penetration via TV'Penetration via 1st part TV "Penetration via 2nd part V1 1st connection via V2 2nd connection via IV Internal Via SR Solder Resist Tung 30 Refractory Metal Layer 40 Buffer Layer 50 Conductor Filler 51 Internal Hollow 100 First Metal Unit Substrate 200 Second Metal Unit Substrate 300 First General Unit Substrate 400 Second General Unit Substrate 500 Third General unit substrate 600 Fourth general unit substrate 110, 210, 310, 410, 510, 610 Conductor pattern layer 120, 220, 320, 420, 520, 620 Insulation layer 111, 211 Rigid reinforcement layer 111'Rigid reinforcement plate 112, 212 First metal layer 112'First metal plate 113, 213 Second metal layer 113' Second metal plate 1000 Multilayer printed circuit board

Claims (9)

With multiple conductor pattern layers,
A penetrating via that connects the uppermost layer and the lowermost layer of the plurality of conductor pattern layers to each other,
Includes a first connecting via that connects the topmost conductor pattern layer to the other conductor pattern layer adjacent thereto.
Each of the penetrating via and the first connecting via
The refractory metal layer formed in each of the conductor pattern layers and
It comprises a buffer layer interposed between the refractory metal layers and having a melting point lower than the melting point of the refractory metal layer.
The penetrating via is
Further seen including a conductor filler, each of which is formed between each of the refractory metal layer and the buffer layer,
The conductor filler has a melting point higher than the melting point of the buffer layer.
At least one of the conductor fillers is a multilayer printed circuit board containing an internal hollow formed inside the conductor filler. The buffer layer is a multilayer printed circuit board according to claim 1 comprising a tin (Sn). The multilayer printed circuit board according to claim 1 or 2 , wherein each of the refractory metal layer and the conductor filler contains copper (Cu). The top layer and / or the bottom layer of the conductor pattern layer is
The multilayer printed circuit board according to any one of claims 1 to 3 , which includes a rigid reinforcing layer. The multilayer printed circuit board according to claim 4 , wherein the rigidity reinforcing layer includes an Invar. A second connecting via connecting the lowermost conductor pattern layer and the other conductor pattern layer adjacent thereto,
The plurality of conductor pattern layers excluding the uppermost and lowermost conductor pattern layers further include an internal via that connects adjacent conductor pattern layers to each other.
Each of the second connecting via and the internal via
The melting point metal layer and the buffer layer are included.
The refractory metal layer is formed on any one of the adjacent conductor pattern layers.
The multilayer printed circuit board according to any one of claims 1 to 5 , wherein the buffer layer is bonded to the other one of the adjacent conductor pattern layers and is bonded to the refractory metal layer. The internal hollow is extended from one end of the conductor filler in which the conductor filler is bonded to the refractory metal layer to the other end of the conductor filler in which the conductor filler is bonded to the buffer layer.
The multilayer printed circuit board according to any one of claims 1 to 6, wherein the buffer layer fills at least a part of the internal hollow. Multiple internal pattern layers formed inside the insulation,
A first external pattern layer and a second external pattern layer, at least partially embedded in the upper surface and the lower surface of the insulating portion, respectively.
Includes a penetrating via that penetrates the insulating portion to connect the first external pattern layer and the second external pattern layer to each other.
The penetrating via is
A buffer layer that disperses pressure and
A conductor filler formed in the upper part and the lower part of the buffer layer, bonded to the buffer layer, and having an internal hollow formed inside, respectively.
Formed in each of the second outer patterned layer and the first outer pattern layer, the binding to the conductor filler, seen including and a refractory metal layer having a higher melting point than the melting point of the buffer layer, the conductor The filler is a multilayer printed circuit board having a melting point higher than the melting point of the buffer layer. The multilayer printed circuit board according to claim 8 , wherein the insulating portion contains a photocurable resin.

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