TW202045752A - Method for forming a copper layer on a circuit board and a circuit board having a sputtered copper layer - Google Patents
Method for forming a copper layer on a circuit board and a circuit board having a sputtered copper layer Download PDFInfo
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- TW202045752A TW202045752A TW108120695A TW108120695A TW202045752A TW 202045752 A TW202045752 A TW 202045752A TW 108120695 A TW108120695 A TW 108120695A TW 108120695 A TW108120695 A TW 108120695A TW 202045752 A TW202045752 A TW 202045752A
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Abstract
Description
本發明是關於一種電路板技術,特別是關於一種電路板銅層的製程及其結構。The invention relates to a circuit board technology, in particular to a manufacturing process and structure of a circuit board copper layer.
現有電路板的製程中,普遍需要通過化學鍍或電鍍的方式在基板上形成銅層,所形成的銅層後續可進一步製成圖形化電路。與電鍍相較,化學鍍有其優點在於,通過適當的表面處理之後,即可在非導體表面鍍上一層薄銅,這樣的特性使得電路設置的自由度大幅提昇,而被廣泛地運用在電路板製程中。In the existing circuit board manufacturing process, it is generally necessary to form a copper layer on the substrate by means of electroless plating or electroplating, and the formed copper layer can be further made into a patterned circuit later. Compared with electroplating, electroless plating has its advantage in that after proper surface treatment, a thin layer of copper can be plated on the surface of non-conductors. This feature greatly increases the freedom of circuit setting and is widely used in circuits. The board is in process.
但是,化學鍍銅也有其缺點在於,其鍍液組成較為複雜,工藝難度較高,連帶地導致化學鍍銅的成本也較高。However, electroless copper plating also has its disadvantages in that the composition of the plating solution is more complicated, the process is more difficult, and the cost of electroless copper plating is also higher.
有鑑於此,本發明之主要目的在於提供另一種可在電路板上形成銅層的替代性方法及結構。In view of this, the main purpose of the present invention is to provide another alternative method and structure for forming a copper layer on a circuit board.
為了達成上述及其他目的,本發明提供一種在電路板上形成銅層的方法,其包括:In order to achieve the above and other objectives, the present invention provides a method for forming a copper layer on a circuit board, which includes:
提供一電路板結構,該電路板結構具有一待鍍面,該待鍍面具有導電區及非導電區;以及Providing a circuit board structure having a surface to be plated, the surface to be plated having conductive areas and non-conductive areas; and
對該待鍍面進行濺鍍處理,在該待鍍面的導電區及非導電區形成一濺鍍銅層。Sputtering is performed on the surface to be plated, and a sputtered copper layer is formed on the conductive area and the non-conductive area of the surface to be plated.
為了達成上述及其他目的,本發明提供一種具有濺鍍銅層的電路板,其包括一電路板結構及一濺鍍銅層,電路板結構具有一待鍍面,待鍍面具有導電區及非導電區,濺鍍銅層則形成於待鍍面的導電區及非導電區。In order to achieve the above and other objectives, the present invention provides a circuit board with a sputtered copper layer, which includes a circuit board structure and a sputtered copper layer. The circuit board structure has a surface to be plated, and the surface to be plated has a conductive area and a non-conductive area. In the conductive area, the sputtered copper layer is formed in the conductive area and the non-conductive area of the surface to be plated.
通過上述技術,本發明可以用物理方式使銅離子沈積在待鍍面,且銅離子的繞射性能好,能夠濺鍍形狀複雜的待鍍面,從而在待鍍面的導電區及非導電區均形成銅層,能夠取代習用電路板製程中的化學鍍製程,減少鍍液的使用,並有機會降低成本。Through the above technology, the present invention can physically deposit copper ions on the surface to be plated, and the diffraction performance of copper ions is good, and can sputter the surface to be plated with complex shapes, so that the conductive and non-conductive areas of the surface to be plated can be sputtered. The copper layer is formed, which can replace the electroless plating process in the conventional circuit board manufacturing process, reduce the use of plating solution, and have the opportunity to reduce costs.
本發明揭示一種在電路板上形成銅層的方法及一種具有濺鍍銅層的電路板,該方法廣泛地相容於現有電路板製程中的銅層設置製程,特別是能夠取代化學鍍銅的製程。The present invention discloses a method for forming a copper layer on a circuit board and a circuit board with a sputtered copper layer. The method is widely compatible with the copper layer setting process in the existing circuit board manufacturing process, and is particularly capable of replacing electroless copper plating Process.
以下通過第1至7圖說明本發明其中一實施例的製程。Hereinafter, the manufacturing process of one embodiment of the present invention will be described with reference to FIGS. 1-7.
請參考第1圖,首先,提供一電路板結構1,該電路板結構1具有一待鍍面11,待鍍面11具有導電區111及非導電區112,導電區及非導電區112的數量視電路設計而定,在電路設計複雜度高的電路板結構中,待鍍面11可能具有為數眾多的導電區111及非導電區112。可以理解地是,當電路板結構的電路複雜度越高,待鍍面的表面通常也越粗糙,導電區及非導電區的高度也未必相同。所述導電區111例如為電路板結構中已先預製有部分電路的下層電路層,例如銅下層電路銅層。所述非導電區112例如是電路板結構中的介電質層、防焊層或封裝膠,例如聚醯亞胺、環氧樹脂或其他電路板結構常用的樹脂。本實施例所例示的電路板結構為單面、單層板,在其他可能的實施方式中,適用的電路板結構也可為雙面板或多層板。Please refer to Figure 1. First, a
請參考第2圖,對待鍍面11進行濺鍍處理,從而在待鍍面11的導電區111及非導電區112形成一濺鍍銅層20,所述濺鍍處理是利用物理氣相沈積原理,在真空條件下,利用低氣壓、大電流的電弧放電技術,通過氣體放電使銅靶材中的銅原子被電漿體轟擊而離開銅靶材,利用電子的加速作用,使被濺出的銅原子沈積在待鍍面11上,由於被濺出的銅原子具有良好的繞射能力,因此能夠在待鍍面11的不規則表面上均沈積一層薄銅,從而使導電區111及非導電區112均能形成濺鍍銅層20。Please refer to Figure 2 to perform a sputtering process on the
請參考第3圖,對濺鍍銅層20進行電鍍處理,在濺鍍銅層20上形成電鍍銅層30,所述電鍍處理是利用電解的原理在濺鍍銅層20上補上一層銅,以增加整體銅層的厚度。Please refer to Figure 3, the
接著,可進一步對濺鍍銅層20及電鍍銅層30進行圖形化處理,成為圖形化電路。所述圖形化處理例示性地以第4至7圖表示。Then, the
首先,請參考第4圖,將一光阻層40形成於電鍍銅層30上,並對光阻層40選擇性照射、曝光。First, referring to FIG. 4, a
接著,如第5圖所示,以顯影液將局部光阻層40選擇性移除,裸露底下的電鍍銅層30。Next, as shown in FIG. 5, the partial
再接著,如第6圖所示,以蝕刻液將裸露的電鍍銅層30及其底下的濺鍍銅層20選擇性移除,使濺鍍銅層20及電鍍銅層30被圖形化。Then, as shown in FIG. 6, the exposed copper
最後,如第7圖所示,移除光阻層,所製得的電路板即包括電路板結構1以及圖形化的濺鍍銅層20與電鍍銅層30,最終,濺鍍銅層20形成於電路板結構1待鍍面11上的導電區111與非導電區112的局部表面,電鍍銅層30則覆蓋於濺鍍銅層20上。根據所需的電路設計,還可以進一步在第7圖所示的電路板繼續增層、進行防焊處理、表面處理及/或其他電路板製程中常規的後處理。Finally, as shown in Figure 7, the photoresist layer is removed, and the resulting circuit board includes the
通過上述技術,本發明可以用物理方式使銅離子沈積在待鍍面,且銅離子的繞射性能好,能夠濺鍍形狀複雜的待鍍面,從而在待鍍面的導電區及非導電區均形成銅層,能夠取代習用電路板製程中的化學鍍製程,減少鍍液的使用,並有機會降低成本。Through the above technology, the present invention can physically deposit copper ions on the surface to be plated, and the diffraction performance of copper ions is good, and can sputter the surface to be plated with complex shapes, so that the conductive and non-conductive areas of the surface to be plated can be sputtered. The copper layer is formed, which can replace the electroless plating process in the conventional circuit board manufacturing process, reduce the use of plating solution, and have the opportunity to reduce costs.
1:電路板結構 11:待鍍面 111:導電區 112:非導電區 20:濺鍍銅層 30:電鍍銅層 40:光阻層 1: Circuit board structure 11: to be plated 111: conductive area 112: Non-conductive area 20: Sputtered copper layer 30: Electroplated copper layer 40: photoresist layer
第1至7圖為本發明其中一實施例的製程示意圖。Figures 1-7 are schematic diagrams of the manufacturing process of one embodiment of the present invention.
1:電路板結構 1: Circuit board structure
11:待鍍面 11: to be plated
111:導電區 111: conductive area
112:非導電區 112: Non-conductive area
20:濺鍍銅層 20: Sputtered copper layer
30:電鍍銅層 30: Electroplated copper layer
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