1280827 九、發明說明： 【發明所屬之技術領域】 本發明係關於雙面電路基板之製造方法，特別是關於 藉由有底導通孔來形成雙面導通之雙面電路基板之製造方 法。 【先前技術】 習知之藉由有底導通孔來形成雙面導通之雙面電路基 板之製造方法，例如圖5之⑴〜(5)所示的方法，首先如圖 5⑴所示，準備出在絕緣基材31雙面分別具有導電性金屬 層32、33之金屬面積層板。 接著，如圖5(2)所示，對一導電性金屬I 33、絕緣基 材32施以處理，以另一導電性金屬層32之絕緣基材31 側面露出的方式來形成導通用孔34。然後，如圖5(3)所示， 除去形成導通用孔34時的殘渣。 “然後，如圖5⑷所示，以電錄法來職予導電性物質， 藉此形成供導通雙面的導電性金屬層Μ、” <導電 屬層36 。 、 最後’如圖5(5)所示，藉由一連串的光微影方法(包含 形成光阻層、露光、顯影、蚀刻、剝離除去光阻層等，未 ®示出）來形成電路配線圖案’如此製造出雙面電路美板 上述習知之製造方法，如圖6所示，因上述圖；步 驟中導電性物質3 5之賦予處理不足，會產生電鍍物析出 不良部位37’其乃雙面的導電性金屬層32、3 通不良的原因。 守 1280827 又’如圖5(4)所示，在導通用孔 電性金屬層36厚声< & # _ $ ^ 底。卩周緣部，導 變差的原因。拎卩主丄 其乃導通可靠性 艾至的原U &時，為確保雙 夕邋補宵蚩认 彳等冤性金屬層32、33 間之導通可罪性，必須將導電性金屬 導電性全屬；^ S厚’但由於 生4屬層36也會覆蓋住電路 32、33，故如FI 7 /成邛之導電性金屬層 ^ 形成步驟之蝕刻來作成 电路之導電性金屬層變厚，如此 配線圖t。 冑以开/“密度的電路 為了改善該問題，專利文獻 填有底導通孔内部的方法。 ““出以電錢物充 然而，習知之以電鑛物充填有底導通孔内部的方法， 因有底導通孔之配置密度不@，各孔單位之電流密度會依 孔位置而改變，如圖8所示，在導通用孔34稀疏的區域％ 其充填m-方面，在導通用孔34密集的區域39其 充填度低’基於如此般之電鑛物析出速度差，冑電鑛物析 出速度快者接觸導電性金制33時，電鍍㈣t急㈣ 加’而在該導電性金屬層33電鍍形成出導電性金屬4〇(用 來充填導通用1 34者），如此會抑制其他有底導通孔内之 電鍍物析出’而將難以防止析出速度變得極慢。如此般， 依然存在著因導電性物質賦予處理不^所造成之雙面導電 性金屬層間之導通不良問題。 又，如專利文獻4所示，以電鍍物充填有底導通孔内 部後不除去抗鍍被膜的方式，針對元件構裝電路配線部之 最終表面電鍍處理，若事先使抗鍍層形成開口，當電鍍物 6 Ϊ280827 充填於有底導通孔内部時，將難以抑制電路配線上無用電 錢物之析出。 〔專利文獻1〕曰本特開2002 - 151623號公報 〔專利文獻2〕日本特開2〇〇2 - 232135號公報 〔專利文獻3〕曰本特開2003 - 273170號公報 〔專利文獻4〕曰本特開平10 — 209593號公報 【發明内容】 本發明之目的係為了解決以下兩大課題。其一為，為 了改善電路基板（藉由有底導通孔來形成雙面電路的導電路） 之電鍍物析出不良所產生之導通不良，習知採用之厚電鍍 法所造成之難以形成微細電路之問題。其二為，針對採用 導電性金屬之電鍍處理來充填導通用孔的方法時所產生之 問題’亦即在導通用孔之配置稀疏區、配置密集區其導通 孔充填用電鍍被膜之電鐘速度不同，起因於此會造成導通 不良的問題。 為了解決上述課題，本發明提供之電路基板之製造方 法，係具備以下步驟： 準備出雙面型金屬面積層板，該積層板，係在絕緣基 材之一面上，具有第一導電性金屬層（對形成有底導通孔後 的蝕刻，其具有不被貫穿的厚度），並在絕緣基材之另一面 上’具有弟一導電性金屬層（其厚度比第一導電性金屬層 薄）；在該第二導電性金屬層上形成光阻被膜； 將光阻被膜、導電性金屬層、絕緣基材從第二導電性 金屬層側施以處理，以第一導電性金屬層之絕緣基材側面 7 1280827 露出的方式來形成導通用孔； 攸導通用孔開口側，對具有開口之第二導電性金屬層 實施蝕刻處理，使該導電性金屬層之開口擴大； 使用電鍍法，以該導通用孔底部之該第一導電性金屬 層為陰極對忒導通用孔實施導電性金屬之電鍍充填（在不 和具有開Π之第二導電性金屬層形成電氣連接的範圍）； 、剝離除去光阻被膜後，在導通用孔開口側的面上賦予 導電性物質； 對賦予導電性物質後之第二導電性金屬層面侧以電鍍 來形成導電性金屬層； 、皆由第_ ‘電性金屬層、導電性物質層、電鍍形成的 導電：金屬層所構成之開口側導電性金屬I、以及第一導 電〖生孟屬層’以光微影法來形成電路配線圖案。 •又，為了形成更微細的電路所採用的方法包含以下步BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a double-sided circuit board, and more particularly to a method of manufacturing a double-sided circuit board having double-sided conduction by a bottom via. [Prior Art] A method of manufacturing a double-sided conductive double-sided circuit substrate by a bottom via hole, for example, the method shown in (1) to (5) of FIG. 5, first prepared as shown in FIG. 5 (1) The insulating substrate 31 has metal-area laminates of conductive metal layers 32 and 33 on both sides. Next, as shown in FIG. 5 (2), the conductive metal I 33 and the insulating base material 32 are treated, and the conductive hole 34 is formed such that the side surface of the insulating base material 31 of the other conductive metal layer 32 is exposed. . Then, as shown in Fig. 5 (3), the residue when the conductive hole 34 is formed is removed. "Next, as shown in Fig. 5 (4), a conductive material is applied by an electric recording method, thereby forming a conductive metal layer 导 for conducting both sides," < conductive layer 36. Finally, as shown in FIG. 5 (5), the circuit wiring pattern is formed by a series of photolithography methods (including forming a photoresist layer, exposing, developing, etching, stripping, removing the photoresist layer, etc., not shown). The manufacturing method of the above-mentioned conventional double-sided circuit board is as shown in Fig. 6. In the above-mentioned drawing, the treatment of the conductive material 35 is insufficient in the step, and the plating deposition defective portion 37' is double-sided. The reason why the conductive metal layers 32 and 3 are defective. Shou 1280827 and 'as shown in Figure 5 (4), in the conductive hole metal layer 36 thick sound &<&# _ $ ^ bottom.卩The peripheral part of the ,, the cause of the difference. In the original U & when it is the reliability of the 艾 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , All are; ^ S thick 'but because the raw 4 layer 36 will also cover the circuits 32, 33, so the conductive metal layer such as FI 7 / 邛 形成 etched to form a circuit of the conductive metal layer thickened , so the wiring diagram t. In order to improve the problem, the patent document is filled with the method of the inside of the via hole. "There is a method of filling the inside of the via hole with electric minerals. The arrangement density of the bottom via holes is not @, and the current density of each hole unit varies depending on the hole position. As shown in FIG. 8, in the area where the common hole 34 is sparse, the filling of the common hole 34 is dense. The region 39 has a low filling degree. Based on such a difference in the rate of precipitation of the electro-minerals, when the deposition rate of the electro-chemical minerals is fast, the electro-precipitating gold 33 is contacted, and electroplating (4) is urgent (4) plus ', and electroplating is formed on the conductive metal layer 33 to form a conductive layer. The metal 4〇 (used to fill the general-purpose 34) will inhibit the precipitation of electroplating in other bottomed vias, which will make it difficult to prevent the precipitation rate from becoming extremely slow. In this way, conductive substances still exist. The problem of poor conduction between the double-sided conductive metal layers caused by the treatment is not provided. As shown in Patent Document 4, the plating material is filled in the inside of the via via, and the plating resist is not removed. When the plating resist is formed in the bottom surface of the bottomed via hole, it is difficult to suppress the deposition of unnecessary electricity on the circuit wiring. JP-A-2002-151623 (Patent Document 2) JP-A-2002-273135 (Patent Document 3) JP-A-2003-273170 (Patent Document 4) 曰本特开平10 — OBJECT OF THE INVENTION The object of the present invention is to solve the following two problems: one is to improve plating deposition failure of a circuit board (a conductive circuit for forming a double-sided circuit by a bottom via) The conduction is poor, and it is known that the thick plating method caused by the thick plating method is difficult to form a micro-circuit. The second is that the problem caused by the method of filling the conductive hole by the electroplating treatment of the conductive metal is also guided. In the configuration of the general-purpose hole, the sparse area and the densely-disposed area have different electric clock speeds for the plating film for the via hole filling, which may cause a problem of poor conduction. To solve the above problems, the method for manufacturing a circuit board according to the present invention includes the steps of: preparing a double-sided metal area laminate having a first conductive metal layer on one surface of an insulating substrate (the etching after forming the bottom via hole has a thickness that is not penetrated), and has a conductive metal layer (the thickness of which is thinner than the first conductive metal layer) on the other side of the insulating substrate; Forming a photoresist film on the second conductive metal layer; and applying the photoresist film, the conductive metal layer, and the insulating substrate from the second conductive metal layer side to the insulating substrate of the first conductive metal layer The side surface 7 1280827 is exposed to form a conductive hole; the common hole opening side is etched, and the second conductive metal layer having the opening is etched to enlarge the opening of the conductive metal layer; The first conductive metal layer at the bottom of the universal hole is a cathode for conducting a conductive metal plating on the common hole of the conductive hole (not forming an electrical connection with the second conductive metal layer having the opening) After the photoresist film is removed and removed, a conductive material is applied to the surface on the opening side of the common hole; and the conductive metal layer is formed by plating on the second conductive metal layer side to which the conductive material is applied; The circuit is formed by photolithography by the first conductive metal layer, the conductive material layer, the electroplated conductive material: the open-side conductive metal I composed of the metal layer, and the first conductive material. Wiring pattern. • Again, the method used to form a finer circuit consists of the following steps
賦予導電性物質後之第二導電性金 線圖案形成部外均形成抗鍍被膜； 將該抗鍍被膜剝離除 以電鍍來形成電路配線圖案後， 去； 將剝離抗鍵被膜後-使電路配線圖荦…第—導電性金屬層除去! 3案形成電氣分離，如此形成電路配線圖案。 此處，開口之擴大尺寸 較佳為2"m，赋…^…王周為—〜15"- 牛 丨導電性物f後藉電錢形成導電性金屬/ 之乂 4所形成之導電性 … 金屬層、及糟電鍍所形成之電路g 1280827 線圖案，其尺寸為〜20/zm，較佳為4"m〜i2"m。 本發明中賦予導電性物質的方法，可採用藉茱鍍、濺 鍍來形成薄膜的方法，或實施直接沉積等的導電化處理、 化學鍍敷處理等之任一者。 依本舍明之電路基板之製造方法，為了避免因導電性 物質賦予處理不；電錢物析4不&而產生之雙面 導電性金屬層間的導電不良，亦即為確保有底導通用孔内 壁、特別是底部周緣的導通可靠性而獲得充分的厚度，所 採用的改善方式，係以從孔底析出的電鍍物來充填有底導 通用孔的内壁。 又在確保有底導通用孔内壁之導通可靠性時，習知之 電鍍物會同時覆蓋住電路形成部而造成難以形成高密度電 路，相對於此，本發明中，藉由使第二導電性金屬層變薄， 且使導電性物質賦予後經電鍍形成之導電性金屬層厚度成 為1 /z m〜20 # m、較佳為4 " m〜12 # m，如此可減低導電性 金屬層整體厚度，而能簡單地形成出高密度電路。 又’在以電鍵物充填有底導通用孔時，依孔配置之疏 松可能會抑制其他孔内之電鍍物析出，針對此現象，本發 明在以電鍍物充填有底導通用孔之步驟，由於在第二導電 性金屬層上面形成抗鍍被膜，就算充填於有底導通用孔内 部之電艘物接觸第二導電性金屬層的情形，電鍍面積並不 會產生急劇的變化，如此可減輕依孔配置疏密所產生之其 他孔内的電鍍物析出抑制現象。 又，在以電鍍物充填有底導通用孔内部之前，藉由蝕 9 1280827 刻使第二導電性金屬層後退i #㈤〜丨5 # m、較佳為2 #瓜左 右如此可減少充填於有底導通用孔内部之電鑛物接觸第 ； 二導電性金屬層的情形，又配合上抗鍍層之遮蔽效果，同 ，時也能抑制住第二導電性金屬層上之電鍍物析出。 . 【實施方式】 參照圖式來詳細說明本發明的電路基板之製造方法。 圖1、圖2顯示出，藉由形成光阻層、曝光、#刻、 將光阻層剝離除去等一連串的步驟所組成的光微影法來形 春成電路配線圖案的情形。首先，如圖丨⑴所示準備出雙面 型金屬面積層板，係在聚醯亞胺膜等的絕緣基材丨之一面， 形成第一導電性金屬層2(8/zm厚的銅箔，其對有底導通 用孔形成後的蝕刻，具有不被貫穿的厚度），在 的另-面形成第二導電性金屬層3(一厚的：=; 度比第一導電性金屬層2為薄）。 其次，如圖1(2)所示，在比第一導電性金屬層丨薄之 第二導電性金屬層3上，積層感光性乾臈光阻，^全面曝 •光而形成光阻被膜4。 然後，如圖1(3)所示，對光阻被膜4、第二導電性金 屬層3、絕緣基材1，從第二導電性金屬層3側照射yag 雷射，以第-導電性金屬層2之絕緣基材J側面露出的方 式來形成導通用孔5。 開口側對第二導 氧化氫水溶液之 口擴大2 // m。 然後，如圖1(4)所示，從導通用孔5 電性金屬層3進行#刻處理（使用硫酸與過 混合溶液），藉此使該導電性金屬層3之開 ⑤ 1280827 然後，如圖2(1)所示，以位於導通用孔5底部之第一 導電性金屬層2為陰極，藉由電鐘法（硫酸銅電鑛），對導 通用孔5實施導電性金屬7之電鍍充填(在不致與第二導電 性金屬層3形成電氣連接的範圍）。圖中之符號8代表電鑛 用的陽極。 ^後如圖2(2)所示，將光阻被膜4剝離除去後，對 導通用孔開口側之面實施直接鏟敷處理，#此賦予導電性 物質9。 然後，如圖2(3)所示，當賦予導電性物質9後，對第 二導電性金屬層3側實施電鍍處理（使用硫酸銅電鍍液）， 藉此形成導電性金屬層1 〇。 最後，如圖2(4)所示，對位於導通用孔開口側及底側 之黾〖生孟屬層，藉由光微影法來形成電路配線圖案1 1， 如此形成電路基板。 又’為了形成更微細的電路，可採用圖3、圖4所示 的方法。 首先，如圖3(1)所示，係實施與上述圖1(1)〜圖2(2)為 止相同的步驟，而準備出在導通用孔開口側賦予導電性物 質9之基板。 然後’如圖3(2)所示，在賦予導電性物質9後之第二 導電性金屬層3側面上，除電路配線圖案形成部外均形成 抗艘被膜12。該抗鍍被膜12，係經由被覆光阻層、曝光、 顯影等一連串的步驟來形成出。 然後，如圖3(3)所示，藉由使用硫酸銅電鍍液之電鍍 11 1280827 手法來形成電路配線圖案1 3。 然後，如圖3(4)所示，將光阻被膜12剝離除去。 然後，如圖4( 1)所示，將剝離光阻被膜12後露出之導 電性物質9及第二導電性金屬層3除去，如此使電路配線 圖案彼此形成電氣分離。 表後’如圖4(2)所示，對第一導電性金屬層2，藉由 光微影法來形成電路配線圖案14，如此形成電路基板。 〔實施例1〕 使用新曰鐵化學製之雙面無黏著型銅面積層板（耶士帕 彝克斯）’其在厚25//m之聚醯亞胺膜兩面具有銅箔，且 進行半钱刻處理，而使第一導電性金屬層厚度為，第 二導電性金屬層厚度為4#m。 然後，積層上厚20 // m之負型感光性乾膜（抗鍍被膜）， 王面曝光後，用UV-YAG雷射來形成開口徑50 // m的有 底導通用孔。 然後’以硫酸及過氧化氫水溶液之混合液，將第二導 孟屬層（厚度4 // m的銅箔）所形成的開口（全周）擴大2 // m。 然後，使用硫酸銅電鍍液，藉由電鍍手法（以第一導電 ^金屬層為陰極），對有底導通用孔内部進行鍍銅被膜之充 填處理。 …、 猎由氣氧化鈉將抗鍍層剝離，以直接鍍敷處理 來賦予導電性物質。 接著’進行硫酸銅電鍍處理以在第二導電性金屬層側 ⑤ 1280827 析出6 // m厚的鍍銅被膜。之後，以一般的光微影手法來 形成電路圖案，如此製得電路配線基板。 •〔實施例2〕 如上述實施例1同樣地，使用新日鐵化學製之雙面無 黏著型鋼面積層板（耶士帕聶克斯），其在厚25//m之聚醯 亞胺膜兩面具有銅箔，且進行半蝕刻處理，而使第一導電 性金屬層厚度為8/zm，第二導電性金屬層厚度為4“m。 ^後，積層上厚20 // m之負型感光性乾膜（抗鍍被膜）， •經全面曝光後，用UV_YAG雷射來形成開口徑5—的有 底導通用孔。 然後，以硫酸及過氧化氫水溶液之混合液，將第二導 電性金屬層（厚度4// m的銅箔）所形成的開口（全周）擴大2 μ m。 然後，使用硫酸銅電鍍液，藉由電鍍手法（以第一導電 性金屬層為陰極），對有底導通用孔内部進行鍍銅被膜之充 填處理。 _ H ’藉由氫氧化納將抗鍍層剝離’以直接鍍敷處理 來賦予導電性物質。 然後，在第二導電性金屬層側的面上，積層20厚之感 光性乾膜’經曝光、顯影’藉此形成抗鑛被膜（除電路开^ 部外）。 〜成 接者，進行電鍍銅處理（使用硫酸銅電鍍液），以形 // m厚的電路配線圖案。 y氣 之後，將抗鍍被膜剝離除去，並將剝離除去後露出之 13 1280827 直接鍍敷被膜及第二導電性金屬層予以韻刻除去。 之後，以光微影手法來處理第一導電性金屬層而形成 電路圖案，如此製得電路基板。 【圖式簡單說明】 圖1(1)〜(4)係顯示本發明一實施例之製造步驟圖。 圖2(1)〜(4)係接續於圖1之製造步驟圖。 圖3(1)〜(4)顯示本發明的其他實施例之製造步驟圖。 圖4(1)、（2)係接續於圖3之製造步驟圖。 圖5(1)〜（5)係顯示習知製造方法之製造步驟圖。 圖6係習知製造方法製得之電路基板的概念截面圖。 圖7係習知製造方法製得之電路基板的概念截面圖。 圖8係習知製造方法製得之電路基板的概念截面圖。 【主要元件符號說明】 1···絕緣基材 2···第一導電性金屬層 3 ···第二導電性金屬層 4···抗鍍被膜 5···導通用孔 6···電鍍用陰極 7···導電性金屬 8···電鍍用陽極 9···導電性物質 10···導電性金屬層 11…電路配線圖案 1280827 12·· •抗 鍍 被膜 13·· •電 路 配線 圖 案 14·· •電 路 配線 圖 案 31·· •絕 緣 基材 32·· .導 電 性金 屬 層 33·· •導 電 性金 屬 層 34·· •導 通 用孔 35·· •導 電 性物 質 36" •導 電 性金 屬 37" •電 鐘物析 出 不 良部 位 38" •導 通 用孔稀疏 的區 域 39" •導 通 用孔 密 集 的區 域 40·· •導 電 性金 屬An anti-plating film is formed on the outside of the second conductive gold line pattern forming portion after the conductive material is applied; the plating resist is peeled off and plated to form a circuit wiring pattern, and then the anti-bond film is peeled off - the circuit wiring is removed Fig.... The first conductive metal layer is removed! The case is electrically separated, and the circuit wiring pattern is formed as described above. Here, the expanded size of the opening is preferably 2"m, Fu...^...Wang Zhouwei-~15"- The electrical conductivity formed by the conductive metal/theft 4 after the electric charge of the burdock conductive material f... The metal layer and the circuit formed by the plating of the g 1280827 line pattern have a size of 〜20/zm, preferably 4"m~i2" m. In the method for imparting a conductive material in the present invention, a method of forming a thin film by ruthenium plating or sputtering, or a conductive treatment such as direct deposition or an electroless plating treatment may be employed. According to the method for manufacturing a circuit board according to the present invention, in order to avoid the treatment caused by the conductive material, the conductive defect between the double-sided conductive metal layers caused by the electric energy analysis 4 is not ensured, that is, the bottom conductive common hole is ensured. A sufficient thickness is obtained for the conduction reliability of the inner wall, particularly the bottom periphery, and the improvement is adopted by filling the inner wall of the bottom conductive hole with an electroplated material deposited from the bottom of the hole. Further, in order to ensure the conduction reliability of the inner wall of the bottom conductive common hole, the conventional plating material covers the circuit forming portion at the same time, thereby making it difficult to form a high-density circuit. In contrast, in the present invention, the second conductive metal is used. The thickness of the conductive metal layer formed by plating after the conductive material is applied is 1 /zm~20 #m, preferably 4 " m~12 # m, thereby reducing the overall thickness of the conductive metal layer , and can easily form a high-density circuit. In addition, when the bottom conductive common hole is filled with the electric key, the looseness according to the hole arrangement may inhibit the precipitation of the plating in the other hole. In response to this phenomenon, the present invention fills the bottom conductive common hole with the plating, due to the step A plating resist is formed on the second conductive metal layer, and even if the electric charge filled in the bottom conductive common hole contacts the second conductive metal layer, the plating area does not change sharply, thereby reducing the dependence. Electroplating precipitation inhibition in other holes generated by pores and pores. Further, before the inside of the bottom conductive hole is filled with the plating material, the second conductive metal layer is retreated by etching 9 1280827 i (5) ~ 丨 5 # m, preferably 2 #瓜, so that the filling can be reduced. The electric mineral contact inside the bottomed common hole; the case of the second conductive metal layer, together with the shielding effect of the anti-plating layer, can also suppress the precipitation of the plating on the second conductive metal layer. [Embodiment] A method of manufacturing a circuit board of the present invention will be described in detail with reference to the drawings. Fig. 1 and Fig. 2 show a case where a circuit wiring pattern is formed by photolithography which is formed by a series of steps of forming a photoresist layer, exposing, etching, and removing the photoresist layer. First, as shown in Fig. (1), a double-sided metal-area laminate is prepared, and a first conductive metal layer 2 (8/zm thick copper foil) is formed on one surface of an insulating substrate such as a polyimide film. The etching after the formation of the bottomed common hole has a thickness that is not penetrated, and the second conductive metal layer 3 is formed on the other side (a thick:=; degree is smaller than the first conductive metal layer 2) Is thin). Next, as shown in FIG. 1 (2), a photosensitive dry photoresist is laminated on the second conductive metal layer 3 which is thinner than the first conductive metal layer, and the photoresist film 4 is formed by full exposure and light. . Then, as shown in FIG. 1 (3), the photoresist film 4, the second conductive metal layer 3, and the insulating base material 1 are irradiated with a yag laser from the side of the second conductive metal layer 3 to form a first conductive metal. The conductive hole 5 is formed in such a manner that the side surface of the insulating substrate J of the layer 2 is exposed. The opening side is enlarged by 2 // m to the mouth of the second hydrogen peroxide aqueous solution. Then, as shown in FIG. 1 (4), the etching process (using sulfuric acid and the over-mixed solution) is performed from the conductive metal layer 3 of the conductive hole 5, whereby the conductive metal layer 3 is opened 5 1280827, then As shown in FIG. 2 (1), the first conductive metal layer 2 located at the bottom of the conductive hole 5 is used as a cathode, and the conductive metal 7 is plated by the electric clock method (copper sulfate electro ore). Filling (in a range that does not form an electrical connection with the second conductive metal layer 3). Symbol 8 in the figure represents an anode for electric mining. Then, as shown in Fig. 2 (2), after the photoresist film 4 is peeled off, the surface of the opening side of the common hole is subjected to a direct shovel treatment, and the conductive material 9 is applied thereto. Then, as shown in Fig. 2 (3), after the conductive material 9 is applied, the second conductive metal layer 3 side is subjected to a plating treatment (using a copper sulfate plating solution), whereby the conductive metal layer 1 is formed. Finally, as shown in Fig. 2 (4), the circuit board 1 is formed by the photolithography method to form the circuit wiring pattern 1 1 on the opening side and the bottom side of the common hole. Further, in order to form a finer circuit, the methods shown in Figs. 3 and 4 can be employed. First, as shown in Fig. 3 (1), the same steps as those of Fig. 1 (1) to Fig. 2 (2) described above are carried out, and a substrate to which the conductive material 9 is applied to the opening of the common hole is prepared. Then, as shown in Fig. 3 (2), on the side surface of the second conductive metal layer 3 to which the conductive material 9 is applied, the anti-cavity film 12 is formed except for the circuit wiring pattern forming portion. The plating resist 12 is formed by a series of steps including coating a photoresist layer, exposure, development, and the like. Then, as shown in Fig. 3 (3), the circuit wiring pattern 13 is formed by electroplating using a copper sulfate plating solution 11 1280827. Then, as shown in Fig. 3 (4), the photoresist film 12 is peeled off. Then, as shown in Fig. 4 (1), the conductive material 9 and the second conductive metal layer 3 which are exposed after the photoresist film 12 is removed are removed, so that the circuit wiring patterns are electrically separated from each other. As shown in Fig. 4 (2), the circuit wiring pattern 14 is formed on the first conductive metal layer 2 by photolithography, thereby forming a circuit board. [Example 1] A double-sided non-adhesive copper-area laminate (Jespa Knox) made of a new barium iron chemical having a copper foil on both sides of a 25/m thick polyimide film was carried out. The thickness of the first conductive metal layer is such that the thickness of the second conductive metal layer is 4 #m. Then, a negative photosensitive thin film (anti-plating film) having a thickness of 20 // m was laminated on the laminate, and after exposure to the royal surface, a bottomed conductive hole having an opening diameter of 50 // m was formed by a UV-YAG laser. Then, the opening (full circumference) formed by the second conductor layer (copper foil having a thickness of 4 // m) was expanded by 2 // m with a mixture of sulfuric acid and an aqueous hydrogen peroxide solution. Then, using a copper sulfate plating solution, a copper plating film is filled inside the bottomed conductive hole by a plating method (the first conductive metal layer is used as a cathode). ..., hunting is stripped of the anti-plating layer by sodium oxyhydroxide, and the conductive material is imparted by direct plating treatment. Next, a copper sulfate plating treatment was performed to deposit a 6/5 m thick copper plating film on the second conductive metal layer side 5 1280827. Thereafter, a circuit pattern is formed by a general photolithography method, and a circuit wiring substrate is thus obtained. [Example 2] As in the above-mentioned Example 1, a double-sided non-adhesive steel area laminate (Jespa Nex) made of Nippon Steel Chemical Co., Ltd. was used, which was a polyimide of 25/m thick. The film has copper foil on both sides and is subjected to a half etching process so that the thickness of the first conductive metal layer is 8/zm, and the thickness of the second conductive metal layer is 4"m. ^, the thickness of the layer is 20 // m. Type photosensitive dry film (anti-plating film), • After full exposure, use UV_YAG laser to form a bottomed conductive hole with an opening diameter of 5. Then, a second mixture of sulfuric acid and hydrogen peroxide solution The opening (full circumference) formed by the conductive metal layer (copper foil having a thickness of 4/m) is enlarged by 2 μm. Then, using a copper sulfate plating solution, a plating method (using a first conductive metal layer as a cathode) is used. Filling the inside of the bottomed common hole with a copper plating film. _ H ' peeling off the plating layer by sodium hydroxide' is applied to the conductive material by direct plating treatment. Then, on the side of the second conductive metal layer On the surface, a 20-thick photosensitive dry film is exposed and developed. Into the anti-mine film (except the circuit opening part). ~Connector, perform electroplating copper treatment (using copper sulfate plating solution), in the shape of / / m thick circuit wiring pattern. After y gas, the anti-plating film is peeled off After removing and removing the exposed 13 1380827 direct plating film and the second conductive metal layer, the first conductive metal layer is processed by photolithography to form a circuit pattern. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 (1) to (4) show the manufacturing steps of an embodiment of the present invention. Fig. 2 (1) to (4) are diagrams of the manufacturing steps of Fig. 1. 3(1) to (4) show manufacturing steps of other embodiments of the present invention. Fig. 4 (1) and (2) are diagrams of manufacturing steps subsequent to Fig. 3. Fig. 5 (1) to (5) are shown Fig. 6 is a conceptual cross-sectional view of a circuit board produced by a conventional manufacturing method. Fig. 7 is a conceptual cross-sectional view of a circuit board manufactured by a conventional manufacturing method. Fig. 8 is a conventional manufacturing method. Conceptual cross-sectional view of the obtained circuit board. [Main component symbol description] 1···Insulation substrate 2···First conductive metal layer 3···Second conductive metal layer 4···Anti-plating film 5···Conducting hole 6···Calcium for plating 7···Conductive metal 8· - Electroplating anode 9 · · Conductive material 10 · · Conductive metal layer 11 ... Circuit wiring pattern 1280827 12 · · Anti-plating film 13 · · Circuit wiring pattern 14 · · Circuit wiring pattern 31 · • Insulating base material 32·· . Conductive metal layer 33·· • Conductive metal layer 34·· • Conductor hole 35·· • Conductive material 36" • Conductive metal 37" • Electric clock substance precipitation defective part 38" • Guided areas with sparse general holes 39" • Guided areas with dense holes 40·· • Conductive metal