JP2005166917A - Printed wiring board and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress the negative effect that the width of a copper circuit is reduced by etching serving to remove a seed layer and to secure a necessary request circuit width. <P>SOLUTION: A conductor circuit 13 is formed of a base region 14 on a conductive seed layer-side and a surface region 15 on a tip surface-side by electrolytic copper plating layers of different metal organizations by an adjustment of electroplating current density. The electrolytic copper plating layer of the surface region 15 is formed of the metal organization more precisely than the electrolytic copper plating layer of the base region 14. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a printed wiring board and a manufacturing method thereof, and more particularly to a printed wiring board having a conductor circuit formed by an additive method and a manufacturing method thereof.

  An additive method is known as a method of forming a printed wiring board (for example, Patent Documents 1 and 2). The steps of the additive method will be described with reference to FIGS. As shown in FIG. 8B, a thin conductive seed layer 102 is uniformly formed on one surface of the insulating substrate 101 as shown in FIG. 8A by sputtering or the like.

  Next, as shown in FIG. 8C, a resist layer 103 is formed on the conductive seed layer 102 by roll lamination of a dry film resist or application of a liquid resist. Then, as shown in FIG. 8D, a plating resist 104 patterned by exposure and development by a photolithography method is formed.

  Next, as shown in FIG. 8E, a copper plating portion (circuit plating) 106 is formed on the conductive seed layer 102 between the resists 105 by electrolytic copper plating. Thereafter, as shown in FIG. 8F, the plating resist 104 is removed. Then, as shown in FIG. 8G, the conductive seed layer 102 between the plating parts (unnecessary part) is removed by etching, and a conductor circuit by the copper plating part 106 is completed.

  Conductive circuit formation by the additive method is a narrower circuit formation than a subtractive (etching) method in which a conductive layer made of copper foil or the like uniformly formed on an insulating substrate is etched to form a circuit. Has the advantage of being able to. This is advantageous in the present situation where the circuit line width of the printed wiring board tends to be narrowed as the electronic equipment becomes lighter, thinner and smaller.

  However, in the conductor circuit formation by the additive method, the copper circuit portion (copper plating portion 106) is also etched by etching for removing the unnecessary conductive seed layer 102 performed after the circuit formation, and FIGS. ), The circuit width (land diameter) of the copper circuit portion is narrower to the width Wa than the width Wo.

For this reason, it is difficult to ensure the required circuit width when mounting the IC chip. On the other hand, if the circuit design is performed in consideration of the reduction in the circuit width in advance, the circuit density is limited.
JP 2001-196740 A JP 2001-345540 A

  The problem to be solved by the present invention is to suppress the reduction of the width of the copper circuit portion by etching for removing the seed layer in the printed wiring board by the additive method, and to secure the required required circuit width. .

  The printed wiring board according to the present invention is an additive printed wiring board in which a conductive circuit by electrolytic copper plating is formed on an insulating substrate via a conductive seed layer, wherein the conductive circuit is a base on the conductive seed layer side. Region and the surface layer region on the tip surface side are composed of electrolytic copper plating layers having different metal structures, and the electrolytic copper plating layer of the surface region is composed of a denser metal structure than the electrolytic copper plating layer of the base region ing.

  The denseness of the metal structure can be evaluated by the average particle size of the precipitated crystals constituting the electrolytic copper plating layer. In the printed wiring board according to the present invention, the average particle size of the precipitated crystals of the electrolytic copper plating layer in the surface region is the base portion. It is smaller than the average grain size of the precipitated crystals of the electrolytic copper plating layer in the region.

  Further, the printed wiring board according to the present invention is an additive printed wiring board in which a conductive circuit by electrolytic copper plating is formed on an insulating substrate via a conductive seed layer, and the conductive circuit is on the conductive seed layer side. The base region and the surface layer region on the tip surface side are composed of electrolytic copper plating layers having different current densities, and the electrolytic copper plating layer in the surface region is electrolyzed at a lower current density than the electrolytic copper plating layer in the base region. It is comprised by the copper plating layer.

  In the printed wiring board according to the present invention, preferably, the base region is composed of electrolytic copper plating layers having different metal structures in a lower region on the conductive seed layer side and an upper region on the surface layer region side. The electrolytic copper plating layer in the lower region has a denser metal structure than the electrolytic copper plating layer in the upper region.

  Moreover, in the printed wiring board by the additive method in which the conductive circuit by electrolytic copper plating is formed on the printed wiring board insulating base material according to the present invention through the conductive seed layer, the conductive circuit is at the inside and the surface portion. It is comprised by the electrolytic copper plating of a mutually different metal structure, and the electrolytic copper plating of the said surface part is comprised by the finer metal structure than the internal electrolytic copper plating.

  A method for manufacturing a printed wiring board by an additive method according to the present invention includes a resist layer forming step of forming a resist layer on a conductive seed layer formed on an insulating substrate, and exposing and developing the resist layer, A plating resist forming step for forming a plated plating resist, and electrolytic copper plating at a high current density (usually a current density) is performed, and a first portion is formed on the conductive seed layer where the plating resist is not formed. A first plating step for forming one electrolytic copper plating layer, and a second plating for performing electrolytic copper plating at a low current density to form a second electrolytic copper plating layer on the first electrolytic copper plating layer A plating resist removal step for removing the plating resist; and a conductive seed layer removal for removing unnecessary portions of the conductive seed layer by etching. And a degree.

In the printed wiring board manufacturing method according to the present invention, preferably, the current density in the second plating step is 0.1 A / dm ^{2 to} 1 A / dm ² , and the current density in the second plating step is the first density. Lower than the current density of the plating process.

The method for manufacturing a printed wiring board by the additive method according to the present invention includes a resist layer forming step of forming a resist layer on a conductive seed layer formed on an insulating substrate, and exposing and developing the resist layer. A plating resist forming step of forming a patterned plating resist, and electrolytic copper plating at a low current density, and a third electrolysis is formed on the conductive seed layer in a portion where the plating resist is not formed A third plating step for forming a copper plating layer and a first electrolytic copper plating layer on the third electrolytic copper plating layer by performing electrolytic copper plating at a high current density (normal current density) A second plating step of performing electrolytic copper plating at a low current density to form a second electrolytic copper plating layer on the first electrolytic copper plating layer, and for the plating A plating resist removing step for removing the resist,
A conductive seed layer removing step of removing unnecessary portions of the conductive seed layer by etching.

Current density of the third plating process in the manufacturing method of the printed wiring board, as well as the current density of the second plating step, it may be 0.1A ^/ dm ² ~1A ^/ dm 2 about.

  In the printed wiring board according to the present invention, the surface layer region of the electrolytic copper plating layer is composed of a denser metal structure than the electrolytic copper plating layer, and more specifically, the deposited crystal of the electrolytic copper plating layer in the surface layer region. Since the average particle diameter is small, the surface layer region of the conductor circuit has high etching resistance, and the amount of decrease in the circuit width of the surface layer region of the conductor circuit is reduced in the step of removing the conductive seed layer by etching.

  As a result, the circuit width of the surface layer area necessary for mounting the IC chip or the like in the conductor circuit can be ensured to the required circuit width without performing circuit design in anticipation of a large reduction in the circuit width in advance.

  An electrolytic copper plating layer having a dense metal structure can be obtained by setting the current density of electrolytic copper plating low. Electrolytic copper plating with low current density has a slow plating layer formation speed, so in consideration of productivity, only the surface area of the conductor circuit required for mounting IC chips etc. is formed by electrolytic copper plating with low current density, The base region of the conductor circuit whose circuit width may be narrowed is formed by electrolytic copper plating with a high current density.

  In addition, by forming the lower region on the conductive seed layer side of the base region of the conductor circuit with a dense metal structure, the undercut generated in the lower region of the conductor circuit in the step of removing the conductive seed layer by etching is performed. Progression is also reduced.

Has been.

  This makes the undercut small without requiring special treatment such as dry treatment, and does not cause defects such as insulative cover material filling that causes migration and peeling of conductor circuits, etc. Can be obtained.

  FIG. 1 shows Embodiment 1 of a printed wiring board according to the present invention.

  This printed wiring board is an additive printed wiring board in which a conductive circuit 13 is formed by electrolytic copper plating on an insulating substrate 11 made of polyimide film or the like via a conductive seed layer 12.

  In the conductor circuit 13, the base region 14 on the conductive seed layer 12 side is formed by electrolytic copper plating with a high current density (normal current density), and the surface layer region 15 on the tip surface side is formed by electrolytic copper plating with a low current density. ing.

  Here, the low current density and the high current density are mutual comparison, and the current density of the electrolytic copper plating forming the surface layer region (second electrolytic copper plating layer) 15 is the base region (first electrolytic copper). This means that the current density of the electrolytic copper plating forming the (plating layer) 14 is lower.

  The lower the current density of the electrolytic copper plating, the smaller the average grain size of the precipitated crystals constituting the electrolytic copper plating layer. Therefore, the conductor circuit 13 has a base region 14 on the conductive seed layer side and a surface layer region on the tip surface side. 15, the base region 14 and the surface layer region 15 are formed of electrolytic copper plating layers having different metal structures, so that the surface region 15 The average grain size of the precipitated crystals of the electrolytic copper plating layer is smaller than the average grain size of the precipitated crystals of the electrolytic copper plating layer in the base region 14.

  As a result, the electrolytic copper plating layer in the surface region 15 is composed of a denser metal structure than the electrolytic copper plating layer in the base region 14.

  As a result, the surface layer region 15 of the conductor circuit 13 has high etching resistance, and the surface layer region 15 of the conductor circuit 13 is reduced in the conductive seed layer removing step by etching. In order to obtain the necessary etching resistance here, the average grain size of the copper crystals is preferably 1 μm or less.

  As a result, the circuit width of the surface layer region 15 necessary for mounting the IC chip or the like in the conductor circuit 13 can be ensured to the required circuit width without designing the circuit in anticipation of a large reduction in the circuit width in advance. This makes it possible to increase the density of the circuit without significant restrictions.

  Further, in the conductor circuit 13, the base region 14 that does not affect the mounting of an IC chip or the like is usually formed by electrolytic copper plating with a current density, so that the increase in plating time due to low current density electrolytic copper plating is minimized. It is limited, and there is no significant decrease in productivity.

  The thickness of the surface layer region 15 formed by electrolytic copper plating with a low current density may be a thickness with a margin more than the thickness of the seed layer removal etching process, that is, the thickness of the conductive seed layer 12.

  When the conductive seed layer 12 is formed by electroless plating, the thickness of the conductive seed layer 12 is required to be about 1 to 2 μm from the viewpoint of pinholes and the like. When the conductive seed layer 12 is formed by sputtering or vapor deposition, the thickness of the conductive seed layer 12 is about 0.1 to 0.3 μm.

  Therefore, when the conductive seed layer 12 is formed by electroless plating, the thickness of the surface layer region 15 may be about 1 to 3 μm. When the conductive seed layer 12 is formed by sputtering or vapor deposition, the thickness of the surface layer region 15 is sufficient. The thickness may be about 0.1 to 1 μm.

  Next, Embodiment 1 of the method for manufacturing a printed wiring board according to the present invention will be described with reference to FIGS.

  Sputtering, vapor deposition, electroless plating, etc., as shown in FIG. 2 (b), over the entire surface of one side (upper surface) of the insulating base 11 made of polyimide film or the like as shown in FIG. 2 (a). Thus, the thin conductive seed layer 12 made of nickel, chromium, copper or the like is uniformly formed.

  Next, as shown in FIG. 2C, as a resist layer forming step, a resist layer 21 is formed on the entire surface of the conductive seed layer 12 by roll lamination of a dry film resist or application of a liquid resist.

  Next, as shown in FIG. 2D, as a plating resist formation step, a plating resist 22 patterned by exposure and development by a photolithography method is formed.

  Next, as shown in FIG. 2 (e), as the first plating step, electrolytic copper plating is performed at a normal current density (high current density), and the portion 23 where the plating resist 22 is not formed is formed. A first electrolytic copper plating layer (base region of the conductor circuit) 14 is formed on the conductive seed layer 12.

The current density in the first plating step may be a normal current density of about 1 A / dm ^{2 to} 10 A / dm ² , thereby ensuring productivity.

Next, as shown in FIG. 2 (f), as the second plating step, electrolytic copper plating at a low current density is performed, and a second electrolytic copper plating layer is formed on the first electrolytic copper plating layer 14. (Surface region) 15 is formed. Current density of the second plating step may at 0.1A ^/ dm ² ~1A ^/ dm 2 about, by electrolytic copper plating according to the current density, the average particle diameter of 1μm or less dense metal structure of copper precipitated crystals Thus, an electrolytic copper plating layer can be obtained.

  In addition, the 1st plating process and the 2nd plating process should just change the electroplating current density using the same electrolytic plating apparatus and the same plating bath.

  By the first plating step and the second plating step described above, a conductor circuit 13 having a two-layer structure including the first electrolytic copper plating layer 14 and the second electrolytic copper plating layer 15 is obtained.

  Next, as shown in FIG. 2G, the plating resist 22 is removed as a plating resist removal step.

  Next, as shown in FIG. 2H, as a conductive seed layer removing step, unnecessary portions of the conductive seed layer 12 are removed by whole surface etching. Thereby, the conductor circuit 13 is completed.

  The conductor circuit 13 is thinned by the entire surface etching in the conductive seed layer removing step, and the surface layer region (second electrolytic copper plating layer 15) on the tip surface side of the conductor circuit 13 is a base region (on the conductive seed layer side). Since the first electrolytic copper plating layer 14) has a denser metal structure than the electrolytic copper plating layer, the surface layer region of the conductor circuit 13 has high etching resistance, and the lateral width is reduced in the conductive seed layer removing step by etching ( Wo-Wb) is low.

  As a result, the circuit width of the surface layer area necessary for mounting the IC chip or the like in the conductor circuit can be ensured to the required circuit width without performing circuit design in anticipation of a large reduction in the circuit width in advance.

FIG. 3 (a) is a photomicrograph of 2000 times the cross section of the electrolytic copper plating layer obtained after patterning a copper foil plated at a current density of 0.5 A / dm ² and etching time of 18 seconds. FIG. 3 (c) shows a micrograph of the cross section of the electrolytic copper plating layer obtained after patterning a copper foil plated at a current density of 0.5 A / dm ² and etching time of 27 seconds. After patterning the copper foil plated at a current density of 4.0 A / dm ² , a micrograph of 2000 times the cross section of the electrolytic copper plating layer obtained with an etching time of 18 seconds is shown in FIG. After patterning the copper foil plated at 4.0 A / dm ² , 2000 times micrographs of the surface of the electrolytic copper plating layer obtained with an etching time of 27 seconds are shown.

  From these micrographs, it can be seen that when the current density of the electrolytic copper plating is low, the average particle diameter of the precipitated copper crystals is small, an electrolytic copper plating layer having a dense metal structure is obtained, and the etching resistance is improved.

  As a result of changing the current density of the electrolytic copper plating and investigating the average particle size and etching resistance of the copper crystals, it was found that the average particle size of the copper crystals is 1 μm or less in terms of etching resistance. . Therefore, in consideration of productivity, it is preferable that the average particle diameter of the copper crystals constituting the second electrolytic copper plating layer 15 is about 0.1 to 1.0 μm.

  FIG. 4 shows Embodiment 2 of the printed wiring board according to the present invention. 4, parts corresponding to those in FIG. 1 are denoted by the same reference numerals as those in FIG. 1, and description thereof is omitted.

  In this embodiment, the base region 14 on the conductive seed layer 12 side of the conductor circuit 13 includes a lower region (third electrolytic copper plating layer) 141 on the conductive seed layer 12 side and an upper region on the surface layer region 15 side ( The first electrolytic copper plating layer) 142 is composed of electrolytic copper plating layers having different metal structures, and the electrolytic copper plating layer in the lower region 141 is composed of a denser metal structure than the electrolytic copper plating layer in the upper region 142. ing.

  That is, in the base region 14, the lower region 141 is formed by electrolytic copper plating with a low current density, and the upper region 142 is formed by electrolytic copper plating with a high current density (normal current density).

  As a result, in addition to the surface layer region (second electrolytic copper plating layer) 15 of the conductor circuit 13, the lower region 141 of the base region 14 also has high etching resistance. In the conductive seed layer removal step by etching, the conductor circuit 13 The surface area 15 and the lower area 141 of the base area 14 are reduced.

  As a result, the circuit width of the surface layer region 15 necessary for mounting the IC chip or the like in the conductor circuit 13 can be ensured to the required circuit width without designing the circuit in anticipation of a large reduction in the circuit width in advance. This makes it possible to increase the density of the circuit without significant restrictions.

  In addition, the progress of undercut that occurs in the lower region of the conductor circuit 13 is reduced, the undercut is small without requiring special processing such as dry processing, and there is a problem in filling the insulating cover material that causes migration or the conductor circuit. It is possible to obtain a printed wiring board by an additive method that does not cause problems such as peeling.

  Moreover, when forming a conductor circuit by electrolytic copper plating, first performing electrolytic copper plating at a low current density also has the effect of making the circuit height uniform. The reason is as follows.

  The conductive seed layer 12 formed on the insulating substrate 11 by sputtering or the like is as thin as several thousand angstroms and has high electric resistance. For this reason, the difference in the current density of electroplating increases with the distance from the plating electrode, and the film thickness of the plating varies.

  Initially, by performing electrolytic copper plating at a low current density, the difference in current density is reduced, and the electrical resistance decreases as the plating film thickness increases. Thereafter, if electrolytic copper plating is performed at a general current density, a large difference in the initial current density can be avoided, and the plating film thickness can be made uniform. In order to make the plating film thickness uniform, in other words, in order to reduce the variation of the plating layer, the thickness of the lower region 141 (third electrolytic copper plating layer) is 1 μm or more. desirable.

  Next, Embodiment 2 of the method for manufacturing a printed wiring board according to the present invention will be described with reference to FIGS.

  Sputtering, vapor deposition, electroless plating, etc., as shown in FIG. 5 (b), over the entire surface of one side (upper surface) of the insulating substrate 11 made of polyimide film or the like as shown in FIG. 5 (a). Thus, the thin conductive seed layer 12 made of nickel, chromium, copper or the like is uniformly formed.

  Next, as shown in FIG. 5C, as a resist layer forming step, a resist layer 21 is formed on the entire surface of the conductive seed layer 12 by roll lamination of a dry film resist or application of a liquid resist.

  Next, as shown in FIG. 5D, as a plating resist forming step, a plating resist 22 patterned by exposure and development by a photolithography method is formed.

  Next, as shown in FIG. 5E, as a third plating step, on the conductive seed layer 12 in the portion 23 where the plating resist 22 is not formed by electrolytic copper plating at a low current density. A third electrolytic copper plating layer (lower region of the base region of the conductor circuit) 141 is formed.

Current density of the third plating process may be a 0.1A ^/ dm ² ~1A ^/ dm 2 about, by electrolytic copper plating according to the current density, the average particle diameter of 1μm or less dense metal structure of copper precipitated crystals Thus, an electrolytic copper plating layer can be obtained.

  Next, as shown in FIG. 5 (f), as the first plating step, the first electrolysis is performed on the third electrolytic copper plating layer 141 by electrolytic copper plating with a normal current density (high current density). A copper plating layer (upper region of the base region of the conductor circuit) 142 is formed.

The current density in the first plating step may be a normal current density of about 1 A / dm ^{2 to} 10 A / dm ² as in the first embodiment, thereby ensuring productivity.

By the third plating step and the first plating step described above, the base region 14 of the two-layered conductor circuit 13 is obtained by the third electrolytic copper plating layer 141 and the first electrolytic copper plating layer 142. As shown in FIG. 5G, as the second plating step, electrolytic copper plating with a low current density is performed, and a second electrolytic copper plating layer (surface layer) is formed on the first electrolytic copper plating layer 142. Region) 15 is formed. Current density of the second plating step may at 0.1A ^/ dm ² ~1A ^/ dm 2 about, by electrolytic copper plating according to the current density, the average particle diameter of 1μm or less dense metal structure of copper precipitated crystals The electrolytic copper plating layer by is obtained.

  In the first plating process, the second plating process, and the third plating process, the same electrolytic plating apparatus and the same plating bath are used, and only the electrolytic plating current density is changed.

  3 by the 3rd electrolytic copper plating layer 141, the 1st electrolytic copper plating layer 142, and the 2nd electrolytic copper plating layer 15 by the 3rd plating process, the 1st plating process, and the 2nd plating process which were mentioned above. A conductor circuit 13 having a layer structure is obtained.

  Next, as shown in FIG. 5H, the plating resist 22 is removed as a plating resist removal step.

  Next, as shown in FIG. 5I, as a conductive seed layer removing step, unnecessary portions of the conductive seed layer 12 are removed by whole surface etching. Thereby, the conductor circuit 13 is completed.

  The conductor circuit 13 is thinned by the entire surface etching in the conductive seed layer removing step. Among the conductor circuits 13, the surface layer region (second electrolytic copper plating layer 15) on the front surface side and the lower region of the base region of the conductor circuit Since the (third electrolytic copper plating layer 141) has a denser metal structure than the electrolytic copper plating layer in the base region (first electrolytic copper plating layer 14) on the conductive seed layer side, the surface layer region of the conductor circuit 13 In addition, the lower region of the base region has a high etching resistance, and in the step of removing the conductive seed layer by etching, the reduction in the lateral width (Wo-Wb) is small, and the progress and expansion of the undercut A are reduced.

  As a result, the circuit width of the surface layer area necessary for mounting an IC chip or the like in the conductor circuit can be ensured to the required circuit width without designing the circuit in anticipation of a large reduction in the circuit width in advance. Additive method with excellent productivity without requiring special processing such as processing, undercut is small, and there are no problems such as poor filling of the insulating cover and peeling of the conductor circuit causing migration. A printed wiring board can be manufactured.

  Moreover, when forming a conductor circuit by electrolytic copper plating, first performing electrolytic copper plating at a low current density also has the effect of making the circuit height uniform. The reason is as follows.

  The conductive seed layer 12 formed on the insulating substrate 11 by sputtering or the like is as thin as several thousand angstroms and has high electric resistance. For this reason, the difference in the current density of electroplating increases with the distance from the plating electrode, and the film thickness of the plating varies.

  Initially, by performing electrolytic copper plating at a low current density, the difference in current density is reduced, and the electrical resistance decreases as the plating film thickness increases. Thereafter, if electrolytic copper plating is performed at a general current density, a large difference in the initial current density can be avoided, and the plating film thickness can be made uniform.

  In order to make the plating film thickness uniform, in other words, in order to reduce the variation of the plating layer, the lower region of the conductive circuit 13 on the conductive seed layer side, that is, the third electrolytic copper plating layer. The thickness of 141 is desirably 1 μm or more.

  FIG. 6 shows Embodiment 3 of the printed wiring board according to the present invention. In FIG. 6 as well, portions corresponding to those in FIG. 1 are denoted by the same reference numerals as those in FIG. 1, and description thereof is omitted.

  In this embodiment, the inside 131 and the surface portion 132 of the conductor circuit 13 are configured by electrolytic copper plating of different metal structures, and the electrolytic copper plating of the surface portion 132 has a denser metal structure than the electrolytic copper plating of the inside 131. It is configured.

  That is, the inside 131 of the conductor circuit 13 is formed by electrolytic copper plating with a high current density (normal current density), and the surface portion 132 is formed by electrolytic copper plating with a low current density.

  As a result, the etching resistance of the surface portion 132 of the conductor circuit 13 is increased, and the surface layer region and the lower region of the conductor circuit 13 are reduced in the conductive seed layer removal step by etching.

  As a result, the circuit width of the conductor circuit 13 can be secured to the required circuit width without designing the circuit in anticipation of a large reduction in the circuit width in advance, and the circuit can be densified without being greatly restricted. become.

  In addition, the progress of the undercut that occurs in the lower region of the conductor circuit 13 is reduced, the undercut is small without requiring a special process such as a dry process, and there is a poor filling of the insulating cover material or the conductor circuit that causes migration. It is possible to obtain a printed wiring board by an additive method that does not cause problems such as peeling.

  Next, Embodiment 3 of the method for manufacturing a printed wiring board according to the present invention will be described with reference to FIGS.

  Sputtering, vapor deposition, electroless plating, etc., as shown in FIG. 7 (b), over the entire surface of one side (upper surface) of the insulating substrate 11 made of polyimide film or the like as shown in FIG. 7 (a). Thus, the thin conductive seed layer 12 made of nickel, chromium, copper or the like is uniformly formed.

  Next, as shown in FIG. 7C, as a resist layer forming step, a resist layer 21 is formed on the entire surface of the conductive seed layer 12 by roll lamination of a dry film resist or application of a liquid resist.

  Next, as shown in FIG. 7D, as a plating resist forming step, a plating resist 22 patterned by exposure and development by a photolithography method is formed.

  Next, as shown in FIG. 7 (e), as an internal region plating step, electrolytic copper plating is performed at a normal current density (high current density), and the conductivity of the portion 23 where the plating resist 22 is not formed. The inside 131 of the conductor circuit 13 is formed on the conductive seed layer 12.

The current density in the inner region plating step may be a normal current density of about 1 A / dm ^{2 to} 10 A / dm ² , thereby ensuring productivity.

  Next, as shown in FIG. 7F, the plating resist 22 is removed as a plating resist removal step.

  Next, as shown in FIG. 7G, as a resist layer re-forming step, the resist layer 32 is re-formed by applying a liquid resist to the whole.

  Next, as shown in FIG. 7H, as a plating resist re-forming step, a plating resist 32 patterned by exposure and development by a photolithography method is re-formed. The plating resist 32 creates a gap 33 around the inside 131 of the conductor circuit 13.

Next, as shown in FIG. 7 (i), as the surface portion plating step, electrolytic copper plating is performed at a low current density, and the entire outer surface of the inside 131 of the conductor circuit 13 is coated with the surface. A portion 132 is formed. Current density of the surface portion plating process may be a 0.1A ^/ dm ² ~1A / dm 2 about, by electrolytic copper plating according to the current density, the average particle diameter of 1μm or less dense metal structure of copper precipitated crystals An electrolytic copper plating layer is obtained.

  Next, as shown in FIG. 7J, the plating resist 32 is removed as a plating resist removal step.

  Next, as shown in FIG. 7 (k), as a conductive seed layer removing step, unnecessary portions of the conductive seed layer 12 are removed by whole surface etching. Thereby, the conductor circuit 13 is completed.

  The conductor circuit 13 is thinned by the entire surface etching in the conductive seed layer removing step. However, since the surface portion 132 of the conductor circuit 13 has a finer metal structure than the electrolytic copper plating layer in the inside 131, the outer surface of the conductor circuit 13 is obtained. Has a high etching resistance, and in the step of removing the conductive seed layer by etching, there is little decrease in lateral width, and the undercut A is less likely to expand.

(Example 1)
A Kapton EN (manufactured by Toray DuPont), which is a polyimide film, was used as an insulating substrate. This insulating substrate is set in a sputtering chamber, and argon is used as a plasma gas. Under a vacuum of 7 × 10 ⁻³ Toor, a nickel / chromium seed layer is sputtered by 100 Å, and a copper seed layer is formed thereon. 2000 angstroms were formed.

  A sample was taken out and a dry film resist (manufactured by Hitachi Chemical Co., Ltd.) was laminated. By exposing and developing the circuit design pattern on this dry film resist, the dry film resist in the circuit forming portion was removed, and only the non-circuit forming portion was covered with the dry film resist.

Then, copper was deposited in the place where the resist was not formed by electrolytic steel plating, and the circuit was formed. At this time, electrolytic steel plating was performed at a current density of 3 A / dm ² until a thickness of 7 μm, and then 1 μm was plated at a current density of 0.3 A / dm ² to form a thickness of 8 μm.

  Electrolytic copper plating uses the following sulfuric acid steel plating bath. Electricity is applied to the conductive seed layer on the insulating substrate immersed in this sulfuric acid steel plating bath, and copper is deposited where the resist is not coated. I let you.

<Sulfate steel plating bath>
Copper sulfate pentahydrate 75g / L
Sulfuric acid 190g / L
Chloride ion 50mg / L
Capper Grime CLX-A (Meltex) 5mL / L
Capper Gream CLX-C (Meltex) 5mL / L
The resist in the non-circuit forming portion was stripped using a 3% aqueous sodium hydroxide solution. Then, the conductive seed layer was removed by etching using an etching solution such as iron chloride solution or copper chloride solution.

  As a result, the width reduction amount of the surface layer portion of the conductor circuit obtained was 1.0 μm.

(Example 2)
When forming a circuit by electrolytic copper plating, electrolytic steel plating is performed at a current density of 0.3 A / dm ² until a thickness of 1 μm, and then electrolytic steel plating is performed at a current density of 3 A / dm ² until a thickness of 7 μm. Then, 1 μm was plated at a current density of 0.3 A / dm ² to form 8 μm. Except for this, the circuit was formed under the same conditions as in Example 1.

  As a result, the width reduction amount of the surface layer portion of the conductor circuit obtained was 0.9 μm, and the adder cut amount was 1.2 μm.

(Comparative Example 1)
When forming the circuit by electrolytic steel plating, the circuit was formed in the same manner as in Example 1 except that the circuit was formed up to 8 μm at a current density of 3 A / dm ² .

  As a result, the width reduction amount of the surface layer portion of the conductor circuit obtained was 1.6 μm, and the undercut amount was 2.3 μm.

It is sectional drawing which shows Embodiment 1 of the printed wiring board by this invention. (A)-(h) is process drawing which shows Embodiment 1 of the manufacturing method of the printed wiring board by this invention. (A)-(d) is a microscope picture which shows the cross section of the electrolytic copper plating layer by a low current density, and the electrolytic copper plating layer by a high current density. It is sectional drawing which shows Embodiment 2 of the printed wiring board by this invention. (A)-(i) is process drawing which shows Embodiment 2 of the manufacturing method of the printed wiring board by this invention. It is sectional drawing which shows Embodiment 3 of the printed wiring board by this invention. (A)-(k) is process drawing which shows Embodiment 3 of the manufacturing method of the printed wiring board by this invention. (A)-(g) is process drawing which shows the manufacturing method of the conventional printed wiring board.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Insulation base material 12 Conductive seed layer 13 Conductor circuit 131 Interior 132 Surface part 14 Base area | region (1st electrolytic copper plating layer)
141 Lower region (third electrolytic copper plating layer)
142 Upper region (first electrolytic copper plating layer)
15 Surface region (second electrolytic copper plating layer)
21 resist layer 22 resist for plating

Claims (8)

In the printed wiring board by the additive method in which a conductor circuit by electrolytic copper plating is formed on an insulating substrate through a conductive seed layer,
The conductive circuit is composed of an electrolytic copper plating layer having a metal structure different from that of the base region on the conductive seed layer side and the surface layer region on the tip surface side, and the electrolytic copper plating layer in the surface layer region is formed of the base region. A printed wiring board composed of a finer metal structure than the electrolytic copper plating layer. The printed wiring board according to claim 1, wherein the average grain size of the precipitated crystals of the electrolytic copper plating layer in the surface region is smaller than the average grain size of the precipitated crystals of the electrolytic copper plating layer in the base region. In the printed wiring board by the additive method in which a conductor circuit by electrolytic copper plating is formed on an insulating substrate through a conductive seed layer,
The conductor circuit is composed of an electrolytic copper plating layer having different current densities in a base region on the conductive seed layer side and a surface layer region on the tip surface side, and the electrolytic copper plating layer in the surface layer region is formed on the base region. A printed wiring board composed of an electrolytic copper plating layer having a lower current density than the electrolytic copper plating layer.   The base region is composed of electrolytic copper plating layers having different metal structures in a lower region on the conductive seed layer side and an upper region on the surface layer region side, and the electrolytic copper plating layer in the lower region is the upper region The printed wiring board according to any one of claims 1 to 3, wherein the printed wiring board is composed of a metal structure denser than the electrolytic copper plating layer. In the printed wiring board by the additive method in which a conductor circuit by electrolytic copper plating is formed on an insulating substrate through a conductive seed layer,
Printed wiring in which the conductor circuit is configured by electrolytic copper plating of metal structures different from each other inside and on the surface portion, and the electrolytic copper plating on the surface portion is configured with a denser metal structure than the internal electrolytic copper plating. Board. A resist layer forming step of forming a resist layer on the conductive seed layer formed on the insulating substrate;
A resist formation process for plating that exposes and develops the resist layer to form a patterned plating resist;
A first plating step of performing electrolytic copper plating with a high current density and forming a first electrolytic copper plating layer on the conductive seed layer in a portion where the plating resist is not formed;
A second plating step of performing electrolytic copper plating at a low current density and forming a second electrolytic copper plating layer on the first electrolytic copper plating layer;
A plating resist removal step for removing the plating resist;
A conductive seed layer removing step of removing unnecessary portions of the conductive seed layer by etching;
A method of manufacturing a printed wiring board by an additive method having The print according to claim 6, wherein a current density of the second plating step is 0.1 A / dm ^{2 to} 1 A / dm ² , and a current density of the second plating step is lower than a current density of the first plating step. A method for manufacturing a wiring board. A resist layer forming step of forming a resist layer on the conductive seed layer formed on the insulating substrate;
A resist formation process for plating that exposes and develops the resist layer to form a patterned plating resist;
A third plating step of performing electrolytic copper plating at a low current density and forming a third electrolytic copper plating layer on the conductive seed layer in a portion where the resist for plating is not formed;
A first plating step of performing electrolytic copper plating with a high current density and forming a first electrolytic copper plating layer on the third electrolytic copper plating layer;
A second plating step of performing electrolytic copper plating at a low current density and forming a second electrolytic copper plating layer on the first electrolytic copper plating layer;
A plating resist removal step for removing the plating resist;
A conductive seed layer removing step of removing unnecessary portions of the conductive seed layer by etching;
A method of manufacturing a printed wiring board by an additive method having