JP2004146666A - Multilayered circuit board and manufacturing method thereof - Google Patents
Multilayered circuit board and manufacturing method thereof Download PDFInfo
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- JP2004146666A JP2004146666A JP2002311136A JP2002311136A JP2004146666A JP 2004146666 A JP2004146666 A JP 2004146666A JP 2002311136 A JP2002311136 A JP 2002311136A JP 2002311136 A JP2002311136 A JP 2002311136A JP 2004146666 A JP2004146666 A JP 2004146666A
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- JP
- Japan
- Prior art keywords
- insulating layer
- circuit board
- interlayer insulating
- electrodeposition
- columnar conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
Description
【0001】
【発明の属する技術分野】
本発明は、回路基板とその為の製造法に関するものであり、さらに詳細にいえば、本発明は層間導通用の柱状導体を有し、層間絶縁層に電着手法で電着樹脂を用いた多層回路基板及びその製造法に関する。
【0002】
【従来の技術とその問題点】
電気・電子機器の更なる小型・軽量化の要求のために回路基板に於ける配線の密度は年々高くなっている。この要求に応えるために片面配線から、両面配線、さらには多層化が進められている。
【0003】
近年、多層回路基板においてはその内層の配線との電気的な導通を得るために、配線あるいは金属箔上に突起状導体をエッチングやメッキ、印刷などの手法で形成し、ここに絶縁樹脂をラミネ−トする事により、突起状導体が樹脂を貫通し、さらに金属箔を積層する事で層間の導通をこの突起状導体を介して得るという手法がある。
【0004】
しかしながら、突起状導体の樹脂への貫通は必ずしも安定せず、貫通が不十分な場合は層間の導通不良を起こしてしまう虞がある。
【0005】
【課題を解決するための手段】
電着手法は通電部に樹脂を析出する手法であり、適切な樹脂を選択することにより回路基板の配線間の絶縁にも適用可能なものである。
【0006】
そこで本発明では、多層回路基板の層間絶縁層として電着手法により形成した電着樹脂を適用するものであり、貫通不良による層間の導通不良を起こす虞のない多層回路基板を提供するものである。
【0007】
金属箔上に電着手法により層間絶縁層として電着樹脂を形成し、この際前加工又は後加工で電着樹脂に開口部を設け、該開口部を電解あるいは無電解メッキ又は導電ペ−ストを印刷すること等適切な手法により導電体で充填する。
【0008】
また、金属箔上にメッキ又はエッチングあるいは転写や印刷など適切な手法で柱状導体を形成し、必要に応じて特願2001−369645のように柱状導体の先端部をフォトレジストなどの非導電体でマスキングし、電着手法により絶縁膜を形成する。
【0009】
層間絶縁層に用いる電着樹脂としてはこの後配線層を形成する面が該配線層金属と接着性のある樹脂を用いる。あるいは必要に応じて層間絶縁層と該配線層金属との間に接着性の樹脂層を形成することもできる。
【0010】
また、柱状導体の先端部が樹脂により埋設される場合、研磨を行うことで柱状導体の先端部を露出させても良い。このようにして、柱状導体を有する層間絶縁層付金属箔が形成される。
【0011】
この後、層間絶縁層の電着樹脂が析出した金属箔と対向する表面に配線層を形成する。このとき、配線層の形成方法としては、層間絶縁層上に金属箔を張り合わせてサブトラクティブ法を適用できる。この場合、電着樹脂が析出した金属箔も同時に配線が形成可能である。
【0012】
配線の形成手法としては、この他、薄い金属箔を張り合わせるか、スパッタや真空蒸着のような乾式又は無電解メッキなどによる湿式の導電化層を形成し、これをシ−ド層としてセミアディティブ法により配線を形成することもできる。
【0013】
あるいは、剥離可能な基板上に所望の配線を形成し、これを層間絶縁層に位置合わせを行い転写することにより配線を形成するか、層間絶縁層上にフォトレジストなどで所望の配線とは反転した形状を形成し、これをマスクとして無電解メッキなどで配線を形成するフルアディティブ法も適用できる。
【0014】
このようにして得られた配線層及び層間絶縁層付金属箔の該金属箔を用いて所要の配線を形成できる。
【0015】
また、上記配線を形成する他の手法としては、上記金属箔を全面除去し、薄い金属箔を張り合わせるか、あるいはスパッタや真空蒸着のような乾式又は無電解メッキなどによる湿式の導電化層を形成し、これをシ−ド層としてセミアディティブ法により配線を形成することも可能である。
【0016】
あるいは、上記金属箔を全面除去し、これとは別に剥離可能な基板上に所望の配線を形成し、これを層間絶縁層に位置合わせを行い転写することにより配線を形成するか、又は同様に上記金属箔を全面除去し、層間絶縁層上にフォトレジストなどで所望の配線とは反転した形状を形成し、これをマスクとして無電解メッキなどで配線を形成するフルアディティブ法も適用できる。
【0017】
以上の方法により両面に配線層を有する回路基板が形成される。この回路基板に対し、上記手法で形成された柱状導体を有する層間絶縁層付金属箔を積層し、積層した金属箔面に上記手法で所望の配線層を形成することを繰り返すことにより多層回路基板を製作することができる。
【0018】
【発明の実施の形態】
以下、図示の実施例を参照しながら本発明をさらに説明する。図1は本発明の一実施例による多層回路基板の製造工程図である。
【0019】
まず、同図(1)のように銅箔1上に層間接続部2となる箇所にドライフィルムレジスト3で電着時の析出マスクを通常の露光現像工程で形成する。次いで、同図(2)のように露出している銅箔1の面上に電着手法により層間絶縁層4となる電着樹脂を析出させる。
【0020】
さらに、同図(3)のようにドライフィルムレジスト3を剥離して開口した層間接続部2を形成する。そこで、同図(4)のように層間絶縁層4をマスクとしてメッキ手法により柱状導体5を層間接続部2に形成する。次に、同図(5)のように層間絶縁層4及び柱状導体5上に一様に銅箔6を積層する。
【0021】
次いで、同図(6)のように両面の銅箔1、6に同時にサブトラクティブ法で所要の配線層7、8を形成する。更に、上記図(1)〜(4)の手法により形成された柱状導体を有する層間絶縁層付銅箔を両面から積層し、同図(7)のようにサブトラクティブ法により他の所要の配線層9、10を形成して多層回路基板を製作する。これらの工程を繰り返すことによりさらに層数を増すことが可能である。
【0022】
図2は本発明の他の実施例による多層回路基板の製造工程図である。この実施例では、先ず同図(1)のように銅箔12の面上に、所望の柱状導体高さの厚みを持つ銅箔11を形成し、この銅箔11にドライフィルムレジストをラミネ−トし、所定の層間接続部の箇所にエッチングマスクとなるドライフィルムレジスト13を残すように通常の露光現像工程で形成する。
【0023】
次いで、同図(2)のように銅箔11に対してエッチング処理を加えて柱状導体14を形成する。そこで、同図(3)のように柱状導体14の先端部のドライフィルムレジスト13を剥離せず電着手法により層間絶縁層15を形成する。
【0024】
さらに、同図(4)のようにドライフィルムレジスト13を剥離した段階で、層間絶縁層15及び柱状導体14の面上に一様に銅箔16を積層し、同図(5)の如く両面同時にサブトラクティブ法で所要の配線層17、18を形成する。
【0025】
そして、同図(1)〜(3)の工程を経てドライフィルムレジスト13を剥離して得られる柱状導体を有する層間絶縁層付銅箔を両面から積層し、同図(6)のようにサブトラクティブ法により他の所要の配線層19、20を形成して多層回路基板を製作する。これらの工程を繰り返すことによりさらに層数を増すことが可能である。
【0026】
【発明の効果】
本発明によれば、柱状導体が樹脂を貫通する必要がないので、層間接続不良の虞のない多層回路基板を製作することが可能である。
【図面の簡単な説明】
【図1】本発明の一実施例による多層回路基板の製造工程図。
【図2】本発明の他の実施例による多層回路基板の製造工程図。
【符号の説明】
1 銅箔
2 層間接続部
3 ドライフィルムレジスト
4 層間絶縁層
5 柱状導体
6 銅箔
7 配線層
8 配線層
9 配線層
10 配線層[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a circuit board and a manufacturing method therefor, and more specifically, the present invention has a columnar conductor for interlayer conduction, and uses an electrodeposition resin by an electrodeposition method for an interlayer insulating layer. The present invention relates to a multilayer circuit board and a method for manufacturing the same.
[0002]
[Conventional technology and its problems]
Due to the demand for further reduction in size and weight of electric and electronic devices, the density of wiring on circuit boards has been increasing year by year. In order to meet this demand, single-sided wiring, double-sided wiring, and further multilayering are being promoted.
[0003]
In recent years, in order to obtain electrical continuity with the wiring in the inner layer of a multilayer circuit board, projecting conductors are formed on the wiring or metal foil by etching, plating, printing, or the like, and the insulating resin is laminated here. There is a method in which the protruding conductor penetrates the resin by performing the heat treatment, and furthermore, a metal foil is laminated to obtain conduction between layers through the protruding conductor.
[0004]
However, the penetration of the protruding conductor into the resin is not always stable. If the penetration is insufficient, there is a possibility that poor conduction between layers may occur.
[0005]
[Means for Solving the Problems]
The electrodeposition method is a method of depositing a resin on a current-carrying part, and can be applied to insulation between wirings of a circuit board by selecting an appropriate resin.
[0006]
Therefore, in the present invention, an electrodeposition resin formed by an electrodeposition method is applied as an interlayer insulating layer of a multilayer circuit board, and a multilayer circuit board which does not have a possibility of causing a conduction failure between layers due to a penetration failure is provided. .
[0007]
An electrodeposition resin is formed as an interlayer insulating layer on a metal foil by an electrodeposition technique, and an opening is formed in the electrodeposition resin by pre-processing or post-processing, and the opening is electrolytically or electrolessly plated or a conductive paste. Is filled with a conductor by an appropriate method such as printing.
[0008]
In addition, a columnar conductor is formed on a metal foil by an appropriate method such as plating, etching, transfer, or printing, and the tip of the columnar conductor is formed of a non-conductive material such as a photoresist as necessary, as disclosed in Japanese Patent Application No. 2001-369645. Mask and form an insulating film by electrodeposition.
[0009]
As the electrodeposition resin used for the interlayer insulating layer, a resin having a surface on which a wiring layer is to be formed later adheres to the wiring layer metal is used. Alternatively, if necessary, an adhesive resin layer may be formed between the interlayer insulating layer and the wiring layer metal.
[0010]
If the tip of the columnar conductor is buried with resin, the tip of the columnar conductor may be exposed by polishing. Thus, a metal foil with an interlayer insulating layer having a columnar conductor is formed.
[0011]
Thereafter, a wiring layer is formed on the surface of the interlayer insulating layer facing the metal foil on which the electrodeposition resin is deposited. At this time, as a method for forming the wiring layer, a subtractive method can be applied by bonding a metal foil on the interlayer insulating layer. In this case, wiring can be formed simultaneously with the metal foil on which the electrodeposition resin is deposited.
[0012]
Other methods for forming the wiring include laminating thin metal foil or forming a wet conductive layer by dry or electroless plating such as sputtering or vacuum deposition, and using this as a seed layer, which is semi-additive. Wiring can also be formed by a method.
[0013]
Alternatively, a desired wiring is formed on a peelable substrate, and the wiring is formed by positioning and transferring the wiring to the interlayer insulating layer, or the desired wiring is inverted on the interlayer insulating layer using a photoresist or the like. A full-additive method in which a formed shape is formed and a wiring is formed by electroless plating or the like using this as a mask can also be applied.
[0014]
A required wiring can be formed using the metal foil of the wiring layer and the metal foil with an interlayer insulating layer obtained in this manner.
[0015]
In addition, as another method of forming the wiring, the metal foil is entirely removed, and a thin metal foil is laminated, or a wet conductive layer formed by dry or electroless plating such as sputtering or vacuum deposition is used. It is also possible to form a wiring by using this as a seed layer by a semi-additive method.
[0016]
Alternatively, the metal foil is entirely removed, a desired wiring is separately formed on a peelable substrate, and the wiring is formed by aligning and transferring this with an interlayer insulating layer, or similarly. A full additive method in which the metal foil is entirely removed, a desired wiring is formed on the interlayer insulating layer using a photoresist or the like, and the wiring is formed by electroless plating or the like using the mask as a mask, can also be applied.
[0017]
A circuit board having wiring layers on both surfaces is formed by the above method. On this circuit board, a metal foil with an interlayer insulating layer having a columnar conductor formed by the above method is laminated, and a desired wiring layer is repeatedly formed on the laminated metal foil surface by the above method. Can be manufactured.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be further described with reference to the illustrated embodiments. FIG. 1 is a manufacturing process diagram of a multilayer circuit board according to one embodiment of the present invention.
[0019]
First, as shown in FIG. 1A, a deposition mask for electrodeposition is formed with a dry film resist 3 on a
[0020]
Further, as shown in FIG. 3 (3), the
[0021]
Next, the required
[0022]
FIG. 2 is a manufacturing process diagram of a multilayer circuit board according to another embodiment of the present invention. In this embodiment, first, as shown in FIG. 1A, a copper foil 11 having a desired columnar conductor height is formed on a surface of a
[0023]
Next, as shown in FIG. 2B, the copper foil 11 is subjected to an etching process to form the
[0024]
Further, at the stage where the dry film resist 13 is peeled off as shown in FIG. 4D, a
[0025]
Then, copper foil with an interlayer insulating layer having a columnar conductor obtained by peeling off the dry film resist 13 through the steps of FIGS. 1A to 3C is laminated from both sides, and as shown in FIG. Other required wiring layers 19 and 20 are formed by the active method to manufacture a multilayer circuit board. By repeating these steps, the number of layers can be further increased.
[0026]
【The invention's effect】
According to the present invention, it is not necessary for the columnar conductor to penetrate the resin, so that it is possible to manufacture a multilayer circuit board having no risk of poor interlayer connection.
[Brief description of the drawings]
FIG. 1 is a manufacturing process diagram of a multilayer circuit board according to an embodiment of the present invention.
FIG. 2 is a manufacturing process diagram of a multilayer circuit board according to another embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF
Claims (7)
Priority Applications (1)
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JP2002311136A JP4160813B2 (en) | 2002-10-25 | 2002-10-25 | Multilayer circuit board manufacturing method |
Applications Claiming Priority (1)
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JP2002311136A JP4160813B2 (en) | 2002-10-25 | 2002-10-25 | Multilayer circuit board manufacturing method |
Publications (2)
Publication Number | Publication Date |
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JP2004146666A true JP2004146666A (en) | 2004-05-20 |
JP4160813B2 JP4160813B2 (en) | 2008-10-08 |
Family
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JP2002311136A Expired - Fee Related JP4160813B2 (en) | 2002-10-25 | 2002-10-25 | Multilayer circuit board manufacturing method |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100796981B1 (en) * | 2006-10-19 | 2008-01-22 | 삼성전기주식회사 | Method for manufacturing printed circuit board |
JP2010529693A (en) * | 2007-06-11 | 2010-08-26 | ピーピージー インダストリーズ オハイオ, インコーポレイテッド | Method for forming a solid blind via through a dielectric coating on a high density interconnect (HDI) substrate material |
-
2002
- 2002-10-25 JP JP2002311136A patent/JP4160813B2/en not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100796981B1 (en) * | 2006-10-19 | 2008-01-22 | 삼성전기주식회사 | Method for manufacturing printed circuit board |
JP2010529693A (en) * | 2007-06-11 | 2010-08-26 | ピーピージー インダストリーズ オハイオ, インコーポレイテッド | Method for forming a solid blind via through a dielectric coating on a high density interconnect (HDI) substrate material |
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JP4160813B2 (en) | 2008-10-08 |
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