JP4769056B2 - Wiring board and method of manufacturing the same - Google Patents

Description

  The present invention relates to a wiring board having conductor bumps as external connection terminals on the surface of the board and a method for manufacturing the same.

  2. Description of the Related Art Conventionally, a wiring board on which a semiconductor integrated circuit element (hereinafter referred to as “IC chip”) is mounted has a conductor bump made of solder having a shape rising from the surface of the board as an external connection terminal for connecting an IC chip.

JP 2005-26491 A

  The conductor bump as described above can be obtained by printing and reflowing a solder paste using a coating mask having an opening corresponding to the bump diameter. However, in the method of obtaining the conductor bumps by paste printing in this way, there is a limit to miniaturizing the interval and the diameter of the conductor bumps, and in recent years, it can cope with the high density wiring required for the wiring board. Have difficulty.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a method of manufacturing a wiring board capable of miniaturizing the interval and diameter of conductor bumps.

Means for Solving the Problems and Effects of the Invention

To solve the above problems, a method of manufacturing the wiring board of the present invention is a manufacturing method of a wiring substrate having a conductive bump as an external connection terminal on the substrate surface, to name a substrate surface, containing an inorganic filler, An opening is formed in the surface insulating layer composed mainly of the same resin material as that of the interlayer insulating layer, and the conductive pad is exposed on the bottom surface of the opening, and the substrate surface including the inside of the opening is electrolessly formed. and electroless Cu plating layer forming step of forming an electroless Cu plating layer by performing Cu plating, patterned by plating resist so as to expose the opening and its periphery as a mask, electroless Cu plating on the exposed portion the layers forming the electroless Cu plating layer by performing electrolytic Cu plating as a base to form a Cu bump consisting of the electroless Cu plating layer and the electrolytic Cu plated layer Characterized in that it comprises a lamp forming step.

  According to this, it is possible to obtain a conductor bump as a fine pattern of plating, as in the case of obtaining an internal wiring of a wiring board by a plating resist finely patterned by using a well-known lithography technique typified by photolithography. Therefore, it is possible to form conductor bumps with finer intervals and diameters than in the case of paste printing. Moreover, the wiring board of the present invention obtained by such a manufacturing method has the following characteristics.

That is, the wiring board of the present invention is a wiring board having conductor bumps as external connection terminals on the substrate surface, and an opening is provided in the surface insulating layer forming the substrate surface and connected to the conductor pad forming the bottom surface of the opening. The conductive bumps are formed in close contact with the inner wall and peripheral edge of the opening by plating, and the conductive pads and the conductive bumps connected thereto are formed by Cu plating. The conductive bumps are formed of an electroless Cu plating layer as a base. It is formed of Cu bumps made of an electrolytic Cu plating layer, and the surface insulating layer contains an inorganic filler and is mainly composed of the same resin material as the interlayer insulating layer . In this case, it is preferable that, for example, a roughening process is performed on the inner wall and the periphery of the opening in the surface insulating layer where the conductor bumps are in close contact. Moreover, it is preferable that the height of the part which appeared on the board | substrate surface in a conductor bump is set to 1/10 or more and 1/2 or less with respect to the diameter of opening, for example.

  According to this, since the conductor bump is formed by plating, it is formed not only in the conductor pad but also in a bowl shape and is in close contact with the inner wall and the peripheral edge of the opening, and the contact area of the conductor bump is large, and the contact It has become improved. That is, since the surface insulating layer is roughened, the adhesion of the plating to the inner wall and peripheral edge of the opening becomes strong. Therefore, even if shear stress is applied to the conductor bump between the resin material constituting the wiring board and the IC chip mounted on the resin material, the adhesion of the conductor bump is improved. Since the stress is absorbed and the occurrence of cracks at the joint is prevented, good connection reliability can be obtained. On the other hand, in conventional paste printing, since the conductor bump is formed by pouring the paste into the opening by printing, the conductor bump is only in contact rather than in close contact with the inner wall of the opening, Adhesiveness is inferior to the conductor bump in this invention.

  Next, in the wiring board of the present invention, the conductor pads and the conductor bumps connected thereto can be formed by Cu plating. According to this, since the conductor pads and the conductor bumps are formed by the same Cu plating, the adhesion between them is improved, and good connection reliability is obtained. On the other hand, a conductor bump using a conventional solder paste is usually installed on a conductor pad made of Cu plating via Ni-Au plating. In this case, phosphoric acid contained in an electroless Ni plating bath is used. The compound forms a phosphorus-enriched layer at the interface with the conductor bump made of solder, and cracks are likely to occur in this layer, so the connection reliability is inferior to the conductor bump in the present invention.

  Next, in the wiring board of the present invention, the top surface of the conductor bump can be a concave surface. That is, the wiring board of the present invention is a wiring board having conductor bumps as external connection terminals on the surface of the board, and an opening is provided in the surface insulating layer forming the surface of the board and connected to the conductor pad forming the bottom surface of the opening. The formed conductor bump is characterized in that its top surface is a concave surface. According to this, when the IC chip mounted on the wiring board is flip-chip connected, the terminal of the IC chip having a smaller diameter is fitted on the concave top surface of the conductor bump (see FIG. 2). There is an advantage that the IC chip is not easily displaced. In addition, the conductor bump has a shape that fits closely to the inner wall and the periphery of the opening (saddle shape), and the top surface is formed in a concave shape because the portion that appears on the substrate surface is larger than the opening diameter. It's easy to do. Further, the portion appearing on the substrate surface (and the top surface of the conductor bump) can be formed larger in diameter than the terminal of the IC chip without being caught by the opening diameter.

  Next, in the wiring board of the present invention, the surface insulating layer can be made of the same resin material as the interlayer insulating layer. In the conventional method of printing a solder paste, since reflow needs to be performed after printing, the surface insulating layer forming the substrate surface needs to have characteristics (solder heat resistance) that can withstand the melting temperature of the solder. . However, according to the method of forming the conductor bumps by plating as in the present invention, the surface insulating layer does not require solder heat resistance, and therefore, the same resin material as that of the interlayer insulating layer can be used.

<Wiring board>
An embodiment of a wiring board of the present invention will be described with reference to the drawings. FIG. 1 is a diagram schematically showing a cross-sectional structure of a wiring board 1 according to the first embodiment of the present invention. In the wiring board 1, a surface appearing on the upper side in the drawing is a first surface MP1, and a surface appearing on the lower side is a second surface MP2. The wiring board 1 is disposed between the IC chip and the main board (motherboard or the like). The Cu bump 7 formed on the first surface MP1 side has an IC chip as shown in FIG. Flip chip connected. On the other hand, the conductor pads 57 formed on the second surface MP2 side are provided with lead pins, solder balls, etc. (not shown), and the main board is connected thereto.

  The substrate core portion CB is mainly composed of a resin plate 2 such as a fiber reinforced resin plate (for example, a glass fiber reinforced epoxy resin), and the resin plate 2 is formed with a through hole 21A penetrating in the plate thickness direction. A through conductor 21 is formed on the inner wall by Cu plating for conducting electrical connection between the wiring laminated portions L1 and L2. The inside of the through conductor 21 is filled with a resin filler 23 made of an epoxy resin containing an inorganic filler (for example, silica filler), and the end of the through conductor 21 is a lid conductor made of Cu plating. 52 is formed.

  In the wiring laminated portions L1 and L2 provided on both surfaces of the substrate core portion CB, resin insulating layers (B11 to B13, SR1, B21 to B23, SR2) and conductor layers (M11 to M14, M21 to M24) are alternately arranged. Have a laminated structure. The conductor layers M11 to M14 and M21 to M24 include wiring 53 made of Cu plating, conductor pads 55, 56, 57, solid conductors 51, 54, and the like, and interlayer connection is made between the layers by via conductors 5. Yes. Here, the conductor pads 55 in the conductor layers M <b> 11 to M <b> 13 and M <b> 21 to M <b> 23 are conductor portions that serve as receptacles for the via conductor 5. The conductor pad 56 in the conductor layer M <b> 14 is a conductor portion that serves as a tray for the Cu bump 7. The conductor pads 57 in the conductor layer M24 are for forming lead pins and solder balls (not shown), and the surface thereof is Ni-Au plated.

  The resin insulating layers (interlayer insulating layers) B11 to B13, B21 to B23 are made of a thermosetting resin material 3 such as an epoxy resin appropriately including an inorganic filler such as silica powder, and the conductor layers M11 to M14 and M21 to M24. A via conductor 5 is formed through the insulating layer for interlayer connection. Further, on the conductor layers M14 and M24, a solder resist layer (surface layer insulation) made of a photosensitive resin material 4 such as an epoxy resin containing an inorganic filler such as silica powder as appropriate and further containing a flame retardant such as a phosphorus compound. Layers) SR1 and SR2 are formed, and openings 6A and 8A for exposing the conductor pads 56 and 57 are formed.

  The Cu bump 7 is made of Cu plating, is connected to the conductor pad 56, and has a bowl shape that is in close contact with the inner wall 61 and the peripheral edge 62 of the opening 6A of the solder resist layer SR1. That is, the Cu bump 7 has the same shape as the via conductor 5 for interlayer connection, and has a portion 75 present in the opening 6A connected to the conductor pad 56 and a diameter larger than that of the portion 75. And a portion 73 appearing on the first surface MP1. Further, the Cu bump 7 has an interval (center interval) of, for example, 150 μm or less.

  Further, as shown in FIG. 2, the Cu bump 7 has a portion 73 (the top surface 71 of the Cu bump 7) appearing on the first surface MP1 from the terminal T of the IC chip so that the IC chip can be easily flip-chip connected. Is also formed in a large diameter. Further, the top surface 71 is a concave curved surface, and when the IC chip is flip-chip connected, the terminal T fits into the concave top surface 71 to prevent displacement. The top surface 71 of the Cu bump 7 is not limited to the concave curved surface as shown in FIGS. 1 and 2, but may be a flat surface shown in FIG. 3C or a convex curved surface shown in FIG. Thus, the contact area with the terminal T can be improved.

  Further, in the Cu bump 7, the height of the portion 73 appearing on the first surface MP1 can be set to about 1/10 or more and 1/2 or less with respect to the diameter of the opening 6A. For example, the diameter of the opening 6A can be set to 80 to 100 μm, and the height of the portion 73 appearing on the first surface MP1 can be set to 10 to 50 μm. By setting this range, the IC chip can be flip-chip connected satisfactorily as described above.

  Further, the Cu bump 7 can have a protruding length from the end of the opening 6A of the portion 73 appearing on the first surface MP1 to be 1/3 or less, more preferably 1/4 or less of the adjacent opening interval. . Further, the interval between the adjacent Cu bumps 7 can be set to half or more of the interval between the adjacent openings 6A. Exceeding these may cause a short circuit between adjacent Cu bumps 7.

<Manufacturing method of wiring board>
An embodiment of a method for manufacturing a wiring board according to the present invention will be described with reference to the drawings.
The wiring board 1 is formed by alternately laminating resin insulating layers (B11 to B13, SR1, B21 to B23, SR2) and conductor layers (M11 to M14, M21 to M24) on both surfaces of the substrate core portion CB. It is obtained by forming the wiring laminated portions L1 and L2. This can be realized by using a known build-up process (a process in which a semi-additive method, a film-form resin material laminate formation technique, a photolithography technique, or the like is combined). Further, the substrate core portion CB is formed with a through hole 21A penetrating in the thickness direction by drilling in the resin plate 2 made of epoxy resin reinforced by the glass fiber 28, and the through conductor 21 covering the inner wall is plated with Cu. It is obtained by filling the hole filling material 23 inside.

  7 and 8 are process diagrams of the final stage when manufacturing the wiring laminated portions L1 and L2 of the wiring substrate 1, that is, the process of forming the Cu bumps 7 by forming the solder resist layer SR1. Prior to step 1, a conductor pad 56 is formed on the interlayer insulating layer B13.

  First, in Step 1 (Cu roughening step), Cu roughening treatment (a known microetching method, blackening treatment, etc.) is performed on the conductor pad 56 in order to improve adhesion to the resin material 4 to be formed later. Apply. In step 2 (surface insulating layer forming step), a solder resist layer SR1 (a layer made of the resin material 4) is laminated so as to cover the conductor pads 56. At this time, since the surface of the conductor pad 56 has been subjected to Cu roughening treatment, the adhesiveness with the solder resist layer SR1 is good. As will be described later, since the Cu bumps 7 are formed by Cu plating, the surface insulating layer forming the first surface MP1 is required in the case of a conventional paste printing method that requires solder reflow. The required solder heat resistance is not required. However, the surface insulating layer on the second surface MP2 side is required to have solder heat resistance because lead pins (fixed with solder) and solder balls are placed on the conductor pads 57 exposed in the openings 8A. For this reason, the surface insulating layer forming the second surface MP2 is a solder resist layer SR2 made of the resin material 4 having solder heat resistance, and the surface insulating layer forming the first surface MP1 is also made of the same resin material 4 together with this. If the solder resist layer SR1 is formed, both SR1 and SR2 can be formed at a time, so that the process becomes simple.

  Next, in step 3 (opening drilling step), the opening 6A is drilled in the solder resist layer SR1 by processing by a so-called photo via process. As a result, the conductor pad 56 is exposed on the bottom surface of the opening 6A. In step 4 (resin roughening step), a solder resist including the inner wall 61 and the peripheral edge 62 of the opening 6A is used by using potassium permanganate or the like in order to improve the adhesion to the Cu bump 7 formed later by plating. A roughening process is performed on the surface of the layer SR1.

  Next, in step 5 (bump formation step), the exposed portion is subjected to Cu plating using the plating resist MS patterned to expose the inside of the opening 6A (conductor bump 56, inner wall 61) and its peripheral edge 62 as a mask. Cu bumps 7 are formed. Specifically, the Cu bumps 7 are formed by procedures such as 5-1 (electroless plating), 5-2 (mask formation), and 5-3 (electrolytic plating). First, in 5-1 (electroless plating), a copper sulfate-based electroless Cu plating solution is applied to the entire surface of the solder resist layer SR1 including the inside of the opening 6A (conductor bump 56, inner wall 61) after applying a Pd catalyst. The electroless Cu plating layer 77 is formed by applying electroless Cu plating. In 5-2 (mask formation), a plating resist MS is formed at a position excluding the opening 6A and the peripheral edge 62 thereof. This can be obtained by exposing and developing the photosensitive resist and removing the portions of the openings 6A and the peripheral edge 62 that are exposed, thereby exposing the patterns.

  Subsequently, in 5-3 (electrolytic plating), electrolytic Cu plating is performed using the electroless Cu plating layer 77 as a base to form an electrolytic Cu plating layer 78, and the electroless Cu plating layer 77 and the electrolytic Cu plating layer 78 are formed. A Cu bump 7 is formed on the exposed portion (opening 6A and its peripheral edge 62). Here, the shape of the top surface 71 of the Cu bump 7 can be controlled when the electrolytic Cu plating layer 78 is formed. For example, as shown in FIG. 3A, the top surface 71 of the Cu bump 7 has a concave shape (FIG. 3B) depending on the thickness of the plating resist MS, the formation thickness of the electrolytic Cu plating layer 78, and the like. , Flat shape (FIG. 3C), convex shape (FIG. 3D). For example, when the formation thickness of the electrolytic Cu plating layer 78 is less than the thickness of the plating resist MS, the top surface 71 of the Cu bump 7 tends to be concave following the shape of the opening 6A, while the electrolytic Cu plating is performed. When the formation thickness of the layer 78 is increased, such a concave portion is filled, and the layer 78 is likely to be flat or convex.

  After the formation of the electrolytic Cu plating layer 78, the plating resist MS is removed, and the Cu bump 7 is obtained by removing the electroless Cu plating layer 77 existing under the plating resist MS by quick etching. Thereafter, the wiring board 1 is completed through predetermined inspections such as electrical inspection and appearance inspection.

<Other embodiments>
Hereinafter, other embodiments of the present invention will be described with reference to the drawings. In addition, about the location which overlaps with the above-mentioned 1st Embodiment, the same number is attached | subjected and description is abbreviate | omitted.

  FIG. 4 is a diagram schematically showing a cross-sectional structure of the wiring board 1B of the second embodiment. In the wiring board 1B, an insulating layer B14 using the same resin material 3 as the interlayer insulating layers B11 to B13 and B21 to 23 is used for the surface insulating layer forming the first surface MP1. This is because the Cu bumps 7 are formed by Cu plating, so that the surface heat insulating layer forming the first surface MP1 has a solder heat resistance that has been required in the case of a conventional paste printing method that requires solder reflow. This is because sex is not required. In the present embodiment, the surface insulating layer forming the second surface MP2 is also the insulating layer B24 using the resin material 3. In this case, since the insulating layers B14 and B24 can be formed at once, the process is simple.

  FIG. 5 is a diagram schematically illustrating a cross-sectional structure of the wiring board 1 </ b> C of the third embodiment. The wiring substrate 1C uses the insulating layer B14 using the same resin material 3 as the interlayer insulating layers B11 to B13 and B21 to 23 as the surface insulating layer that forms the first surface MP1, while the surface insulating layer that forms the second surface MP2. The solder resist layer SR2 made of the resin material 4 having solder heat resistance is used for the layer. This is obtained by sequentially forming the insulating layer B14 and the solder resist layer SR2. According to this, the surface layer insulating layer forming the first surface MP1 can be made of the same resin material 3 as the interlayer insulating layers B11 to B13 and B21 to 23, while being soldered to the surface layer insulating layer forming the second surface MP2. Since the resin material 4 having heat resistance is used, lead pins (fixed with solder) and solder balls can be satisfactorily installed.

  FIG. 6 is an enlarged view of a main part of a wiring board 1D of the fourth embodiment in which solder plating bumps 7H are formed instead of the Cu bumps 7. Similarly, when the solder plating bump 7H is formed, the size of the bump can be reduced as compared with the case where the solder paste is printed. Not only this but other metal plating can be similarly applied as a conductor bump. Further, a Ni plating layer 79 is interposed between the solder plating bump 7H and the conductor pad 56, thereby improving the adhesion between them.

  As mentioned above, although embodiment of this invention was described, this invention is not limited to these forms, In the range of the same identity as the invention embodied in these, it can change suitably and can implement.

The figure which represents roughly the cross-section of the wiring board (1st Embodiment) of this invention The figure showing the state where the IC chip is flip-connected to the conductor bump Illustration of conductor bump shape The figure which represents roughly the cross-section of the wiring board (2nd Embodiment) of this invention The figure which represents roughly the cross-section of the wiring board (3rd Embodiment) of this invention First modification of conductor bump Process drawing showing the manufacturing method of the wiring board of this invention Figure following Figure 8

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Wiring board 56 Conductor pad 6A Opening 61 Opening inner wall 62 Opening periphery 7 Conductive bump 71 Conductive bump top surface SR Surface insulating layer B Interlayer insulating layer MP Substrate surface MS Plating resist

Claims (7)

A wiring board having conductor bumps as external connection terminals on the substrate surface, wherein an opening is provided in a surface insulating layer forming the substrate surface, and the conductor bump connected to the conductor pad forming the bottom surface of the opening is formed by plating. The conductive pads and the conductive bumps connected to the conductive pads are formed by Cu plating in close contact with the inner wall and the peripheral edge of the opening, and the conductive bumps are an electroless Cu plating layer and an electrolytic Cu plating layer as a base. A wiring board , wherein the surface insulating layer contains an inorganic filler and is mainly composed of the same resin material as the interlayer insulating layer . The wiring board according to claim 1, wherein a roughening process is performed on an inner wall and a peripheral edge of the opening in the surface insulating layer where the conductor bumps are in close contact.   The wiring board according to claim 1, wherein a top surface of the conductor bump is a concave surface. The surface insulating layer, a wiring board according to any one of the interlayer insulating layer to become formed of the same resin material according to claim 1 to 3. The conductor bump, wherein the has a portion present in the connected the opening to the conductor pad, and appears portion on the substrate surface, the portion appearing on the substrate surface is formed in a columnar shape according Item 5. The wiring board according to any one of Items 1 to 4. The wiring board according to claim 5, wherein a height of a portion of the conductor bump that appears on the surface of the board is set to 1/10 or more and 1/2 or less with respect to a diameter of the opening. A method of manufacturing a wiring board having conductor bumps as external connection terminals on a substrate surface,
It name the substrate surface, containing an inorganic filler, an opening bored which bored an opening in the surface insulating layer formed is composed of the same resin material as the interlayer insulating layer mainly, to expose the contact pads on the bottom of the opening And an electroless Cu plating layer forming step of forming an electroless Cu plating layer by performing electroless Cu plating on the substrate surface including the inside of the opening; and patterning to expose the inside of the opening and the periphery thereof. Using the plated resist as a mask, an electrolytic Cu plating layer is formed by applying electrolytic Cu plating to the exposed portion of the electroless Cu plating layer as a base, and a Cu made of the electroless Cu plating layer and the electrolytic Cu plating layer. And a bump forming step of forming a bump.

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