KR20120029311A - Package substrate unit and method for manufacturing package substrate unit - Google Patents

Abstract

PURPOSE: A package substrate unit and a manufacturing method thereof are provided to improve connection reliability between a solder bumper formed in an electronic component and a solder bumper formed in a package substrate unit by including an electrode unit. CONSTITUTION: A package substrate unit(1) comprises an insulating layer(21) and an electrode unit. The electrode unit is formed in the insulating layer. The electrode unit establishes electricity joint with a terminal of an electronic component. The electrode unit has a protrusion. The protrusion is projected toward the electronic component. A solder resist layer(25) surrounds the electrode unit and the protrusion. The end part of the protrusion is projected from the surface of the solder resist layer.

Description

PACKAGE SUBSTRATE UNIT AND METHOD FOR MANUFACTURING PACKAGE SUBSTRATE UNIT}

Embodiments described herein relate to a package substrate unit and a manufacturing method of the package substrate unit.

Usually, the package wiring board comprised so that it has high density by a multilayered structure is calculated | required. In this regard, a wiring board configured to have a multi-layer high-density structure includes interstitial vias (IVHs) formed in the core layer, IVH pads formed in the core layer, vias formed in the reinforcement layer, to establish electrical connections between specific layers. A buildup substrate having a via pad and a wiring pattern formed in the reinforcement layer is known. Such multilayer reinforced substrates are also known to function as package substrate units.

An exemplary structure of a conventional package substrate unit 100 having a multilayer structure will be described below with reference to FIG. 19. 19 is a configuration diagram of a conventional package substrate unit 100. 20A is a sectional view of a conventional semiconductor chip mounting layer. 20B is a plan view of a conventional semiconductor chip mounting layer.

As shown in FIG. 19, the package substrate unit 100 includes a semiconductor chip mounting layer 3, a ball grid array (BGA) solder ball mounting layer 19, an insulating layer 4 (see FIG. 20A), and an insulating layer 5. ). In addition, the package substrate unit functions as an upper and a lower reinforcement layer, respectively, and has an insulating layer 14 having a via 12 and a via pad 13, and a core layer 15 and a solder resist layer 7, 16. It is formed to have a multilayer reinforcement structure having a).

The through hole 17 is formed in the core layer 15 at a predetermined position. Each through hole 17 is provided with a through hole via 18 in which a pair of via pads 13 are placed on the upper and lower sides. In addition, in the package substrate unit 100, the semiconductor chip 10 is mounted on the upper surface of the semiconductor chip mounting layer 3 as an electronic component.

The semiconductor chip mounting layer 3 includes an insulating layer 4 (see FIG. 20A), a conductive pad 6 formed on the upper surface of the insulating layer 4, and a solder resist layer 7. In the soldering resist layer 7, an opening 8 located above is formed at a predetermined position (see Fig. 19). The solder bump 11 formed in the terminal of the semiconductor chip 10 forms the solder bump 9 and the solder joint formed in the opening 8 provided in the solder resist layer 7 of the semiconductor chip mounting layer 3. . Here, eutectic solder (Sn / Pb) is used for the solder bump 9.

On the other hand, in the publication which discloses the prior art, the copper bump which functions as an electroplating electrode for forming a solder post with a copper post and a copper post is formed in the base resin layer in which electronic components, such as a semiconductor chip, are mounted A package substrate is disclosed.

(Patent Document 1) Japanese Unexamined Patent Publication No. 2008-042118

In recent years, from the viewpoint of environmental problems, solders used for mounting semiconductor chips are lead-free solders containing no lead (Pb) from eutectic solders (for example, Sn / Ag, Sn / Ag / Cu, Sn / Cu, etc.). Is being converted to).

Here, the melting point temperature (eg 220 ° C.) of the lead-free solder is higher than the melting point temperature (eg 183 ° C.) of the eutectic solder. Therefore, the lead-free solder is easily distorted due to the difference in thermal expansion when the semiconductor chip 10 is mounted on the package substrate unit 100. In addition, since the lead-free solder has a higher hardness than the eutectic solder, the lead-free solder is more fragile than the eutectic solder.

Referring to Figs. 20A and 20B, the following describes the factors causing cracks in the solder bumps 9 when using lead-free solder. Here, the stress on each solder bump 9 occurs at the interface between the different materials. More specifically, stress is generated at the interface between each opening 8 and solder bump 9 (indicated by the black circle α in the figure) on the solder resist layer 7, and the conductive pad 6 and each solder bump ( 9) occurs at the interface between them (indicated by the black circle β in the figure).

In particular, since the stress is concentrated at the interface between the openings 8 and the solder bumps 9 on the solder resist layer 7, each opening 8 and the solder bumps 9 on the solder resist layer 7 are concentrated. Cracks occur from the interface between them (indicated by the black circle α in the drawing) toward the center of the solder bump 9. If such cracking occurs inside the solder bumps 9, the connection strength between the solder bumps 11 and the solder bumps 9 formed in the terminals of the semiconductor chip 10 (see Fig. 19) is affected.

On the other hand, in the case of the package substrate disclosed in the prior art publication, since the copper post is formed in the through hole of the base resin layer, it is necessary to form an opening in the base resin layer using an expensive laser device. In addition, it is also necessary to align or coalesce the base resin layer on which the copper post is formed with the substrate on which the solder is printed.

Accordingly, an object of one embodiment of the present invention is to provide a package substrate unit capable of improving the connection reliability between the solder bumps formed on the electronic component and the solder bumps formed on the package substrate unit.

According to an aspect of an embodiment of the present invention, a package electrode unit includes an insulating layer; Through solder, an electrode unit is formed in the insulating layer to establish an electrical joint with the terminal of the electronic component located opposite the insulating layer, the electrode unit having a protrusion projecting toward the electronic component.

According to the present invention, it is possible to provide a package substrate unit capable of improving the connection reliability between the solder bumps formed on the electronic component and the solder bumps formed on the package substrate unit.

1 is a cross-sectional view of a package substrate unit according to the first embodiment,
2A is a cross-sectional view of a semiconductor chip mounting layer according to the first embodiment,
2B is a plan view of a semiconductor chip mounting layer according to the first embodiment,
3 is an explanatory diagram for illustrating exemplary dimensions of components of the semiconductor chip mounting layer;
4A is a cross-sectional view for explaining a distribution of stress applied to a solder bump,
4B is a plan view for explaining the distribution of stresses applied to the solder bumps,
5 is a view for explaining the reliability test associated with the solder bump,
6 is a flowchart for explaining a manufacturing method for manufacturing a package substrate unit,
7A to 7J are explanatory diagrams for describing a method of manufacturing a package substrate unit.
8 is a cross-sectional view of a semiconductor chip mounting layer constituting a package substrate unit according to the second embodiment,
9 is a cross-sectional view of a semiconductor chip mounting layer constituting a package substrate unit according to the third embodiment,
10 is a cross-sectional view of a semiconductor chip mounting layer constituting a package substrate unit according to the fourth embodiment,
11 is a sectional view of a semiconductor chip mounting layer constituting a package substrate unit according to the fifth embodiment,
12 is a cross-sectional view of a semiconductor chip mounting layer constituting a package substrate unit according to the sixth embodiment,
13 is a sectional view of a semiconductor chip mounting layer constituting a package substrate unit according to the seventh embodiment,
14 is a cross-sectional view of a semiconductor chip mounting layer constituting a package substrate unit according to the eighth embodiment;
15 is a sectional view of a semiconductor chip mounting layer constituting a package substrate unit according to the ninth embodiment,
16 is a cross-sectional view of a semiconductor chip mounting layer constituting a package substrate unit according to the tenth embodiment,
17 is a cross-sectional view of a semiconductor chip mounting layer constituting a package substrate unit according to the eleventh embodiment,
18 is a cross-sectional view of a semiconductor chip mounting layer constituting a package substrate unit according to the twelfth embodiment,
19 is a configuration diagram of a conventional package substrate unit,
20A is a cross-sectional view of a conventional semiconductor chip mounting layer,
20B is a plan view of a conventional semiconductor chip mounting layer.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described with reference to the accompanying drawings.

(a) First embodiment

1 is a cross-sectional view of a package substrate unit according to the first embodiment. 2A is a cross-sectional view of a semiconductor chip mounting layer according to the first embodiment. 2B is a plan view of a semiconductor chip mounting layer according to the first embodiment. 3 is an explanatory diagram for illustrating exemplary dimensions of components of the semiconductor chip mounting layer.

In addition, this invention is not limited to a present Example. In addition, in the example illustrated in the figure, the reinforcing structure is composed of two reinforcing layers. Alternatively, however, it is also possible to construct more than two layers of reinforcing structures, including the semiconductor chip mounting layer 20 on which the metal posts 24 are formed, as in the first embodiment. In the following description according to the first embodiment, it is assumed that the semiconductor chip 10 is mounted on the upper surface of the package substrate unit 1.

As shown in FIG. 1, the package substrate unit 1 includes an upper reinforcement layer 30 having a semiconductor chip mounting layer 20, a BGA solder ball mounting layer 54, a via 31, and a via pad 32. The core layer 40 and the lower reinforcement layer 50 having the vias 51 and the via pads 52 are provided. On the core layer 40, a through hole 41 is formed at a predetermined position. In each of the through holes 41, through hole vias 43 in which a pair of via pads 42 are placed up and down are disposed. In addition, the wiring 42a is formed in the core layer 40.

In the package board | substrate unit 1, the semiconductor chip mounting layer 20 provided with the insulating layer 21 is formed, and the BGA solder ball mounting layer 54 provided with the insulating layer 55 is formed. The package substrate unit 1 includes the vias 31 and via pads 32 formed in the upper reinforcement layer 30, the core layer 40, and the through hole vias 43 and vias formed in the core layer 40. The electrical connection between the pads 42 is established, and the via pads 52 and vias 51 formed in the lower reinforcement layer 50, the core layer 40, and the through hole vias formed in the core layer 40 ( 43 is formed to have a multilayer structure by establishing an electrical connection between the via pad 42 and the via pad 42. In addition, the semiconductor chip 10 is mounted as an electronic component on the upper surface of the semiconductor chip mounting layer 20.

As shown in FIGS. 2A and 2B, the semiconductor chip mounting layer 20 includes an insulating layer 21, a conductive seed metal layer 22a formed around the via 31 on the upper surface of the insulating layer 21, and And a conductive pad 23 formed on the upper surface of the conductive seed metal layer 22a, and a metal post 24 formed in a substantially central portion on the upper surface of the conductive pad 23. In addition, the semiconductor chip mounting layer 20 includes a solder resist layer 25 formed to surround the conductive pad 23 and the metal post 24. On the soldering resist layer 25, the opening 26 located in the upper side is formed in a predetermined position (two positions of FIG. 2A and FIG. 2B).

Further, on the solder resist layer 25, the openings 26 are formed not only on the metal posts 24 formed on the upper surface of each conductive pad 23, but also on the terminals of the semiconductor chip 10 (see FIG. 1). The formed solder bumps 11 (see FIG. 1) and the solder bumps 27 (see FIG. 1) forming the solder joints are also exposed.

The conductive seed metal layer 22a is located between the insulating layer 21, the bottom surface of the solder resist layer 25, and the bottom surface of the conductive pad 23. Accordingly, the conductive seed metal layer 22a is formed for the purpose of improving electrical conductivity of the conductive pad 23 and the metal post 24, improving contact with the insulating layer 21, and improving connection reliability. It is.

The conductive pad 23 is formed as a round pad member, and is made of the same material (eg, copper) as the metal post 24 formed on the upper surface of the conductive pad 23. The conductive pad 23 also functions as an electrode unit for establishing electrical connection with the terminals of the semiconductor chip 10 together with the metal posts 24. On the other hand, the conductive pad 23 is also known as a controlled collapse chip connection (C4) pad.

Each metal post 24 is made of copper material and is formed as a cylindrical post in an upward orientation at a substantially central portion of the corresponding conductive pad 23. Specifically, each of the metal posts 24 is formed on the solder resist layer 25 at positions where the openings 26 are formed and the solder bumps 27 formed in the same openings 26 are supported from the inside of the height. Formed. As a result, the solder bumps 27 are printed not only around each metal post 24 but also around each opening 26 formed in the solder resist layer 25.

Therefore, in the first embodiment, the mounting height T between the semiconductor chip 10 and the package substrate unit 1 can be maintained at a predetermined height. Specifically, in the package substrate unit 1 according to the first embodiment having the conductive pads 23 (C4 pads) of finer or narrower pitch, by providing a metal post inside the solder bumps 27, the semiconductor The mounting height T between the chip 10 and the package substrate unit 1 can be maintained at a predetermined height. As a result, distortion can be prevented from occurring in the solder bumps 27.

Moreover, in each solder bump 27, since the metal post 24 is formed so that the solder bump 27 may be supported from the height inner side, as much as the volume of the corresponding metal post 24 of the solder bump 27, The amount of solder can be reduced. As a result, the pitch P between the conductive pads 23 can be reduced as compared with the semiconductor chip mounting layer 3 (FIG. 19) according to the prior art (pitch P1> pitch P). As a result, the solder bumps can be made high by narrowing the pitch.

In the first embodiment, the metal posts 24 are formed in a cylindrical shape in order to increase the stress dispersing effect. Alternatively, metal posts 24 may be formed as quadrilateral posts, octagonal posts, polygonal posts or rod-shaped protrusions.

3 shows exemplary dimensions of the components of the semiconductor chip mounting layer 20. Specifically, in FIG. 3, the diameter dimension a of each metal post 24, the diameter dimension b of each conductive pad 23, and the diameter dimension c of the soldering resist layer 25 are shown. In addition, FIG. 3, the height size (L _2), the conductive pads of each metal post 24 height dimension (L _1), the height (d), the solder resist layer (25) of each solder bump 27 of the The pitch P between 23 is shown. In addition, the numerical value shown in FIG. 3 shows the ratio at the time of making the diameter dimension of each opening 26 formed in the soldering resist layer 25 into "1".

That is, as illustrated in FIG. 3, each metal post 24 is a cylindrical post having a diameter dimension a in the range of 0.5 to 0.7. Each conductive pad 23 has a diameter dimension (b) in the range of 1.3 to 1.5. The diameter dimension c of each opening 26 formed in the solder resist layer 25 is 1.0. On the other hand, each metal post 24 has a height dimension L _{1 in} the range of 0.3 to 0.7. Each solder bump 27 has a height dimension d in the range of 0.1 to 0.83. The height dimension L ₂ of the solder resist layer 25 is in the range of 0.2 to 0.33. As a result, each metal post 24 is exposed at a position higher than the solder resist layer 25. On the other hand, the pitch P between the conductive pads 23 is in the range of 2 to 1.3.

In the present embodiment, the height dimension L ₁ of the metal post 24 is configured to be larger than the height dimension L ₂ of the solder resist layer 25 (height dimension L ₁ > height dimension L ₂ ). Due to this configuration, it is possible to reliably prevent the occurrence of cracks that concentrate (integrate) stress inside the solder bumps 27.

In this way, by placing each metal post 24 inside the corresponding solder bump 27 for the purpose of supporting the solder bumps 27, the stress generated inside the solder bumps 27 can be dispersed. .

Below, the stress dispersion effect which distributes the stress which generate | occur | produces inside the solder bump 27 by using the metal post 24 is demonstrated with reference to FIG. 4A and 4B. 4A is a cross-sectional view illustrating a stress distribution acting on the solder bumps, and FIG. 4B is a plan view illustrating a stress distribution acting on the solder bumps.

As described above, inside the solder bumps 27, stresses occur at the interface between the solder bumps 27 and other different materials. Specifically, stress is generated at the interface between the openings 26 on the solder bumps 27 and the solder resist layer 25 (shown by black circles α in the figure), and the solder bumps 27 and the respective conductive pads 23 are formed. Stress occurs at the interface (shown by the black circle β in the figure) between On the other hand, in the first embodiment, since the metal posts 24 are formed at substantially the center of the inside of each solder bump 27, the interface between the solder bumps 27 and the metal posts 24 (in the drawing). Stress also occurs in the black circle θ.

Specifically, at the interface between the solder bumps 27 and the openings 26 formed on the solder resist layer 25, the hardness difference between the solder resist layer 25 and the solder bumps 27 is large. Accordingly, cracks are likely to occur due to stress concentration or stress accumulation at these interfaces. On the other hand, at the interface between the solder bumps 27 and the metal posts 24, the hardness difference between the metal posts 24 and the solder bumps 27 is small. As a result, no stress is concentrated or accumulated at these interfaces, so that no cracking occurs.

Thus, with regard to the stresses occurring in the solder bumps 27, in addition to the interface between the solder bumps 27 and the respective openings 26 formed on the solder resist layer 25, which are typically stressed, the solder bumps Stress also occurs at the interface between the metal 27 and each metal post 24 (indicated by the black circle θ in the figure). As a result, the stress is dispersed in a manner that reduces the amount of stress concentrated at one location. Therefore, the number of stress generating positions is easily increased by the metal posts 24, and it is possible to prevent the occurrence of cracks inevitably occurring due to distortion caused by stress.

Reliability test for solder bumps with metal posts

5 shows a table for explaining the reliability test for the solder bumps 27 having the metal posts 24. Here, the reliability results for the solder bump 27 as shown in Figure 5, the solder resist layer, the height dimension height dimension (L ₁₎ of the (L ₂₎ and the metal post 24 (25 3) It depends on the ratio.

Here, 20 package substrate units were tested with the samples. In addition, the numerical values (<1, 1.5, 1.6, 1.7, 2.1, 2.6, 4.0, and 4.1) used for the conditions 1 to 8 are the metals when the height dimension of the soldering resist layer 25 is set to "1". The ratio of the height dimension of the post 24 is shown. In addition, the temperature of the thermal cycle test known as TCB is set in the range of -55 ° C to + 125 ° C. Under all conditions except condition 1, all samples were allowed to pass through TCB 3500 cycles and it was confirmed that no cracking occurred.

Specifically, if the height dimension L ₁ of the metal post 24 is set larger than the height dimension 1 of the solder resist layer 25 (e.g., conditions 2 to 8), all the samples passed TCB 3500 cycles. . Alternatively, if the height dimension L ₁ of the metal post 24 is set smaller than the height dimension 1 of the solder resist layer 25 (condition 1), after TCB 1000 cycles, the inside of the solder bumps 27 A crack occurred.

In each of the conditions 2 to 8 in which the ratio of the height dimension L ₁ of the metal post 24 was set to 1.5, 1.6, 1.7, 2.1, 2.6, 4.0 and 4.1, the solder bumps (all of the 20 samples) The evaluation test result that a crack does not generate | occur | produce inside 27) was obtained. In this way, when the height dimension L ₁ of the metal post 24 is set larger than the height dimension L ₂ of the solder resist layer 25, cracks inevitably generated due to stress concentration are caused by the solder bumps 27. It can prevent that it generate | occur | produces from inside.

Manufacturing Method Of Package Board Unit

Hereinafter, a method of manufacturing the package substrate unit according to the first embodiment will be described with reference to FIG. 6. 6 is a flowchart for explaining a method of manufacturing a package substrate unit according to the first embodiment.

As shown in Fig. 6, when manufacturing a package substrate unit, first, a core layer 40 (see Fig. 1) is formed by the substrate manufacturing system in step S1. That is, first, through hole vias 43 are formed in the core layer 40, and then the via pads 42 and the wirings 42 are formed.

Subsequently, in step S2, the upper reinforcement layer 30 and the lower reinforcement layer 50 (refer to FIG. 1) as the wiring layer are simultaneously formed on both sides of the core layer 40 (see FIG. 2). Specifically, the insulation layer 30a and the insulation layer 50a which form the upper reinforcement layer 30 and the lower reinforcement layer 50 are formed on the core layer 40, respectively. Next, vias 31, via pads 32, and wirings 32a are formed as part of the upper reinforcement layer 30. Similarly, vias 51, via pads 52, and wirings 52a are formed as part of the lower reinforcement layer 50 under the core layer 40. The operation of forming the vias 31 and 51, the via pads 32 and 52 and the wirings 32a and 52a is repeated until the required number of layers are obtained. On the other hand, except for the formation of the insulating layer, the formation of the layer is carried out in step S2 for the purpose of establishing an electrical connection between the layers. As a result of the operation in step S2, a wiring layer is formed as an inner layer between the core layer and the semiconductor chip mounting layer.

Next, in step S3, the base layer of the semiconductor chip mounting layer 20 (FIG. 1) and the base layer of the BGA solder ball mounting layer 54 (see FIG. 1) are formed. In step S2, the base layer of the semiconductor chip mounting layer 20 is formed above the reinforcing layer 30, while the base layer of the BGA solder ball mounting layer 54 is formed below the reinforcing layer 50. More specifically, the insulating layer 21 and the insulating layer 55 are formed on the inner pattern. Thereafter, the conductive seed metal layer 22 (FIG. 7A) is formed before forming the via 31 and the via 51 for the purpose of establishing electrical connection. Subsequently, the vias 31 and 51 are filled with electrolytic plating. Subsequently, a conductive pad 23 representing an electrode unit for establishing electrical connection with a terminal of the semiconductor chip 10 is formed at a position directly above the via 31, and a wiring 32 a is formed. Similarly, a BGA pad 53 representing an electrode unit is formed at a position directly below the via 51, and a wiring 52a is formed.

Next, a metal post 24 is formed on the upper surface of the conductive pad 23 in step S4. As will be described later, in step S4, a metal is formed on the upper surface of the conductive pad 23 for the purpose of supporting the solder bumps 11 formed on the semiconductor chip 10 and the solder bumps 27 forming the solder joints from the inside. The post 24 is formed. Next, in step S5, the solder resist layer 25 and the solder resist layer 60 are formed.

In step S5, the soldering resist layer 25 is formed in order to form the opening 26 in which the metal post 24 is arrange | positioned. Specifically, openings 26 are formed on the solder resist layer by drilling holes in the solder resist layer 25 by photolithography and development. At the same time, the solder resist layer 60 is formed for the purpose of forming the opening in which the BGA solder ball is mounted.

Next, in step S6, printing of the solder bumps is performed. In step S6, the solder bumps 27 which are lead-free solder are printed in the openings 26 formed in the solder resist layer 25 and printed on the upper surface of the metal post 24.

Hereinafter, a manufacturing process of the package substrate unit will be described in detail with reference to FIGS. 7A to 7J. 7A to 7J are explanatory diagrams for explaining a procedure to be performed when manufacturing the package substrate unit according to the first embodiment. Meanwhile, the manufacturing process of the package substrate unit is performed by implementing a predetermined substrate manufacturing system. Hereinafter, a description will be given with reference to an exemplary case of implementing a substrate manufacturing system.

As shown in FIG. 7A, the conductive metal seed layer 22 is formed by electroless plating before the vias 31 are filled by electroplating in the insulating layer 21 constituting the semiconductor chip mounting layer 20 (FIG. 1). To form.

The conductive seed metal layer 22 is etched in a later step (see FIG. 7F), but the conductive metal seed layer remains intact only at the bottom of the conductive pad 23 around the via 31. As described above, the conductive seed metal layer 22a remaining at the bottom of the conductive pad 23 around the via 31 is not only between the via 31 and the insulating layer 21 but also the conductive pad 23. And a seed metal layer of remarkable connection between the insulating layer 21 and the insulating layer 21. Accordingly, the conductive pad 23 and the via 31 are fixed to the insulating layer 21 by the conductive seed metal layer 22a.

Specifically, vias are formed at predetermined positions on the insulating layer 21 to roughen the surface of the insulating layer 21. Subsequently, electroless plating is performed to form a conductive seed metal layer 22, which is a metal plating seed layer, on the surface of the insulating layer 21. The conductive seed metal layer 22 is used as the conductive layer, and the vias 31 are filled by electroplating until a via lid plating layer is formed. The lead plating layer is patterned by the photolithography method to form the conductive pad 23 and the wiring 32a. As described above, the conductive pad 23 represents an electrode unit for establishing an electrical connection with the semiconductor chip 10.

Subsequently, as shown in FIG. 7B, a dry film resist layer 34 having a predetermined thickness is formed on the surface of the copper pattern layer on which the conductive pads 23 are formed using the dry film resist. The dry film resist layer 34 is formed on the semiconductor chip mounting layer 20 by a lamination method.

Then, as shown in FIG. 7C, a photolithography process is performed to expose the predetermined region on the dry film resist layer 34. Specifically, photolithography of the dry film resist is performed by a photomask to transfer a pattern for forming the metal post 24 to the region on the dry film resist layer 34 overlying the upper surface of the conductive pad 23. . Accordingly, the predetermined area exposed during the photolithography process corresponds to the position where the metal post 24 is formed.

Subsequently, as shown in FIG. 7D, the development process is performed on the predetermined region (the region corresponding to the opening of the post) on the dry film resist layer 34 exposed during the photolithography process. As a result of the developing process, an opening 35 used to form the metal post 24 is formed at a predetermined position on the dry film resist layer 34. As shown in FIG. 7D, the opening 35 has a cylindrical shape.

Next, as shown in FIG. 7E, the plating process is performed on the region where the developing process is performed. More specifically, the metal is electroplated to fill the opening 35 formed as a result of the developing process. By filling the opening 35, a cylindrical metal post 24 is formed on the upper surface of the conductive pad 23.

On the other hand, in the first embodiment, in order to form the metal post 24 on the upper surface of the conductive pad 23, a SAM-additive method using a dry film resist is performed. Alternatively, metal posts 24 may be fabricated by performing a subtractive method.

Subsequently, as shown in FIG. 7F, the dry film resist layer 34 formed on the upper surface of the insulating layer 21 is peeled off. While the dry film resist layer 34 is peeled off as shown in FIG. 7F, the conductive seed metal layer 22 is also removed by etching except for the portion remaining under the conductive pad 23. As described above, the conductive seed metal layer 22a remaining at the bottom of the conductive pad 23 around the via 31 is not only between the via 31 and the insulating layer 21 but also the conductive pad 23. And a seed metal layer of remarkable connection between the insulating layer 21 and the insulating layer 21.

Next, as shown in FIG. 7G, the solder resist layer 25 is formed to surround the metal post 24 and the conductive pad 23 formed on the upper surface of the insulating layer 21. In this case, the formation position (height dimension L ₂ ) of the soldering resist layer 25 is set lower than the height dimension L ₁ of the metal post 24. The reason is that, as described above, when the height dimension L ₁ of the metal post 24 is set higher than the height dimension L ₂ of the solder resist layer 25, it is due to the distortion caused by concentration of stress. It is because the crack which arises by making it generate | occur | produce inside the solder bump 27 can be prevented.

Next, as shown in FIG. 7H, the solder resist layer 25 formed on the upper surface of the conductive pad 23 around the metal post 24 is exposed using a photomask. Then, as shown in FIG. 7I, a developing process is performed to solder print the openings around the metal posts 24. More specifically, the upper surface of the conductive pad 23 and the peripheral region of the metal post 24 are developed. As a result, the predetermined region on the developed solder resist layer 25 becomes an opening 26 through which the solder bumps 27 are printed to form a solder joint with the solder bumps 27.

Subsequently, as shown in FIG. 7J, a solder bump 27, which is a lead-free solder, is printed around the metal post 24 located at the center of the opening 26 formed in the solder resist layer 25. As described above with reference to FIGS. 6 and 7A to 7J, the package in which the metal posts 24 are formed to support the solder bumps 27 formed on the semiconductor chip mounting layer 20 from the inside of the height may be provided. The substrate unit 1 can be manufactured.

As described above, in the semiconductor chip mounting layer 20 constituting the package substrate unit 1 according to the first embodiment, the conductive seed metal layer 22a is formed on the upper surface of the insulating layer 21 and is used as an electrode. A functioning conductive pad 23 is formed on the upper surface of the conductive seed metal layer 22a. The metal post 24 which supports the height of the solder bump 27 is formed in the substantially center part of the upper surface of the conductive pad 23. As shown in FIG. Due to the metal posts 24, the stress generated inside the solder bumps 27 can be dispersed. Therefore, the crack inevitably generated by the concentration of stress can be prevented from occurring inside the solder bumps 27.

As a result, connection reliability between the solder bumps 27 formed on the semiconductor chip mounting layer 20 and the solder bumps 11 formed on the terminals of the semiconductor chip 10 in the package substrate unit 1 can be ensured. . In addition, the pitch between the solder bumps 27 can be narrowly formed by such a metal post structure, thereby enabling a high density solder bump structure.

Hereinafter, another example of the semiconductor chip mounting layer constituting the package substrate unit according to the second to twelfth embodiments will be described with reference to FIGS. 8 to 18. In the following description of the second to twelfth embodiments, the same components as those of the semiconductor chip mounting layer 20 according to the first embodiment will be denoted by the same reference numerals, and description thereof will be omitted.

(b) Second embodiment

8 is a cross-sectional view of the semiconductor chip mounting layer 61 constituting the package substrate unit according to the second embodiment. As shown in FIG. 8, in the semiconductor chip mounting layer 61 according to the second embodiment, the surface of the metal post 24 formed on the upper surface of the conductive pad 23 and the upper surface of the conductive pad 23 are formed. Part of the surface treatment layer 81 is formed by performing a surface treatment by a heat resistant preflux treatment using an organic solderability preservative (OSP).

As described above, in the second embodiment, the oxide film and the metal post on the surface of the conductive pad 23 are formed by forming the surface treatment layer 81 on the surface of the metal post 24 and a part of the upper surface of the conductive pad 23. The oxide film at 24 can be removed. In addition, the connection strength and electrical conductivity between the solder bumps 27 formed in the openings 26 on the solder resist layer 25 and the surface of the metal post 24 as well as the surface of the conductive pad 23 can be improved. Will be.

(c) Third embodiment

9 is a cross-sectional view of the semiconductor chip mounting layer 62 constituting the package substrate unit according to the third embodiment. As shown in Fig. 9, in the semiconductor chip mounting layer 62 according to the third embodiment, the dimension of the opening 26a of the solder resist layer 25 is wider. In addition, the solder bumps 11 formed on the semiconductor chip 10 and the solder bumps 27 forming the solder joints are formed in a mushroom shape.

In this manner, in the third embodiment, the electrical conductivity of the conductive pads 23 and the solder bumps 27 with respect to the semiconductor chip 10 can be improved by the solder bumps 27. In addition, since the solder bumps 27 having the metal posts 24 do not contact the openings 26a formed in the solder resist layer 25, the number of contact boundary points decreases. As a result, cracks which inevitably occur due to the stress concentrated at the contact point can be prevented from occurring.

(d) Fourth Embodiment

10 is a cross-sectional view of the semiconductor chip mounting layer 63 constituting the package substrate unit according to the fourth embodiment. Compared with the configuration of FIG. 9 according to the third embodiment, the semiconductor chip mounting layer 63 of FIG. 10 according to the fourth embodiment further includes a surface of the metal post 24 and The surface treatment by heat-resistant preflux treatment is performed on the surface of the conductive pad 23, and differs in the point which forms the surface treatment layer 83. FIG. Thereafter, the mushroom solder bumps 27 are formed on the upper surface of the surface treatment layer 83 formed on the metal posts 24 and the conductive pads 23.

As described above, according to the fourth embodiment, as in the third embodiment, the electrical conductivity of the conductive pad 23 and the solder bumps 27 with respect to the semiconductor chip 10 can be improved. In addition, since the surface treatment layer 83 is formed on the metal posts 24 and the conductive pads 23, not only the surface of the conductive pads 23 but also the surface of the metal posts 24 and the solder bumps 27. It is possible to improve the electrical conductivity and the connection strength of.

(e) Fifth Embodiment

11 is a cross-sectional view of the semiconductor chip mounting layer 64 constituting the package substrate unit according to the fifth embodiment. As shown in FIG. 11, in the semiconductor chip mounting layer 64 according to the fifth embodiment, no solder bumps 27 are formed in the openings 26 on the solder resist layer 25. Instead, a solder 84 is formed around the surface of the metal post 24 formed on the upper surface of the conductive pad 23. As described above, in the fifth embodiment, since the solder 84 is formed only around the surface of the metal post 24, the solder bump 11 formed on the terminal of the semiconductor chip 10 and the metal post 24 are formed. It is possible to reduce the amount of solder required to form a solder joint in the solder, and this structure allows finer pitch.

(f) Sixth Embodiment

12 is a sectional view of a semiconductor chip mounting layer 65 constituting a package substrate unit according to the sixth embodiment. As shown in FIG. 12, in the semiconductor chip mounting layer 65 according to the sixth embodiment, the surface of the metal post 24 and a part of the upper surface of the conductive pad 23 are formed by heat-resistant preflux treatment. Surface treatment is performed to form the surface treatment layer 81. In addition, a solder 84 is formed on the surface of the metal post 24. As described above, in the sixth embodiment, as in the third embodiment, the amount of solder can be reduced and the pitch can be made fine. In addition, since the surface treatment layer 81 is formed, the electrical conductivity of the conductive pads 23 and the solder bumps 27 with respect to the semiconductor chip 10 can be improved.

(g) Seventh embodiment

13 is a cross-sectional view of the semiconductor chip mounting layer 66 constituting the package substrate unit according to the seventh embodiment. As shown in Fig. 13, in the semiconductor chip mounting layer 66 according to the seventh embodiment, the openings 26a formed in the solder resist layer 25 are formed with wider dimensions. In addition, the solder bumps 27 are not formed in the metal posts 24. The surface treatment layer 83 is formed on the surface of the metal post 24 and the surface of the conductive pad 23 by heat-resistant preflux treatment. In this way, in the seventh embodiment, by forming the surface treatment layer 83, the electrical conductivity of the conductive pads 23 and the solder bumps 27 with respect to the semiconductor chip 10 can be improved.

(h) Embodiment 8

14 is a cross-sectional view of the semiconductor chip mounting layer 67 constituting the package substrate unit according to the eighth embodiment. As shown in FIG. 14, in the semiconductor chip mounting layer 67 according to the eighth embodiment, a small amount of solder bumps 27a are formed on the upper surface of the metal post 24 formed on the upper surface of the conductive pad 23. do. The solder bumps 27a form a solder joint directly with the solder bumps 11 formed on the semiconductor chip 10.

Thus, in the eighth embodiment, only a small amount of solder bumps 27a are formed on the upper surface of the metal post 24, and the solder bumps 27a are formed on the semiconductor chip 10 with the solder bumps 11 formed thereon. Since the solder joint is directly formed, the electrical conductivity of the metal post 24 and the conductive pad 23 can be improved.

(i) Ninth Embodiment

15 is a cross-sectional view of a semiconductor chip mounting layer 68 constituting a package substrate unit according to the ninth embodiment. As shown in FIG. 15, in the semiconductor chip mounting layer 68 according to the ninth embodiment, the metal post 24a formed on the upper surface of the conductive pad 23 has a conical shape whose upper diameter is larger than the lower diameter. Has

In addition, the surface treatment layer 85 is subjected to surface treatment by heat-resistant preflux treatment on the surface of the metal post 24a formed on the upper surface of the conductive pad 23 and a part of the upper surface of the conductive pad 23. ). Similarly to the second embodiment, in the ninth embodiment, the surface treatment layer 85 is formed on the surface of the metal post 24a and a part of the upper surface of the conductive pad 23, whereby the opening on the solder resist layer 25 ( It is possible to improve the connection strength and the electrical conductivity between the solder bumps 27 formed in the 26 and the surface of the conductive pad 23 and the surface of the metal post 24a.

On the other hand, in the ninth embodiment, solder bumps 27 are formed on the surfaces of the openings 26 and the metal posts 24a on the solder resist layer 25. Alternatively, however, the solder bumps 27 may not be formed as in the seventh embodiment. That is, the metal post 24a may directly form the solder bump 11 and the solder joint formed on the semiconductor chip 10 through the surface treatment layer 85. In this case, the amount of solder can be reduced, thereby enabling a finer pitch structure.

(j) Tenth Embodiment

16 is a cross-sectional view of the semiconductor chip mounting layer 69 constituting the package substrate unit according to the tenth embodiment. As shown in FIG. 16, in the semiconductor chip mounting layer 69 according to the tenth embodiment, the metal post 24a formed on the upper surface of the conductive pad 23 has a conical shape in which the upper diameter is larger than the lower diameter. Have In addition, the opening 26a formed in the solder resist layer 25 is formed in a wider dimension. In addition, the solder bumps 11 formed on the semiconductor chip 10 and the solder bumps 27 forming the solder joints are formed in a mushroom shape.

Thus, in the tenth embodiment, the electrical conductivity of the solder bumps 27 and the conductive pads 23 with respect to the semiconductor chip 10 can be improved by the solder bumps 27.

(k) Eleventh embodiment

17 is a cross-sectional view of the semiconductor chip mounting layer 70 constituting the package substrate unit according to the eleventh embodiment. As shown in FIG. 17, in the semiconductor chip mounting layer 70 according to the eleventh embodiment, the metal post 24b formed on the upper surface of the conductive pad 23 has a conical shape in which the lower diameter is larger than the upper diameter. Have In addition, the surface treatment layer 85 is subjected to surface treatment by heat-resistant preflux treatment on the surface of the metal post 24b formed on the upper surface of the conductive pad 23 and a part of the upper surface of the conductive pad 23. To form.

Thus, similarly to the ninth embodiment, in the eleventh embodiment, by forming the surface treatment layer 85 on the surface of the metal post 24b and a part of the upper surface of the conductive pad 23, the solder resist layer ( The connection strength with the solder bumps 27 formed in the openings 26 on the 25 can be improved.

Alternatively, as in the ninth embodiment, the solder bumps 27 may not be formed, and through the surface treatment layer 85, the metal posts 24a may be formed from the solder bumps 27 formed on the semiconductor chip 10. It is also possible to form solder joints directly. As a result, the amount of solder can be reduced and the pitch can be made finer.

(l) Embodiment 12

18 is a cross-sectional view of the semiconductor chip mounting layer 71 constituting the package substrate unit according to the twelfth embodiment. As shown in FIG. 18, in the semiconductor chip mounting layer 71 according to the twelfth embodiment, the metal post 24b formed on the upper surface of the conductive pad 23 has a conical shape in which the lower diameter is larger than the upper diameter. Have In addition, the openings 26a formed in the solder resist layer 25a have a wider dimension. In addition, the solder bumps 11 formed on the semiconductor chip 10 and the solder bumps 27 forming the solder joints are formed in a mushroom shape.

Claims (11)

Insulating layer;
An electrode unit formed in the insulating layer to establish an electrical joint with a terminal of an electronic component located opposite the insulating layer through solder;
Including;
And the electrode unit has a protrusion projecting toward the electronic component. The method of claim 1, further comprising a solder resist layer formed to surround the electrode unit and the protrusion,
An end portion of the protruding portion protrudes from a surface of the solder resist layer. The package substrate unit of claim 1, wherein the electrode unit and the protrusion are made of the same material. The package substrate unit of claim 1, wherein the protrusion is formed in a cylindrical shape. The package substrate unit according to claim 1, wherein the protruding portion is provided with a surface treatment layer formed by heat resistant preflux treatment, electrolyte surface treatment, or electroless surface treatment. Electronic parts;
Insulating layer;
An electrode unit formed in the insulating layer to establish an electrical joint with a terminal of an electronic component located opposite the insulating layer through solder;
Including;
And the electrode unit has a protrusion projecting toward the electronic component. The method of claim 6, further comprising a solder resist layer formed to surround the electrode unit and the protrusion,
An end portion of the protruding portion protrudes from a surface of the solder resist layer. The package substrate unit of claim 6, wherein the electrode unit and the protrusion are made of the same material. The package substrate unit of claim 6, wherein the protrusion is formed in a cylindrical shape. The package substrate unit according to claim 6, wherein the protruding portion is provided with a surface treatment layer formed by heat resistant preflux treatment, electrolyte surface treatment, or electroless surface treatment. Forming a core layer;
Forming a reinforcement layer on the core layer;
Forming an electrode unit on the surface of the reinforcing layer, through solder, for establishing an electrical joint with a terminal of the electronic component;
Forming a protrusion protruding toward the electronic component on the electrode unit;
Forming a solder resist layer surrounding the electrode unit and the protrusion;
Forming an opening on the solder resist layer at a position where the protrusion is formed;
Printing a solder bump in the opening
Method of manufacturing a package substrate unit comprising a.

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