JP7336258B2 - Printed wiring board and manufacturing method thereof - Google Patents

Description

The present invention relates to a printed wiring board having plated bumps and a manufacturing method thereof.

Patent Literature 1 discloses bump formation using a plating method.

JP 2010-129996 A

However, as shown in FIG. 4, base plating layers 24' and 30' are formed on conductor pads 14a' and 14b' in openings 16a' and 16b' of different sizes formed in solder resist layer 16'. When bumps 20' and 22' having different sizes are formed by forming top plating layers 28' and 32' on the base plating layers 24' and 30' via intermediate layers 26' and 31'. , between the intermediate layer 26' and the top plating layer 28', and between the intermediate layer 31' and the top plating layer 32'.

A printed wiring board according to the present invention comprises a base insulating layer, a conductor layer formed on the base insulating layer, a base insulating layer formed on the base insulating layer and the conductor layer, and a portion of the conductor layer formed on the base insulating layer and the conductor layer. A solder resist layer having a first opening that exposes a first conductor pad and a second opening that is smaller in diameter than the first opening and exposes another part of the conductor layer as a second conductor pad. a first bump formed on the first conductor pad; and a second bump formed on the second conductor pad and having a smaller diameter than the first bump; One bump includes a first base plating layer formed in the first opening, and a substantially hemispherical first base plating layer formed on the first base plating layer with a first intermediate layer interposed therebetween. and a top plated layer of, the second bump includes a second base plated layer formed in the second opening, and a second intermediate layer on the second base plated layer. and a substantially hemispherical second top plating layer formed through, at least in the second bump, the side surface exposed from the solder resist layer of the second base plating layer and the side surface of the second intermediate layer is covered with a second top plating layer.

Further, a method for manufacturing a printed wiring board according to the present invention comprises forming an insulating base layer, forming a conductor layer on the insulating base layer, and forming a solder resist on the insulating base layer and on the conductor layer. forming a layer; forming a first opening in the solder resist layer to expose a portion of the conductor layer as a first conductor pad; forming a second opening having a smaller diameter to expose another part of the conductor layer as a second conductor pad; forming a first bump on the first conductor pad; forming a second bump having a smaller diameter than the first bump on a second contact pad, wherein forming the first bump includes a first bump within the first opening. forming a base plating layer, forming a first top plating layer on the first base plating layer via a first intermediate layer, and reflowing the first top plating layer and forming a substantially hemispherical first top plating layer in the second opening, wherein forming the second bump includes forming a second base plating layer in the second opening. forming a second top plating layer on the second base plating layer via a second intermediate layer; reflowing the second top plating layer to form a substantially hemispherical second plating layer; forming a top plating layer; and covering at least the side surface of the second base plating layer exposed from the solder resist layer and the side surface of the second intermediate layer with the second top plating layer.

1 is a cross-sectional view showing a printed wiring board according to one embodiment of the present invention; FIG. FIG. 4 is a cross-sectional view showing a printed wiring board according to another embodiment of the present invention; It is a sectional view showing a manufacturing method of a printed wired board of one embodiment of the present invention. It is a sectional view showing a manufacturing method of a printed wired board of one embodiment of the present invention. It is a sectional view showing a manufacturing method of a printed wired board of one embodiment of the present invention. It is a sectional view showing a manufacturing method of a printed wired board of one embodiment of the present invention. It is a sectional view showing a manufacturing method of a printed wired board of one embodiment of the present invention. It is a sectional view showing a manufacturing method of a printed wired board of one embodiment of the present invention. It is a sectional view showing a manufacturing method of a printed wired board of one embodiment of the present invention. It is a sectional view showing a manufacturing method of a printed wired board of one embodiment of the present invention. FIG. 2 is a cross-sectional view for explaining how cracks occur in a conventional printed wiring board;

<About the printed wiring board of the present invention>
One embodiment of the printed wiring board of the present invention will be described with reference to the drawings. 1 and 2 show an enlarged view of a part of printed wiring board 10 manufactured by the manufacturing method of the embodiment. Printed wiring board 10 may be a substrate with a core formed by alternately laminating conductor layers and resin insulation layers having predetermined circuit patterns on one or both sides of a core substrate (not shown). When conductor layers are formed on both sides of the core substrate, the conductor layers facing each other via the core substrate may be connected via through-hole conductors (not shown). Alternatively, printed wiring board 10 may be a coreless substrate obtained by alternately laminating conductor layers and resin insulating layers on a support plate (not shown) instead of the core substrate, and then removing the support plate. . In any case, as shown in FIG. 1, the printed wiring board 10 includes a base insulating layer 12 which is the outermost layer of at least one resin insulating layer, and a base insulating layer 12 formed on the base insulating layer 12. , a conductor layer 14 having a predetermined circuit pattern, and a solder resist layer 16 formed on the base insulating layer 12 and the conductor layer 14 . In many cases, a plurality of other conductor layers and resin insulation layers are alternately provided under the base insulation layer 12, but they are omitted in the drawing. However, the printed wiring board 10 may consist of one layer of the base insulating layer 12 and one layer of the conductor layer 14 .

The base insulating layer 12 can be made of, for example, a resin composition containing an inorganic filler such as silica or alumina and an epoxy resin. The conductor layer 14 is made of a conductive metal such as a metal containing copper as a main component.

The solder resist layer 16 includes first openings 16a that expose portions of the conductor layer 14 as first conductor pads 14a, and second openings 16a that are smaller in diameter than the first openings 16a and expose other portions of the conductor layer 14 as second openings 14a. and a second opening 16b exposed as a second contact pad 14b. The aspect ratio of the first opening 16a, ie, the ratio of the depth to the diameter of the bottom, can be 0.5 or less. The aspect ratio of the second opening 16b, that is, the ratio of the depth to the diameter of the bottom can be 0.6 or more.

Underlayers 18 may be formed on the first and second conductor pads 14a, 14b, respectively. Examples of the underlying layer 18 include a nickel layer formed on the surfaces of the first and second conductor pads 14a and 14b, a palladium layer formed on the nickel layer, and a gold layer formed on the palladium layer. can be done. In addition, a nickel layer and a gold layer formed on the nickel layer can be exemplified. The underlying layer 18 may not be formed.

The printed wiring board 10 further includes a first bump 20 formed on the first conductor pad 14a through the underlying layer 18 and a first bump 20 formed on the second conductor pad 14b through the underlying layer 18 to form the first bump 20 on the second conductor pad 14b. and a second bump 22 having a smaller diameter than the bump 20 of the first. If the underlying layer 18 is not formed, the first and second bumps 20, 22 can be formed directly on the first and second contact pads 14a, 14b. The first bump 20 can be used for connection to a power supply or ground line. A second bump 22 having a diameter smaller than that of the first bump 20 can be used for connection with a signal line.

The first bump 20 includes a first base plating layer 24 formed in the first opening 16a, and a first intermediate layer 26a containing, for example, nickel as a main component on the first base plating layer 24. and a first top plated layer 28 having a substantially hemispherical shape. The thickness of the first intermediate layer 26a is preferably 7 μm or less.

The first base plating layer 24 is made of a conductive metal, preferably a copper-based metal. The first base plating layer 24 is formed up to a height exceeding the surface of the solder resist layer 16 (the surface opposite to the base insulating layer 12). Thereby, the first bump 20 is stably held in the first opening 16a. The thickness B1 of the first base plating layer 24 from the surface of the solder resist layer 16 is preferably within the range of 3 μm to 20 μm.

The first top plating layer 28 has a melting point lower than that of the first base plating layer 24 and is mainly composed of a metal such as tin that is melted by reflow processing and shaped into a substantially hemispherical shape as shown in FIGS. made of a metal that The thickness of the first top plating layer 28 (vertical distance from the lower end of the first top plating layer 28 to the top of the first top plating layer on the outer peripheral surface of the first bump 20) A1 is 5 μm to 45 μm. A range is preferred. By setting the thickness A1 of the first top plating layer 28 within this range, the first bumps 20 and connection pads (not shown) of electronic components such as semiconductor chips and memories mounted on the printed wiring board 10 Good connection reliability can be obtained between

The second bump 22 is formed on the second base plating layer 30 formed in the second opening 16b and on the second base plating layer 30 via the second intermediate layer 26b mainly composed of nickel, for example. and a second top plated layer 32 having a substantially hemispherical shape. The thickness of the second intermediate layer 26b is preferably 7 μm or less.

The second base plating layer 30 is made of a conductive metal, preferably a copper-based metal. The second base plating layer 30 is preferably formed to a height exceeding the surface of the solder resist layer 16 (the surface opposite to the base insulating layer 12). Thereby, the second bump 22 is stably held in the second opening 16b. The thickness B2 of the second base plating layer 30 from the surface of the solder resist layer 16 is preferably within the range of 3 μm to 20 μm.

The second top plating layer 32 has a melting point lower than that of the second base plating layer 30 and is mainly composed of a metal such as tin that is melted by reflow processing and shaped into a substantially hemispherical shape as shown in FIGS. made of a metal that The thickness of the second top plating layer 32 (the vertical distance from the lower end of the second top plating layer 32 to the top of the second top plating layer 32 on the outer peripheral surface of the second bump 22) A2 is 5 μm to 45 μm is preferably in the range of By setting the thickness A2 of the second top plating layer 32 within this range, the second bumps 22 and connection pads (not shown) of electronic components such as semiconductor chips and memories mounted on the printed wiring board 10 Good connection reliability can be obtained between

In the printed wiring board according to the present invention shown in FIG. 1, at least the side surface of the second base plating layer 30 exposed from the solder resist layer 16 and the side surface of the second intermediate layer 26b are covered with the second top plating layer 32. It is With this configuration, the portion between the second intermediate layer 26 b and the second top plating layer 32 is covered with the second top plating layer 32 . Therefore, cracks are less likely to occur in the portion between the second intermediate layer 26b and the second top plated layer 32 .

In the printed wiring board according to the present invention shown in FIG. 2, the side surface of the first base plating layer 24 exposed from the solder resist layer 16 and the side surface of the first intermediate layer 26a are covered with the first top plating layer 28. , the side surface of the second base plating layer 30 exposed from the solder resist layer 16 and the side surface of the second intermediate layer 26b are covered with the second top plating layer 32. As shown in FIG. With this configuration, the portion between the first intermediate layer 26a and the first top plating layer 28 is covered with the first top plating layer 28, and the second intermediate layer 26b and the second top plating layer 32 are covered with the first top plating layer 28. are covered with a second top plating layer 32 . Therefore, cracks are less likely to occur at these locations.

The above-mentioned side surface is a concept including a portion between the first base plating layer 24 and the solder-resist layer 16 and a portion between the second base plating layer 30 and the solder-resist layer 16 . Therefore, the first top plating layer 28 enters the gap between the first base plating layer 24 and the solder-resist layer 16, and the second top plating layer 32 separates the second base plating layer 30 and the solder-resist layer. 16 in some cases.

<About the method for manufacturing the printed wiring board of the present invention>
A method of manufacturing the printed wiring board 10 shown in FIG. 1 according to the present invention will be described below with reference to FIGS. 3A to 3H.

FIG. 3A shows an intermediate body in which a conductor layer 14 having a predetermined circuit pattern and a solder resist layer 16 are formed on a base insulating layer 12 using a known method. In many cases, a plurality of other conductor layers and resin insulation layers are alternately formed under the base insulation layer 12, but they are omitted in the drawing. A plurality of conductor layers and resin insulation layers can be laminated on a core substrate or a support plate that can be removed later. However, printed wiring board 10 may be composed of one resin insulation layer as base insulation layer 12 and one conductor layer 14 , in which case this resin insulation layer corresponds to base insulation layer 12 . A build-up insulating resin film containing an inorganic filler such as silica or alumina and an epoxy resin can be used for the base insulating layer 12 . The solder resist layer 16 is formed with first openings 16a for exposing part of the conductor layer 14 as first conductor pads 14a and other parts of the conductor layer 14 by, for example, a carbon dioxide laser or UV-YAG laser. A second opening 16b is formed exposing two contact pads 14b. Preferably, the aspect ratio of the first opening 16a is 0.5 or less, and the aspect ratio of the second opening 16b is 0.6 or more. A base layer 18 is formed on the first and second conductor pads 14a, 14b by plating, for example, a nickel layer, a palladium layer, and a gold layer in this order. The underlying layer 18 may not be formed.

As shown in FIG. 3B, for example, electroless plating such as electroless copper plating is performed, and the surface of the intermediate (the surface of the solder resist layer 16 and the side surfaces of the first and second openings 16a and 16b) is A seed layer 34 is formed on top and on the underlayer 18 (on the contact pads 14a, 14b if the underlayer 18 is not formed).

As shown in FIG. 3C, a plating resist 36 is formed on the seed layer 34 in a predetermined pattern having openings 36a at the positions where the first and second bumps 20 and 22 (FIG. 1) are to be formed.

As shown in FIG. 3D, an electroplating process is performed to form a first base plating layer 24 and a second base plating layer 24 mainly composed of copper, for example, on the seed layer 34 exposed from the plating resist 36 . A layer 30 is formed.

Further, when forming the first and second base plating layers 24 and 30, the thickness of the first base plating layer 24 and the thickness of the second base plating layer 30 from the surface of the solder resist layer 16 are 3 μm. It is preferable to adjust the plating thickness of the first and second base plating layers 24, 30 so as to be within the range of 20 μm.

As shown in FIG. 3E, for example, electroplating is performed to form first and second intermediate layers 26a, 26b containing, for example, nickel as a main component on the first and second base plating layers 24, 30. be done. The thickness of the first and second intermediate layers 26a, 26b is preferably 7 μm or less.

As shown in FIG. 3F, an electrolytic plating process is performed to form first and second base plating layers 24, 30 with first and second intermediate layers 26a, 26b interposed therebetween. Top plating layers 28 and 32 are formed. The first and second top plating layers 28, 32 are mainly made of a metal, such as tin, which has a melting point lower than that of the first and second base plating layers 24, 30 and can be melted and formed into a substantially hemispherical shape by reflow processing. Consists of metal as a component. The thickness of the first and second top plating layers 28, 32 is preferably in the range of 5 μm to 45 μm.

As shown in FIG. 3G, the plating resist 36 is stripped. Also, the portion of the seed layer 34 exposed by removing the plating resist 36 is removed by etching.

As shown in FIG. 3H, a reflow process is performed to shape the first top plating layer 28 and the second top plating layer 32 into substantially hemispherical shapes. A first bump 20 and a second bump 20 made of a copper layer, a copper/nickel alloy layer, a nickel layer, a nickel/tin alloy layer and a tin layer are formed by reflow treatment from the side closer to the first and second conductor pads 14a and 14b. A bump 22 is formed. In addition, the reflow treatment shapes the first top plating layer 28 and the second top plating layer 32 into a substantially hemispherical shape, and at the same time, the side surfaces of the second base plating layer 30 exposed from the solder-resist layer 16 and the second top plating layer 32 are reflowed. The sides of the second intermediate layer 26b are covered with a second top plating layer 32 (example of FIG. 1, not shown in FIG. 3H) or exposed from the solder resist layer 16 of the first base plating layer 24. The side surface and the side surface of the first intermediate layer 26a are covered with the first top plating layer 28, and the side surface of the second base plating layer 30 exposed from the solder resist layer 16 and the side surface of the second intermediate layer 26b are , is coated with a second top plated layer 32 (example of FIG. 2; illustrated in FIG. 3H).

In the above-described embodiment, in the printed wiring board having the first bumps and the second bumps smaller in diameter than the first bumps, only the second bumps are covered with the top plating layer on the side surfaces, or the first bumps are covered with the top plating layer. Both the first bump and the second bump are side-coated with a top plating layer. However, the present invention can be applied not only to the case where there are bumps of two diameters, but also to printed wiring boards having bumps of a single diameter or bumps of two or more diameters.

REFERENCE SIGNS LIST 10 printed wiring board 12 base insulating layer 14 conductor layer 14a first conductor pad 14b second conductor pad 16 solder resist layer 16a first opening 16b second opening 18 foundation layer 20 first bump 22 second bump 24 first base plating layer 26a first intermediate layer 26b second intermediate layer 28 first top plating layer 30 second base plating layer 32 second top plating layer 34 seed layer 36 plating resist

Claims (16)

A printed wiring board,
a base insulating layer;
a conductor layer formed on the base insulating layer;
a first opening formed on the base insulating layer and the conductor layer and exposing a portion of the conductor layer as a first conductor pad; and the conductor layer having a smaller diameter than the first opening. A solder resist layer having a second opening that exposes another part of as a second contact pad;
a first bump formed on the first conductor pad;
a second bump formed on the second conductor pad and having a smaller diameter than the first bump;
with
The first bump includes a first base plating layer formed in the first opening, and a substantially hemispherical shape formed on the first base plating layer via a first intermediate layer. and a first top plating layer,
The second bump includes a second base plating layer formed in the second opening, and a substantially hemispherical shape formed on the second base plating layer via a second intermediate layer. and a second top plating layer,
In at least the second bump, a side surface of the second base plating layer exposed from the solder resist layer and a side surface of the second intermediate layer are covered with a second top plating layer,
The aspect ratio of the first opening is 0.5 or less, and the aspect ratio of the second opening is 0.6 or more . 2. The printed wiring board according to claim 1, wherein in the first bump, the side surface exposed from the solder resist layer of the first base plating layer and the side surface of the first intermediate layer are the first top plating layer. is covered with 2. The printed wiring board according to claim 1, wherein the thickness of said first top plating layer and said second top plating layer is 5 μm to 45 μm. 2. The printed wiring board according to claim 1, wherein said first base plating layer and said second base plating layer are each formed of a metal containing copper as a main component. 2. The printed wiring board according to claim 1, wherein the first top plating layer and the second top plating layer are each made of metal containing tin as a main component. 2. The printed wiring board according to claim 1, wherein said first base plating layer and said first conductor pad and between said second base plating layer and said first conductor pad . Each layer has a base layer consisting of a nickel layer, a palladium layer and a gold layer. 2. The printed wiring board according to claim 1, wherein the thickness of said first intermediate layer and said second intermediate layer is 7 [mu]m or less. 2. The printed wiring board according to claim 1, wherein the first and second base plating layers are formed to a height exceeding the surface of the solder-resist layer, and the first base plating layer extends from the surface of the solder-resist layer. The thickness of the plating layer and the thickness of the second base plating layer are each in the range of 3 μm to 20 μm. A method for manufacturing a printed wiring board,
forming a base insulating layer;
forming a conductor layer on the base insulating layer;
forming a solder resist layer on the base insulating layer and the conductor layer;
forming a first opening in the solder resist layer to expose a portion of the conductor layer as a first conductor pad;
forming in the solder resist layer a second opening having a diameter smaller than that of the first opening and exposing another part of the conductor layer as a second conductor pad;
forming a first bump on the first contact pad;
forming a second bump having a smaller diameter than the first bump on the second contact pad;
Forming the first bump includes: forming a first base plating layer in the first opening; forming a first base plating layer on the first base plating layer via a first intermediate layer; forming one top plating layer; and reflowing the first top plating layer to form a substantially hemispherical first top plating layer;
Forming the second bump includes forming a second base plating layer in the second opening, and forming a second base plating layer on the second base plating layer via a second intermediate layer. forming a second top plating layer; reflowing the second top plating layer to form a substantially hemispherical second top plating layer; covering the exposed side surface and the side surface of the second intermediate layer with a second top plating layer;
The aspect ratio of the first opening is 0.5 or less, and the aspect ratio of the second opening is 0.6 or more. 10. The printed wiring board manufacturing method according to claim 9 , wherein the side surface of the first base plating layer exposed from the solder resist layer and the side surface of the first intermediate layer are covered with a first top plating layer. . 10. The method of manufacturing a printed wiring board according to claim 9 , wherein the thickness of said first top plating layer and said second top plating layer is within the range of 5 μm to 45 μm. 10. The method of manufacturing a printed wiring board according to claim 9 , wherein said first base plating layer and said second base plating layer are each formed of a metal containing copper as a main component. 10. The method of manufacturing a printed wiring board according to claim 9 , wherein the first top plating layer and the second top plating layer are each formed from a metal containing tin as a main component. 10. The method of manufacturing a printed wiring board according to claim 9 , wherein: between said first base plating layer and said first conductor pad, and between said second base plating layer and said first conductor pad . forming underlayers each comprising a nickel layer, a palladium layer, and a gold layer, respectively . 10. The method of manufacturing a printed wiring board according to claim 9 , wherein the thickness of said first intermediate layer and said second intermediate layer is 7 [mu]m or less. 10. The printed wiring board manufacturing method according to claim 9 , wherein the first and second base plating layers are formed to a height exceeding the surface of the solder-resist layer, and the first base plating layer extends from the surface of the solder-resist layer. The thickness of the first base plating layer and the thickness of the second base plating layer are each within the range of 3 μm to 20 μm.

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