JP2020136652A - Manufacturing method of printed wiring board and printed wiring board - Google Patents

Abstract

To provide a manufacturing method of printed wiring board in which bump height after reflow is aligned.SOLUTION: A manufacturing method of printed wiring board includes steps of: forming a first bump on a first conductor pad; and forming a second bump of smaller diameter than that of the first bump on a second conductor pad. The step of forming the first bump includes: forming a first base plating layer 24 in a first opening; forming a first top plating layer 28 on the first base plating layer; and reflowing the first top plating layer 28. The step of forming the second bump includes: forming a second base plating layer 30 in a second opening; forming, on the second base plating layer, a second top plating layer 32 having a top face above the highest position of the top face of the first top plating layer 28; and reflowing the second top plating layer 32.SELECTED DRAWING: Figure 5

Description

The present invention relates to a method for manufacturing a printed wiring board having plated bumps and a printed wiring board.

Patent Document 1 discloses bump formation using a plating method.

JP-A-2010-129996

However, as shown in FIG. 8, the base plating layers 24'and 30'are formed on the conductor pads 14a' and 14b' in the openings 16a'and 16b' of different sizes formed in the solder resist layer 16'. When the top plating layers 28'and 32'are formed on the base plating layers 24'and 30' to form bumps 20' and 22'of different sizes, after the reflow of the top plating layers 28' and 32' It is possible that the bump heights are not the same.

The method for manufacturing a printed wiring board according to the present invention includes forming a base insulating layer, forming a conductor layer on the base insulating layer, and forming a solder resist layer on the base insulating layer and the conductor layer. Forming, forming a first opening in the solder resist layer that exposes a part of the conductor layer as a first conductor pad, and forming the solder resist layer in a diameter larger than that of the first opening. To form a second opening that exposes another part of the conductor layer as a second conductor pad, to form a first bump on the first conductor pad, and to form the second bump. Forming a second bump having a diameter smaller than that of the first bump on the conductor pad of the above, and forming the first bump includes a first base in the first opening. The second bump includes forming a plating layer, forming a first top plating layer on the first base plating layer, and reflowing the first top plating layer. To form the second base plating layer in the second opening, and to form the second base plating layer on the second base plating layer and above the uppermost position of the upper surface of the first top plating layer. It includes forming a second top plating layer having an upper surface and reflowing the second top plating layer.

Further, the printed wiring board according to the present invention is a printed wiring board, which is formed on a base insulating layer, a conductor layer formed on the base insulating layer, and on the base insulating layer and the conductor layer. In addition, a part of the conductor layer is exposed as a first conductor pad, and another part of the conductor layer having a diameter smaller than that of the first opening is exposed as a second conductor pad. A solder resist layer having a second opening, a first bump formed on the first conductor pad, and a second bump formed on the second conductor pad and having a diameter smaller than that of the first bump. The first bump comprises a first base plating layer formed in the first opening and a first top plating layer formed on the first base plating layer. The second bump comprises a second base plating layer formed in the second opening and a second top plating layer formed on the second base plating layer. The lowest position of the first bump is lower than the lowest position of the second bump, and the uppermost position of the first bump is substantially the same as the uppermost position of the second bump.

It is sectional drawing which shows the printed wiring board produced by the manufacturing method of one Embodiment of this invention. It is sectional drawing which shows the modification of the printed wiring board produced by the manufacturing method of one Embodiment of this invention. It is sectional drawing which shows the modification of the printed wiring board produced by the manufacturing method of one Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the printed wiring board of one Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the printed wiring board of one Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the printed wiring board of one Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the printed wiring board of one Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the printed wiring board of one Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the printed wiring board of one Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the printed wiring board of one Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the printed wiring board of one Embodiment of this invention. (A) and (b) are sectional views which show one step which is characteristic of the manufacturing method of the printed wiring board of one Embodiment of this invention, respectively. (A) to (g) are sectional views which show each process of the manufacturing method of the printed wiring board of one Embodiment of this invention, respectively. (A) to (h) are sectional views which show each process of the manufacturing method of the printed wiring board of one Embodiment of this invention, respectively. It is sectional drawing for demonstrating how the bump heights are not uniform in the printed wiring board according to the prior art.

<About the printed wiring board manufactured by the method for manufacturing the printed wiring board of the present invention>
An embodiment of the method for manufacturing a printed wiring board of the present invention will be described with reference to the drawings. FIG. 1 shows a part of the printed wiring board 10 manufactured by the manufacturing method of the embodiment in an enlarged manner. The printed wiring board 10 may be a board with a core formed by alternately laminating conductor layers and resin insulating layers having a predetermined circuit pattern on one side or both sides of a core board (not shown). When the conductor layers are formed on both sides of the core substrate, the conductor layers facing each other via the core substrate may be connected to each other via a through-hole conductor (not shown). Alternatively, the printed wiring board 10 may be a coreless substrate obtained by alternately laminating conductor layers and resin insulating layers on a support plate (not shown) instead of the core substrate, and then removing the support plate. .. In any case, as shown in FIG. 1, the printed wiring board 10 is formed on the base insulating layer 12 and the base insulating layer 12, which are arranged on the outermost side of at least one resin insulating layer. A conductor layer 14 having a predetermined circuit pattern, and a solder resist layer 16 formed on the base insulating layer 12 and the conductor layer 14 are provided. In many cases, a plurality of other conductor layers and a resin insulating layer are alternately provided in the lower layer of the base insulating layer 12, but they are omitted in the drawing. However, the printed wiring board 10 may be composed of one base insulating layer 12 and one conductor layer 14.

The base insulating layer 12 can be made of, for example, a resin composition containing an inorganic filler such as silica or alumina and an epoxy resin. The conductor layer 14 is formed of a conductive metal, for example, a metal containing copper as a main component.

The solder resist layer 16 has a first opening 16a that exposes a part of the conductor layer 14 as a first conductor pad 14a, and a second portion of the conductor layer 14 that is smaller in diameter than the first opening 16a. It has a second opening 16b to be exposed as the conductor pad 14b of the above. The aspect ratio of the first opening 16a, that is, the ratio of the depth to the diameter of the bottom can be 0.5 or less. The aspect ratio of the second opening 16b, that is, the ratio of the depth to the diameter of the bottom can be 0.6 or more.

The base layer 18 may be formed on the first and second conductor pads 14a and 14b, respectively. Examples of the base layer 18 include a nickel layer formed on the surfaces of the first and second conductor pads 14a and 14b, a palladium layer formed on the nickel layer, and a gold layer formed on the palladium layer. Can be done. In addition, a nickel layer and a gold layer formed on the nickel layer can be exemplified. The base layer 18 does not have to be formed.

The printed wiring board 10 is further formed on the first conductor pad 14a with the first bump 20 formed via the base layer 18 and on the second conductor pad 14b with the base layer 18 interposed therebetween. It is provided with a second bump 22 having a diameter smaller than that of the bump 20 of the above. When the base layer 18 is not formed, the first and second bumps 20 and 22 can be formed directly on the first and second conductor pads 14a and 14b. The first bump 20 can be used for connection with a power supply or a ground wire. The second bump 22 having a diameter smaller than that of the first bump 20 can be used for connection with the signal line.

The first bump 20 is formed on the first base plating layer 24 via a first base plating layer 24 formed in the first opening 16a and an intermediate layer 26 containing, for example, nickel as a main component on the first base plating layer 24. It also has a first top plating layer 28. The thickness of the intermediate layer 26 is preferably 7 μm or less. The intermediate layer 26 does not have to be formed. When the intermediate layer 26 is not formed, the first top plating layer 28 can be formed directly on the first base plating layer 24.

The first base plating layer 24 is formed of a conductive metal, preferably a metal containing copper as a main component. The first base plating layer 24 is preferably formed to a height exceeding the surface of the solder resist layer 16 (the surface opposite to the base insulating layer 12). As a result, the first bump 20 is stably held in the first opening 16a. The thickness B1 of the first base plating layer 24 from the surface of the solder resist layer 16 is preferably in the range of 3 μm to 20 μm. The first base plating layer 24 has a first recess 24a in the central portion of the upper surface. That is, the central portion of the upper surface of the first base plating layer 24 is formed at a position lower than the outer peripheral portion of the upper surface. The depth D1 of the first recess 24a, that is, the distance from the highest position of the outer peripheral portion of the upper surface of the first base plating layer 24 to the bottom position of the recess is 20 μm or less. By reducing the depth D1 of the first recess 24a, when the first top plating layer 28 is formed on the first base plating layer 24 with the intermediate layer 26 interposed therebetween, the first Gas accumulation in the recess 24a is suppressed. As a result, the generation of voids in the first top plating layer 28 is reduced. The depth D1 of the first recess 24a is preferably 15 μm or less, more preferably 10 μm or less.

The first top plating layer 28 has a melting point lower than that of the first base plating layer 24 and is melted by a reflow treatment and shaped into a substantially hemispherical shape as shown in FIG. 1, for example, a metal containing tin as a main component. Consists of. Thickness of the first top plating layer 28 (vertical distance from the lower end of the first top plating layer 28 to the top of the first top plating layer on the outer peripheral surface of the first bump 20) A1 is 5 μm to 45 μm. It is preferably in the range. By setting the thickness A1 of the first top plating layer 28 to this range, the first bump 20 and the connection pad (not shown) of an electronic component such as a semiconductor chip or memory mounted on the printed wiring board 10 can be connected to each other. Good connection reliability can be obtained between them.

The second bump 22 is formed on the second base plating layer 30 via a second base plating layer 30 formed in the second opening 16b and an intermediate layer 26 containing, for example, nickel as a main component on the second base plating layer 30. It also has a second top plating layer 32. The thickness of the intermediate layer 26 is preferably 7 μm or less. The intermediate layer 26 does not have to be formed. When the intermediate layer 26 is not formed, the second top plating layer 32 can be formed directly on the second base plating layer 30.

The second base plating layer 30 is formed of a conductive metal, preferably a metal containing copper as a main component. The second base plating layer 30 is preferably formed to a height exceeding the surface of the solder resist layer 16 (the surface opposite to the base insulating layer 12). As a result, the second bump 22 is stably held in the second opening 16b. The thickness B2 of the second base plating layer 30 from the surface of the solder resist layer 16 is preferably in the range of 3 μm to 20 μm. The second base plating layer 30 has a second recess 30a in the central portion of the upper surface. That is, the central portion of the upper surface of the second base plating layer 30 is formed at a position lower than the outer peripheral portion of the upper surface. The depth D2 of the second recess 30a, that is, the distance from the highest position of the outer peripheral portion of the upper surface of the second base plating layer 30 to the bottom position of the second recess 30a is smaller than the depth D1 of the first recess 24a. .. In the second bump 22 having a diameter smaller than that of the first bump 20, the depth D2 of the second recess 30a is made smaller than the depth D1 of the first recess 24a, so that the depth D2 is on the second base plating layer 30. In some cases, when the second top plating layer 32 is formed via the intermediate layer 26, gas accumulation in the second recess 30a is suppressed. As a result, the generation of voids in the second top plating layer 32 is reduced.

The second top plating layer 32 has a melting point lower than that of the second base plating layer 30, and is melted by a reflow treatment and shaped into a substantially hemispherical shape as shown in FIG. 1, for example, a metal containing tin as a main component. Consists of. Thickness of the second top plating layer 32 (vertical distance from the lower end of the second top plating layer 32 to the top of the second top plating layer 32 on the outer peripheral surface of the second bump 22) A2 is 5 μm to 45 μm. It is preferable that the range is. By setting the thickness A2 of the second top plating layer 32 in this range, the second bump 22 and the connection pad (not shown) of electronic components such as a semiconductor chip and memory mounted on the printed wiring board 10 can be connected to each other. Good connection reliability can be obtained between them.

In the printed wiring board according to the present invention, the lowest position of the first bump 20 is lower than the lowest position of the second bump 22, and the uppermost position of the first bump 20 is the highest position of the second bump 22. It is almost the same.

FIG. 2 shows a modified example of the printed wiring board 10 shown in FIG. Elements or parts similar to those described with reference to FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted as appropriate. In the printed wiring board 10 according to this modification, the upper surface of the second base plating layer 30 of the second bump 22 is formed flat. Other configurations are the same as those of the printed wiring board 10 of FIG. In addition, "flat" means that the upper surface of the second base plating layer 30 is substantially parallel to the main surface of the printed wiring board 10, and minute irregularities that may be generated by the plating treatment may be present. .. By flattening the upper surface of the second base plating layer 30, the void generation rate in the second bump 22 is the same as that of the second bump 22 shown in FIG. 1, which has the second recess 30a in the central portion of the upper surface. It is reduced in comparison.

FIG. 3 shows a modified example of the printed wiring board 10 shown in FIG. Elements or parts similar to those described with reference to FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted as appropriate. In the printed wiring board 10 according to this modification, a raised portion 30b is formed at the center of the upper surface of the second base plating layer 30 of the second bump 22. That is, the central portion of the upper surface of the second base plating layer 30 is located higher than the outer peripheral portion of the upper surface. Other configurations are the same as those of the printed wiring board 10 of FIG. By forming the raised portion 30b in the central portion of the upper surface of the second base plating layer 30, the void generation rate in the second bump 22 is such that the upper surface is flat or the upper surface has the second recess 30a in the central portion of the upper surface. And it is reduced as compared with the second bump 22 shown in FIG.

<About the manufacturing method of the printed wiring board of the present invention>
Hereinafter, a method for manufacturing the printed wiring board 10 shown in FIG. 1 according to the present invention will be described with reference to FIGS. 4A to 4H. The printed wiring board 10 of the modified example shown in FIGS. 2 to 3 is also manufactured by the same manufacturing method.

FIG. 4A shows an intermediate in which a conductor layer 14 and a solder resist layer 16 having a predetermined circuit pattern are formed on a base insulating layer 12 by a known method. In many cases, a plurality of other conductor layers and a resin insulating layer are alternately formed in the lower layer of the base insulating layer 12, but they are omitted in the drawing. The plurality of conductor layers and the resin insulating layer can be laminated on the core substrate or on a support plate that can be removed later. However, the printed wiring board 10 may be composed of one resin insulating layer as the base insulating layer 12 and one conductor layer 14, and in this case, the resin insulating layer corresponds to the base insulating layer 12. For the base insulating layer 12, a build-up insulating resin film containing an inorganic filler such as silica or alumina and an epoxy resin can be used. The solder resist layer 16 has a first opening 16a that exposes a part of the conductor layer 14 as a first conductor pad 14a by, for example, a carbon dioxide gas laser or a UV-YAG laser, and another part of the conductor layer 14. A second opening 16b to be exposed as the second conductor pad 14b is formed. The aspect ratio of the first opening 16a is preferably 0.5 or less, and the aspect ratio of the second opening 16b is preferably 0.6 or more. On the first and second conductor pads 14a and 14b, for example, a nickel layer, a palladium layer, and a gold layer are laminated in this order by plating to form a base layer 18. The base layer 18 does not have to be formed.

As shown in FIG. 4B, for example, an electroless plating treatment such as an electroless copper plating treatment is performed, and the surface of the intermediate body (the surface of the solder resist layer 16 and the side surfaces of the first and second openings 16a and 16b). A seed layer 34 is formed on the top and on the base layer 18 (on the conductor pads 14a and 14b when the base layer 18 is not formed).

As shown in FIG. 4C, a plating resist 36 having a predetermined pattern having openings 36a is formed on the seed layer 34 at the planned formation sites of the first and second bumps 20 and 22 (FIG. 1).

As shown in FIG. 4D, the electrolytic plating treatment is performed, and the portion of the seed layer 34 exposed from the plating resist 36 is subjected to, for example, a first base plating layer 24 containing copper as a main component and a second base plating. Layer 30 is formed. At this time, when the printed wiring board 10 shown in FIGS. 1 to 3 is manufactured, a first recess 24a having a depth of 20 μm or less, preferably 15 μm or less, more preferably 10 μm or less is formed in the central portion of the upper surface. As described above, the plating thickness of the first base plating layer 24 is adjusted. When the printed wiring board 10 shown in FIG. 2 is manufactured, the thickness of the second base plating layer 30 is adjusted so that the upper surface of the second base plating layer 30 is flat. When the printed wiring board 10 shown in FIG. 3 is manufactured, the plating thickness of the second base plating layer 30 is adjusted so that the raised portion 30b is formed in the central portion of the upper surface of the second base plating layer 30. To do.

When forming the first and second base plating layers 24 and 30, the thickness of the first base plating layer 24 and the thickness of the second base plating layer 30 from the surface of the solder resist layer 16 are 3 μm. It is preferable to adjust the plating thickness of the first and second base plating layers 24 and 30 so as to be within the range of about 20 μm.

As shown in FIG. 4E, for example, an electrolytic plating treatment is performed, and an intermediate layer 26 containing, for example, nickel as a main component is formed on the first and second base plating layers 24 and 30. The thickness of the intermediate layer 26 is preferably 7 μm or less. The intermediate layer 26 does not have to be formed.

As shown in FIG. 4F, the electrolytic plating treatment is performed to form the first and second top plating layers 28 and 32 on the first and second base plating layers 24 and 30 with the intermediate layer 26 interposed therebetween. Will be done. The first and second top plating layers 28 and 32 are mainly composed of a metal having a lower melting point than the first and second base plating layers 24 and 30 and being melted by a reflow treatment and shaped into a substantially hemispherical shape, for example, tin. It consists of the metal as a component. The thickness of the first and second top plating layers 28 and 32 is preferably in the range of 5 μm to 45 μm. The upper surface of the first base plating layer 24 is formed flat, or the first recess 24a having a depth D1 of 20 μm or less is formed in the central portion of the upper surface, whereby the first top plating layer 28 is formed. At the time of formation, the gas accumulation in the first recess 24a is suppressed. As a result, the generation of voids in the first top plating layer 28 is reduced. Further, the upper surface of the second base plating layer 30 is formed flat, a second recess 30a shallower than the first recess 24a is formed in the central portion of the upper surface, or a raised portion 30b is formed in the central portion of the upper surface. When the second top plating layer 32 is formed, gas accumulation in the vicinity of the second base plating layer 30 is suppressed. As a result, the generation of voids in the second top plating layer 32 is reduced.

In the process shown in FIG. 4F, the feature of the present invention is that the uppermost position of the upper surface of the second top plating layer 32 is set higher than the uppermost position of the upper surface of the first top plating layer 28. By forming the second top plating layer 32 having an upper surface above the uppermost position of the upper surface of the first top plating layer 28 in this way, the first top plating layer 28 and the second top are formed in the next step. By reflowing the plating layer 32, as shown in FIG. 4H, the uppermost position of the upper surface of the first top plating layer 28 after the reflow and the uppermost position of the upper surface of the second top plating layer 32 are at the same height. become. As a result, the first bump 20 and the second bump 22 having the same bump height can be formed.

As shown in FIG. 4G, the plating resist 36 is peeled off. Further, the portion of the seed layer 34 exposed by removing the plating resist 36 is removed by etching.

As shown in FIG. 4H, a reflow process is performed to shape the first top plating layer 28 and the second top plating layer 32 into a substantially hemispherical shape. When the intermediate layer 26 is formed by the reflow treatment, the copper layer, the copper / nickel alloy layer, the nickel layer, the nickel / tin alloy layer, and tin are formed from the side closer to the first and second conductor pads 14a and 14b. A first bump 20 and a second bump 22 composed of layers are formed. When the intermediate layer 26 is not formed, the first bump 20 and the second bump composed of the copper layer, the copper / tin alloy layer, and the tin layer are formed from the side closer to the first and second conductor pads 14a and 14b. 22 is formed.

In the present invention, the second top plating layer 32 having an upper surface above the uppermost position of the upper surface of the first top plating layer 28 is formed, and contributes to control for making the bump height after reflow the same. The following factors can be considered as factors. The main factors are the thickness of the first base plating layer 24 and the second base plating layer 30, the thickness of the intermediate layer 26, the bump diameters of the first bump 20 and the second bump 22, and the first before reflow. The thickness of the top plating layer 28 and the second top plating layer 30 of 1 and the depth of the first recess 24a and the second recess 30a before reflow can be considered. As an example, in FIGS. 5A and 5B, the thickness of the second base plating layer 30 is made thicker than the thickness of the first base plating layer 24, and the upper surface of the first top plating layer 28 is formed thicker. An example of forming a second top plating layer 32 having an upper surface above the uppermost position is shown. When other factors are used for control, the present invention can be achieved by similarly controlling the thickness, diameter and depth of each factor.

6 (a) to 6 (b) show the manufacturing process of the embodiment in which the thickness of the second base plating layer 30 is thicker than the thickness of the first base plating layer 24 shown in FIGS. 5 (a) and 5 (b). This will be described with reference to g) and FIGS. 7 (a) to 7 (h). In the embodiments shown in FIGS. 6 (a) to 6 (g) and 7 (a) to 7 (h), the same elements or parts as those described with reference to the manufacturing processes of FIGS. 4A to 4H may be used. The same reference numerals are given, and detailed description thereof will be omitted as appropriate.

In the embodiments shown in FIGS. 6 (a) to 6 (g), first, as shown in FIG. 6 (a), the conductor layer 14 and the solder resist layer 16 are formed on the base insulating layer 12 by using a known method. The formed intermediate is prepared. The solder resist layer 16 is formed with a first opening 16a in which a part of the conductor layer 14 is exposed as a first conductor pad 14a. Next, as shown in FIG. 6B, the first conductor pad 14a exposed by the first opening 16a is etched to form the recess 41.

Next, as shown in FIG. 6 (c), the solder resist layer 16 is exposed to a second portion of the conductor layer 14, which is different from the first conductor pad 14a, as a second conductor pad 14b. The opening 16b is formed.

Next, as shown in FIG. 6D, on the surface of the intermediate (the surface of the solder resist layer 16 and the sides of the first and second openings 16a, 16b, the conductor pads 14a (recesses 41), 14b). The seed layer 34 is formed on the surface. Then, a plating resist 36 having a predetermined pattern having an opening 36a is formed on the seed layer 34 at the planned formation sites of the first and second bumps 20 and 22 (FIG. 1). Next, as shown in FIG. 6E, the first base plating layer 24 and the second base plating layer 30 are formed on the portion of the seed layer 34 exposed from the plating resist 36. At this time, since the recess 41 is present in the portion where the first base plating layer 24 is formed, the height of the second base plating layer 30 is higher than the height of the first base plating layer 24.

Next, as shown in FIG. 6 (f), the intermediate layer 26 is formed on the first and second base plating layers 24 and 30. Then, the first and second top plating layers 28 and 32 are formed on the first and second base plating layers 24 and 30 with the intermediate layer 26 interposed therebetween. Next, as shown in FIG. 6 (g), the plating resist 36 is peeled off. Further, the portion of the seed layer 34 exposed by removing the plating resist 36 is removed by etching. After that, a reflow treatment is performed, and the first top plating layer 28 and the second top plating layer 32 are shaped into a substantially hemispherical shape.

In the embodiments shown in FIGS. 7 (a) to 7 (h), first, as shown in FIG. 7 (a), the conductor layer 14 and the solder resist layer 16 are formed on the base insulating layer 12 by using a known method. The formed intermediate is prepared. The solder resist layer 16 has a first opening 16a that exposes a part of the conductor layer 14 as a first conductor pad 14a, and a second opening 16a that exposes another part of the conductor layer 14 as a second conductor pad 14b. The opening 16b and the like are formed.

Next, as shown in FIG. 7B, the second opening 16b is closed with the dry film resist layer 42 to protect the second opening 16b. Next, as shown in FIG. 7C, the first conductor pad 14a exposed by the first opening 16a is etched to form the recess 41. Next, as shown in FIG. 7 (d), the dry film resist layer 42 is removed, and the surface of the intermediate (the surface of the solder resist layer 16 and the side surfaces of the first and second openings 16a and 16b, the conductor pad. A seed layer 34 is formed on 14a (dents 41) and 14b).

Next, as shown in FIG. 7E, a plating resist 36 having a predetermined pattern having openings 36a at the planned formation sites of the first and second bumps 20 and 22 (FIG. 1) is formed on the seed layer 34. It is formed. Next, as shown in FIG. 7 (f), the first base plating layer 24 and the second base plating layer 30 are formed on the portion of the seed layer 34 exposed from the plating resist 36. At this time, since the recess 41 is present in the portion where the first base plating layer 24 is formed, the height of the second base plating layer 30 is higher than the height of the first base plating layer 24.

Next, as shown in FIG. 7 (g), the intermediate layer 26 is formed on the first and second base plating layers 24 and 30. Then, the first and second top plating layers 28 and 32 are formed on the first and second base plating layers 24 and 30 with the intermediate layer 26 interposed therebetween. Next, as shown in FIG. 7 (h), the plating resist 36 is peeled off. Further, the portion of the seed layer 34 exposed by removing the plating resist 36 is removed by etching. After that, a reflow treatment is performed, and the first top plating layer 28 and the second top plating layer 32 are shaped into a substantially hemispherical shape.

10 Printed wiring board 12 Base insulating layer 14 Conductor layer 14a First conductor pad 14b Second conductor pad 16 Solder resist layer 16a First opening 16b Second opening 18 Base layer 20 First bump 22 Second bump 24 1st base plating layer 24a 1st depression 26 Intermediate layer 28 1st top plating layer 30 2nd base plating layer 30a 2nd depression 30b Raised part 32 2nd top plating layer 34 Seed layer 36 Plating resist 41 Recess 42 Dry film resist layer

Claims (20)

It is a manufacturing method of printed wiring boards.
Forming a base insulating layer and
Forming a conductor layer on the base insulating layer and
Forming a solder resist layer on the base insulating layer and the conductor layer,
To form a first opening in the solder resist layer that exposes a part of the conductor layer as a first conductor pad.
To form a second opening in the solder resist layer, which has a diameter smaller than that of the first opening and exposes another part of the conductor layer as a second conductor pad.
Forming a first bump on the first conductor pad and
Including forming a second bump having a diameter smaller than that of the first bump on the second conductor pad.
Forming the first bump means forming a first base plating layer in the first opening and forming a first top plating layer on the first base plating layer. , Including reflowing the first top plating layer,
Forming the second bump means forming a second base plating layer in the second opening, and forming the second base plating layer on the second base plating layer and on the upper surface of the first top plating layer. It includes forming a second top plating layer having an upper surface above the top position and reflowing the second top plating layer. The method for manufacturing a printed wiring board according to claim 1, wherein the thickness of the first top plating layer and the second top plating layer is in the range of 5 μm to 45 μm. The method for manufacturing a printed wiring board according to claim 1, wherein the first base plating layer and the second base plating layer are formed from a metal containing copper as a main component, respectively. The method for manufacturing a printed wiring board according to claim 1, wherein the first top plating layer and the second top plating layer are formed from a metal containing tin as a main component, respectively. The method for manufacturing a printed wiring board according to claim 1, wherein the first base plating layer and the first conductor pad, and the second base plating layer and the first conductor pad layer. It further includes forming a base layer composed of a nickel layer, a palladium layer and a gold layer, respectively. The method for manufacturing a printed wiring board according to claim 1, wherein the first base plating layer and the first top plating layer, and the second base plating layer and the second top plating layer are used. It further includes forming intermediate layers each containing nickel as a main component between the layers. The method for manufacturing a printed wiring board according to claim 6, wherein the thickness of the intermediate layer is 7 μm or less. The method for manufacturing a printed wiring board according to claim 1, wherein the first and second base plating layers are formed to a height exceeding the surface of the solder resist layer, and the first from the surface of the solder resist layer. The thickness of the base plating layer 1 and the thickness of the second base plating layer are each within the range of 3 μm to 20 μm. The method for manufacturing a printed wiring board according to claim 1, wherein the aspect ratio of the first opening is 0.5 or less, and the aspect ratio of the second opening is 0.6 or more. In the method for manufacturing a printed wiring board according to claim 1, forming the first base plating layer has a flat upper surface or a first recess having a depth of 20 μm or less in the central portion of the upper surface. The formation of the second base plating layer further includes forming a first base plating layer having a flat upper surface, having a raised portion in the central portion of the upper surface, or forming the central portion of the upper surface. It further comprises forming a second base plating layer having a second recess that is shallower than the first recess. It is a printed wiring board
With the base insulation layer,
The conductor layer formed on the base insulating layer and
A first opening formed on the base insulating layer and the conductor layer and exposing a part of the conductor layer as a first conductor pad, and the conductor layer having a diameter smaller than that of the first opening. A solder resist layer with a second opening that exposes the other part as a second conductor pad,
With the first bump formed on the first conductor pad,
A second bump formed on the second conductor pad and having a diameter smaller than that of the first bump,
With
The first bump has a first base plating layer formed in the first opening and a first top plating layer formed on the first base plating layer.
The second bump has a second base plating layer formed in the second opening and a second top plating layer formed on the second base plating layer.
The lowest position of the first bump is lower than the lowest position of the second bump, and the uppermost position of the first bump is substantially the same as the uppermost position of the second bump. The printed wiring board according to claim 11, wherein the thickness of the first top plating layer and the second top plating layer is 5 μm to 45 μm. The printed wiring board according to claim 11, wherein the first base plating layer and the second base plating layer are each formed of a metal containing copper as a main component. The printed wiring board according to claim 11, wherein the first top plating layer and the second top plating layer are each formed of a metal containing tin as a main component. The printed wiring board according to claim 11, between the first base plating layer and the first conductor pad, and between the second base plating layer and the first conductor pad layer. Each has a base layer composed of a nickel layer, a palladium layer, and a gold layer. The printed wiring board according to claim 11, wherein the first base plating layer and the first top plating layer, and the second base plating layer and the second top plating layer are used. It has an intermediate layer containing nickel as a main component between them. The printed wiring board according to claim 16, wherein the thickness of the intermediate layer is 7 μm or less. The printed wiring board according to claim 11, wherein the first and second base plating layers are formed to a height exceeding the surface of the solder resist layer, and the first base from the surface of the solder resist layer. The thickness of the plating layer and the thickness of the second base plating layer are each in the range of 3 μm to 20 μm. The printed wiring board according to claim 11, wherein the aspect ratio of the first opening is 0.5 or less, and the aspect ratio of the second opening is 0.6 or more. The printed wiring board according to claim 11, wherein the first base plating layer has a flat upper surface or a first recess having a depth of 20 μm or less in a central portion of the upper surface, and the second base. The plating layer has a flat upper surface, has a raised portion in the central portion of the upper surface, or has a second recess in the central portion of the upper surface, which is shallower than the first recess.

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