JP7257273B2 - Printed wiring board and manufacturing method thereof - Google Patents

Description

The present invention relates to a printed wiring board having plated bumps and a manufacturing method thereof.

Patent Literature 1 discloses bump formation using a plating method.

JP 2010-129996 A

However, as shown in FIGS. 5 and 6, base plating layers 24' and 30' are formed on conductor pads 14a' and 14b' in openings 16a' and 16b' of different sizes formed in solder resist layer 16'. are formed, and top plating layers 28' and 32' are formed on the base plating layers 24' and 30' to form large diameter bumps 20' and small diameter bumps 22' having different sizes. In the large-diameter bumps 20' and the large-diameter bumps 20' in the outer peripheral portion, the heights of the bumps are aligned between the bump height BH3 in the central portion and the bump height BH1 in the outer peripheral portion after the reflow of the top plating layer 28'. sometimes not.

A printed wiring board according to the present invention is a printed wiring board comprising a base insulating layer, a conductor layer formed on the base insulating layer, formed on the base insulating layer and the conductor layer, and a first opening exposing a portion of the conductor layer as a first conductor pad; and a second opening having a smaller diameter than the first opening exposing another portion of the conductor layer as a second conductor pad. a solder resist layer having an opening of , a first bump formed on the first conductor pad, and a second bump formed on the second conductor pad and having a smaller diameter than the first bump and the first bump includes a first base plating layer formed in the first opening and a first top plating layer formed on the first base plating layer. and the second bump has a second base plating layer formed in the second opening and a second top plating layer formed on the second base plating layer. In the plurality of first bumps, the diameter of the first bumps increases toward the center of the printed wiring board, and the highest positions of the plurality of first bumps are substantially the same.

Further, a method for manufacturing a printed wiring board of the present invention is a method for manufacturing a printed wiring board, comprising: forming a base insulating layer; forming a conductor layer on the base insulating layer; forming a solder resist layer on the top and the conductor layer; forming a first opening in the solder resist layer to expose a part of the conductor layer as a first conductor pad; forming a second opening in the layer having a smaller diameter than the first opening and exposing another part of the conductor layer as a second conductor pad; and forming a second bump having a smaller diameter than the first bump on the second conductor pad, wherein forming the first bump comprises: forming a first base plating layer in the first opening; forming a first top plating layer on the first base plating layer; reflowing the first top plating layer; increasing the diameter of the plurality of first bumps toward the center of the printed wiring board by increasing the diameter of the plurality of first base plating layers toward the center of the printed wiring board; forming the second bump includes forming a second base plating layer within the second opening; and forming the first top plating layer on the second base plating layer. forming a second top plating layer having a top surface that is above the top of the top surface of the substrate; and reflowing the second top plating layer.

1 is a cross-sectional view showing a printed wiring board according to one embodiment of the present invention; FIG. FIG. 4 is a diagram for explaining the relationship between bump diameters in the printed wiring board of one embodiment of the present invention; FIG. 4 is a diagram for explaining zones of a printed wiring board in which bump diameters are changed in the printed wiring board according to one embodiment of the present invention; It is a sectional view showing a manufacturing method of a printed wired board of one embodiment of the present invention. It is a sectional view showing a manufacturing method of a printed wired board of one embodiment of the present invention. It is a sectional view showing a manufacturing method of a printed wired board of one embodiment of the present invention. It is a sectional view showing a manufacturing method of a printed wired board of one embodiment of the present invention. It is a sectional view showing a manufacturing method of a printed wired board of one embodiment of the present invention. It is a sectional view showing a manufacturing method of a printed wired board of one embodiment of the present invention. It is a sectional view showing a manufacturing method of a printed wired board of one embodiment of the present invention. It is a sectional view showing a manufacturing method of a printed wired board of one embodiment of the present invention. FIG. 2 is a cross-sectional view for explaining the structure of bumps in a printed wiring board according to the prior art; FIG. 10 is a cross-sectional view for explaining how the heights of large-diameter bumps are not uniform in a printed wiring board according to the prior art;

<About the printed wiring board of the present invention>
One embodiment of the printed wiring board of the present invention will be described with reference to the drawings. FIG. 1 shows an enlarged part of a printed wiring board 10 manufactured by the manufacturing method of the embodiment. Printed wiring board 10 may be a substrate with a core formed by alternately laminating conductor layers and resin insulation layers having predetermined circuit patterns on one or both sides of a core substrate (not shown). When conductor layers are formed on both sides of the core substrate, the conductor layers facing each other via the core substrate may be connected via through-hole conductors (not shown). Alternatively, printed wiring board 10 may be a coreless substrate obtained by alternately laminating conductor layers and resin insulating layers on a support plate (not shown) instead of the core substrate, and then removing the support plate. . In any case, as shown in FIG. 1, the printed wiring board 10 includes a base insulating layer 12 which is the outermost layer of at least one resin insulating layer, and a base insulating layer 12 formed on the base insulating layer 12. , a conductor layer 14 having a predetermined circuit pattern, and a solder resist layer 16 formed on the base insulating layer 12 and the conductor layer 14 . In many cases, a plurality of other conductor layers and resin insulation layers are alternately provided under the base insulation layer 12, but they are omitted in the drawing. However, the printed wiring board 10 may consist of one layer of the base insulating layer 12 and one layer of the conductor layer 14 .

The base insulating layer 12 can be made of, for example, a resin composition containing an inorganic filler such as silica or alumina and an epoxy resin. The conductor layer 14 is made of a conductive metal such as a metal containing copper as a main component.

The solder resist layer 16 includes first openings 16a that expose portions of the conductor layer 14 as first conductor pads 14a, and second openings 16a that are smaller in diameter than the first openings 16a and expose other portions of the conductor layer 14 as second openings 14a. and a second opening 16b exposed as a second contact pad 14b. The aspect ratio of the first opening 16a, ie, the ratio of the depth to the diameter of the bottom, can be 0.5 or less. The aspect ratio of the second opening 16b, that is, the ratio of the depth to the diameter of the bottom can be 0.6 or more.

Underlayers 18 may be formed on the first and second conductor pads 14a, 14b, respectively. Examples of the underlying layer 18 include a nickel layer formed on the surfaces of the first and second conductor pads 14a and 14b, a palladium layer formed on the nickel layer, and a gold layer formed on the palladium layer. can be done. In addition, a nickel layer and a gold layer formed on the nickel layer can be exemplified. The underlying layer 18 may not be formed.

The printed wiring board 10 further includes a first bump 20 formed on the first conductor pad 14a through the underlying layer 18 and a first bump 20 formed on the second conductor pad 14b through the underlying layer 18 to form the first bump 20 on the second conductor pad 14b. and a second bump 22 having a smaller diameter than the bump 20 of the first. If the underlying layer 18 is not formed, the first and second bumps 20, 22 can be formed directly on the first and second contact pads 14a, 14b. The first bump 20 can be used for connection to a power supply or ground line. A second bump 22 having a diameter smaller than that of the first bump 20 can be used for connection with a signal line.

The first bump 20 constituting the large-diameter bump in the printed wiring board 10 of the present invention includes a first base plating layer 24 formed in the first opening 16a and, for example, a and a first top plated layer 28 formed via an intermediate layer 26 containing nickel as a main component. The thickness of the intermediate layer 26 is preferably 7 μm or less. The intermediate layer 26 may not be formed. If the intermediate layer 26 is not formed, the first top plating layer 28 can be formed directly on the first base plating layer 24 .

The first base plating layer 24 is made of a conductive metal, preferably a copper-based metal. The first base plating layer 24 is formed up to a height exceeding the surface of the solder resist layer 16 (the surface opposite to the base insulating layer 12). Thereby, the first bump 20 is stably held in the first opening 16a. The thickness B1 of the first base plating layer 24 from the surface of the solder resist layer 16 is preferably within the range of 3 μm to 20 μm.

The first top plating layer 28 is a metal having a melting point lower than that of the first base plating layer 24 and melted by reflow treatment and shaped into a substantially hemispherical shape as shown in FIG. consists of The thickness of the first top plating layer 28 (vertical distance from the lower end of the first top plating layer 28 to the top of the first top plating layer on the outer peripheral surface of the first bump 20) A1 is 5 μm to 45 μm. A range is preferred. By setting the thickness A1 of the first top plating layer 28 within this range, the first bumps 20 and connection pads (not shown) of electronic components such as semiconductor chips and memories mounted on the printed wiring board 10 Good connection reliability can be obtained between

The second bumps 22 constituting the small-diameter bumps in the printed wiring board 10 of the present invention are composed of a second base plating layer 30 formed in the second opening 16b, and nickel, for example, on the second base plating layer 30. and a second top plated layer 32 formed via an intermediate layer 26 containing as a main component. The thickness of the intermediate layer 26 is preferably 7 μm or less. The intermediate layer 26 may not be formed. If the intermediate layer 26 is not formed, the second top plated layer 32 can be formed directly on the second base plated layer 30 .

The second base plating layer 30 is made of a conductive metal, preferably a copper-based metal. The second base plating layer 30 is preferably formed to a height exceeding the surface of the solder resist layer 16 (the surface opposite to the base insulating layer 12). Thereby, the second bump 22 is stably held in the second opening 16b. The thickness B2 of the second base plating layer 30 from the surface of the solder resist layer 16 is preferably within the range of 3 μm to 20 μm. The second base plating layer 30 has a second depression 30a in the central portion of its upper surface. That is, the central portion of the upper surface of the second base plating layer 30 is formed at a position lower than the peripheral portion of the upper surface.

The second top plating layer 32 is a metal that has a melting point lower than that of the second base plating layer 30 and can be melted by reflow processing and shaped into a substantially hemispherical shape as shown in FIG. consists of The thickness of the second top plating layer 32 (vertical distance from the lower end of the second top plating layer 32 to the top of the second top plating layer 32 on the outer peripheral surface of the second bump 22) A2 is 5 μm to 45 μm is preferably in the range of By setting the thickness A2 of the second top plating layer 32 within this range, the second bumps 22 and connection pads (not shown) of electronic components such as semiconductor chips and memories mounted on the printed wiring board 10 Good connection reliability can be obtained between

In the printed wiring board according to the present invention, in the plurality of first bumps 20 constituting the large-diameter bumps, the diameter of the first bumps 20 increases toward the center of the printed wiring board, and the diameter of the plurality of first bumps 20 increases toward the center of the printed wiring board. are substantially the same.

As an example of a specific mode, as shown in FIG. 2, before the reflow of the first top plating layer 28, the diameter of the first base plating layer 24 of the outer peripheral bump located on the outer periphery of the printed wiring board is Assuming that R1 is the diameter of the first base plating layer 24 of the center bump located in the center of the printed wiring board and R3 is the diameter of the first base plating layer 24, the diameter of the first bump 20 after the reflow of the first top plating layer 28 is: It becomes R1 at the outline portion bumps and R3 at the central portion bumps. The relationship between the peripheral bumps and the central bumps is defined as R3>R1. At this time, assuming that the diameter of the portion of the first base plating layer 24 in contact with the underlying layer 18 is R11, R11 is the same for the peripheral bumps and the central bumps, and the relationship between R1 and R3 is R3>R1> becomes R11. Further, if the bump height of the first bump 20 is BH1 for the peripheral bump and BH3 for the central bump, the relationship is approximately BH1=BH3.

As another example of a specific embodiment, as shown in FIG. 3, the printed wiring board 10 is divided into a central portion Z3, an intermediate portion Z2, and an outer peripheral portion Z1, and the diameter of the first bumps 20 present in the central portion Z3 is When R3 is the diameter of the first bump 20 present in the middle portion Z2 and R3 is the diameter of the first bump 20 present in the outer peripheral portion Z1, R3>R2>R1 can be established.

<About the method for manufacturing the printed wiring board of the present invention>
A method of manufacturing printed wiring board 10 shown in FIG. 1 according to the present invention will be described below with reference to FIGS. 4A to 4H.

FIG. 4A shows an intermediate body in which a conductor layer 14 having a predetermined circuit pattern and a solder resist layer 16 are formed on a base insulating layer 12 using a known method. In many cases, a plurality of other conductor layers and resin insulation layers are alternately formed under the base insulation layer 12, but they are omitted in the drawing. A plurality of conductor layers and resin insulation layers can be laminated on a core substrate or a support plate that can be removed later. However, printed wiring board 10 may be composed of one resin insulation layer as base insulation layer 12 and one conductor layer 14 , in which case this resin insulation layer corresponds to base insulation layer 12 . A build-up insulating resin film containing an inorganic filler such as silica or alumina and an epoxy resin can be used for the base insulating layer 12 . The solder resist layer 16 is formed with first openings 16a for exposing part of the conductor layer 14 as first conductor pads 14a and other parts of the conductor layer 14 by, for example, a carbon dioxide laser or UV-YAG laser. A second opening 16b is formed exposing two contact pads 14b. Preferably, the aspect ratio of the first opening 16a is 0.5 or less, and the aspect ratio of the second opening 16b is 0.6 or more. A base layer 18 is formed on the first and second conductor pads 14a, 14b by plating, for example, a nickel layer, a palladium layer, and a gold layer in this order. The underlying layer 18 may not be formed.

As shown in FIG. 4B, for example, electroless plating such as electroless copper plating is performed, and the surface of the intermediate (the surface of the solder resist layer 16 and the side surfaces of the first and second openings 16a and 16b) is A seed layer 34 is formed on top and on the underlayer 18 (on the contact pads 14a, 14b if the underlayer 18 is not formed).

As shown in FIG. 4C, a plating resist 36 having a predetermined pattern is formed on the seed layer 34 and has openings 36a at the positions where the first and second bumps 20 and 22 (FIG. 1) are to be formed.

As shown in FIG. 4D, an electroplating process is performed to form a first base plating layer 24 and a second base plating layer 24 mainly composed of copper, for example, on the seed layer 34 exposed from the plating resist 36 . A layer 30 is formed. In the present invention, at this stage, by increasing the diameter of the plurality of first base plating layers 24 toward the center of the printed wiring board, the diameter of the first bumps 20 in the final shape is made toward the center of the printed wiring board. You can grow towards it.

Further, when forming the first and second base plating layers 24 and 30, the thickness of the first base plating layer 24 and the thickness of the second base plating layer 30 from the surface of the solder resist layer 16 are 3 μm. It is preferable to adjust the plating thickness of the first and second base plating layers 24, 30 so as to be within the range of 20 μm.

As shown in FIG. 4E, for example, an electrolytic plating process is performed to form an intermediate layer 26 containing, for example, nickel as a main component on the first and second base plating layers 24, 30. As shown in FIG. The thickness of the intermediate layer 26 is preferably 7 μm or less. The intermediate layer 26 may not be formed.

As shown in FIG. 4F, an electrolytic plating process is performed to form first and second top plating layers 28, 32 on the first and second base plating layers 24, 30 with an intermediate layer 26 therebetween. be done. The first and second top plating layers 28, 32 are mainly made of a metal, such as tin, which has a melting point lower than that of the first and second base plating layers 24, 30 and can be melted and formed into a substantially hemispherical shape by reflow processing. Consists of metal as a component. The thickness of the first and second top plating layers 28, 32 is preferably in the range of 5 μm to 45 μm.

As shown in FIG. 4G, the plating resist 36 is removed. Also, the portion of the seed layer 34 exposed by removing the plating resist 36 is removed by etching.

As shown in FIG. 4H, a reflow process is performed to shape the first top plating layer 28 and the second top plating layer 32 into substantially hemispherical shapes. A first bump 20 and a second bump 20 made of a copper layer, a copper/nickel alloy layer, a nickel layer, a nickel/tin alloy layer and a tin layer are formed by reflow treatment from the side closer to the first and second conductor pads 14a and 14b. A bump 22 is formed. If the intermediate layer 26 is not formed, the first and second bumps 20 and 20 are formed from a copper layer, a copper/tin alloy layer, and a tin layer from the side closer to the first and second conductor pads 14a and 14b. 22 are formed.

REFERENCE SIGNS LIST 10 printed wiring board 12 base insulating layer 14 conductor layer 14a first conductor pad 14b second conductor pad 16 solder resist layer 16a first opening 16b second opening 18 base layer 20 first bump 22 second bump 24 first base plating layer 24a first depression 26 intermediate layer 28 first top plating layer 30 second base plating layer 30a second depression 30b raised portion 32 second top plating layer 34 seed layer 36 plating resist

Claims (20)

A printed wiring board,
a base insulating layer;
a conductor layer formed on the base insulating layer;
a first opening formed on the base insulating layer and the conductor layer and exposing a portion of the conductor layer as a first conductor pad; and the conductor layer having a smaller diameter than the first opening. A solder resist layer having a second opening that exposes another part of as a second contact pad;
a first bump formed on the first conductor pad;
a second bump formed on the second conductor pad and having a smaller diameter than the first bump;
with
The first bump has a first base plating layer formed in the first opening and a first top plating layer formed on the first base plating layer,
The second bump has a second base plating layer formed in the second opening and a second top plating layer formed on the second base plating layer,
Among the plurality of first bumps, the diameter of the first bumps increases toward the center of the printed wiring board, and the highest positions of the plurality of first bumps are substantially the same. 2. The printed wiring board according to claim 1, wherein the printed wiring board is divided into a central portion, an intermediate portion, and an outer peripheral portion, the diameter of the first bump present in the central portion is R3, and the diameter of the first bump present in the intermediate portion is R3. When the diameter of the first bump is R2, and the diameter of the first bump present in the outer peripheral portion is R1, R3>R2>R1. 2. The printed wiring board according to claim 1, wherein the thickness of said first top plating layer and said second top plating layer is 5 μm to 45 μm. 2. The printed wiring board according to claim 1, wherein said first base plating layer and said second base plating layer are each formed of a metal containing copper as a main component. 2. The printed wiring board according to claim 1, wherein the first top plating layer and the second top plating layer are each made of metal containing tin as a main component. 2. The printed wiring board according to claim 1, wherein said first base plating layer and said first conductor pad and between said second base plating layer and said first conductor pad layer Each layer has a base layer consisting of a nickel layer, a palladium layer and a gold layer. 2. The printed wiring board according to claim 1, wherein: between the first base plating layer and the first top plating layer and between the second base plating layer and the second top plating layer Each has an intermediate layer mainly composed of nickel between them. 8. The printed wiring board according to claim 7, wherein the intermediate layer has a thickness of 7 [mu]m or less. 2. The printed wiring board according to claim 1, wherein the first and second base plating layers are formed to a height exceeding the surface of the solder-resist layer, and the first base plating layer extends from the surface of the solder-resist layer. The thickness of the plating layer and the thickness of the second base plating layer are each in the range of 3 μm to 20 μm. 2. The printed wiring board according to claim 1, wherein the aspect ratio of said first opening is 0.5 or less, and the aspect ratio of said second opening is 0.6 or more. A method for manufacturing a printed wiring board,
forming a base insulating layer;
forming a conductor layer on the base insulating layer;
forming a solder resist layer on the base insulating layer and the conductor layer;
forming a first opening in the solder resist layer to expose a portion of the conductor layer as a first conductor pad;
forming in the solder resist layer a second opening having a diameter smaller than that of the first opening and exposing another part of the conductor layer as a second conductor pad;
forming a first bump on the first contact pad;
forming a second bump having a smaller diameter than the first bump on the second contact pad;
Forming the first bump includes forming a first base plating layer in the first opening and forming a first top plating layer on the first base plating layer. and reflowing the first top plating layer to increase the diameter of the plurality of first bumps and the diameter of the plurality of first base plating layers toward the center of the printed wiring board, thereby forming a printed wiring. increasing toward the center of the board;
Forming the second bump includes forming a second base plating layer in the second opening, and forming an upper surface of the first top plating layer on the second base plating layer. Forming a second top plating layer having a top surface that is above the top and reflowing the second top plating layer. 12. The printed wiring board manufacturing method according to claim 11, wherein the printed wiring board is divided into a central portion, an intermediate portion, and an outer peripheral portion, and the diameter of the first bump present in the central portion is R3, and When the diameter of the existing first bump is R2 and the diameter of the first bump existing in the outer peripheral portion is R1, R3>R2>R1. 12. The method of manufacturing a printed wiring board according to claim 11, wherein the thickness of said first top plating layer and said second top plating layer is within the range of 5 μm to 45 μm. 12. The method of manufacturing a printed wiring board according to claim 11, wherein said first base plating layer and said second base plating layer are each formed of a metal containing copper as a main component. 12. The method of manufacturing a printed wiring board according to claim 11, wherein the first top plating layer and the second top plating layer are each formed from a metal containing tin as a main component. 12. The method of manufacturing a printed wiring board according to claim 11, wherein: between said first base plating layer and said first conductor pad, and between said second base plating layer and said first conductor pad layer. forming underlayers each comprising a nickel layer, a palladium layer, and a gold layer, respectively. 12. The method of manufacturing a printed wiring board according to claim 11, wherein the thickness between said first base plating layer and said first top plating layer and between said second base plating layer and said second top plating layer forming an intermediate layer containing nickel as a main component between the layers. 18. The method of manufacturing a printed wiring board according to claim 17, wherein the intermediate layer has a thickness of 7 [mu]m or less. 12. The printed wiring board manufacturing method according to claim 11, wherein the first and second base plating layers are formed to a height exceeding the surface of the solder-resist layer, and the first base plating layer extends from the surface of the solder-resist layer. The thickness of the first base plating layer and the thickness of the second base plating layer are each within the range of 3 μm to 20 μm. 12. The printed wiring board manufacturing method according to claim 11, wherein the aspect ratio of the first opening is 0.5 or less, and the aspect ratio of the second opening is 0.6 or more.

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