JP2004071888A - Circuit substrate for semiconductor device and semiconductor device - Google Patents

Circuit substrate for semiconductor device and semiconductor device Download PDF

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Publication number
JP2004071888A
JP2004071888A JP2002230246A JP2002230246A JP2004071888A JP 2004071888 A JP2004071888 A JP 2004071888A JP 2002230246 A JP2002230246 A JP 2002230246A JP 2002230246 A JP2002230246 A JP 2002230246A JP 2004071888 A JP2004071888 A JP 2004071888A
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semiconductor device
semiconductor element
circuit pattern
insulating substrate
semiconductor
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Junichi Nagaseko
長迫　順一
Yoji Kawachi
河内　洋二
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26175—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/83051—Forming additional members, e.g. dam structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]

Abstract

<P>PROBLEM TO BE SOLVED: To position a semiconductor element even under a high-temperature condition, reduce a size of an insulating substrate and suppress costs even in the case of mounting the semiconductor element of a different size. <P>SOLUTION: A circuit substrate 10 for a semiconductor device has a circuit pattern 2 composed of a conductive material on an insulating substrate 1, a region 3 where the semiconductor element is disposed, and a groove part 4 encircling the region. Further, a semiconductor device 20 comprises the insulating substrate 1 having the circuit pattern 2 composed of the conductive material, and a semiconductor element 6 disposed on the circuit pattern of the insulating substrate, and also has a region where the semiconductor element is disposed, and a groove part encircling the region. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、絶縁基板の上に形成された回路パターン上に半導体素子を配置した半導体装置に関する。
【０００２】
【従来の技術】
半導体装置（パワーモジュール）は、絶縁基板に銅薄膜等の導電性材料からなる回路パターンが形成された回路基板と、該回路基板の回路パターンの上に配置された半導体素子（半導体チップ）とから構成されている。この回路基板５０に半導体素子を所定位置に配置する方法にはおよそ２通りある。第１の方法は、配置する半導体素子の大きさに合わせた形状の回路パターンを形成しておく方法である。第２の方法は、回路基板上に半導体素子の配置位置に合わせた形状にレジストを形成しておき、該レジストに沿って半導体素子を配置する方法である。まず、第１の方法について説明する。この場合には、図４に示すように、回路基板５０には、絶縁基板５１の上に半導体素子を配置する領域５３に合わせた形状を有するエッチング部５４が形成された回路パターンを備えている。
【０００３】
次に、第２の方法について説明する。図５に示すように、回路パターン５２に半導体素子５６ａ、５６ｂ、５６ｃ、５６ｄをはんだ付けする場合には、回路パターン５２上にレジスト５５ａ、５５ｂを形成して位置決めを行っている。さらに、この凸状のレジスト５５ａ、５５ｂによってはんだ流れの防止を行っている。
【０００４】
【発明が解決しようとする課題】
しかし、上記第１の方法の場合には、上記エッチング部５４を形成するために、配置する半導体素子のサイズに合わせて回路パターン５２をエッチングする必要がある。そのため、異なるサイズの半導体素子を配置する場合には、チップサイズに対応する異なる形状のエッチング部５４を回路パターン５２に形成する必要があり、コスト高となっていた。
【０００５】
また、上記第２の方法の場合には、高温条件下ではレジストが剥がれる場合があり、温度条件によっては半導体素子の位置決めのためにレジストを使用できない。
【０００６】
さらに、隣接してはんだ付けする半導体素子の間ではんだがくっついてしまわないように、位置決め用のレジスト５５ａの幅を大きくする必要がある。例えば、図５の左側の半導体素子５６ａ、５６ｂを配置するためのレジスト５５ａに比べて、右側の半導体素子５６ｃ、５６ｄをより近接させて配置するためにレジスト５５ｂを狭くしている。この場合、はんだ５８ｃ、５８ｄがレジスト５５ｂの上部で互いに付着してしまう場合がある。これを避けるためには、レジスト５５を一定以上の幅とする必要があるので、絶縁基板が大きくなっていた。このため近年の装置の小型化を実現することが困難となっていた。
【０００７】
そこで、本発明の目的は、半導体装置を作製するにあたって、高温条件下でも半導体素子を位置決めでき、絶縁基板のサイズを小さくできると共に、異なるサイズの半導体素子を搭載する場合にもコストを抑制することである。
【０００８】
【課題を解決するための手段】
本発明に係る半導体装置用回路基板は、絶縁基板の上に導電性材料からなる回路パターンを有する半導体装置用回路基板であって、
半導体素子を配置する領域と、前記領域を囲む溝部とを有することを特徴とする。
【０００９】
本発明に係る半導体装置は、導電性材料からなる回路パターンを有する絶縁基板と、
前記絶縁基板の回路パターンの上に配置された半導体素子と
を備え、
前記半導体素子を配置する領域と、前記領域を囲む溝部とを有することを特徴とする。
【００１０】
また、本発明に係る半導体装置は、前記半導体装置であって、前記溝部はレーザ光照射で形成されたことを特徴とする。
【００１１】
【発明の実施の形態】
本発明の実施の形態に係る半導体装置用回路基板及び半導体装置について添付図面を用いて説明する。なお、図では実質的に同一の部材には同一の符号を付している。
【００１２】
実施の形態１．
本発明の実施の形態１に係る半導体装置用回路基板について図１を用いて説明する。図１は、この半導体装置用回路基板の平面図である。この半導体装置用回路基板は、絶縁基板１の上に導電性材料からなる所定形状の回路パターン２を有する。この回路パターン２は、例えば、銅薄膜、ニッケルメッキ薄膜等を用いることができる。また、半導体素子を配置する領域３と、それを囲む溝部４を有する。この半導体素子を配置する領域３とは、半導体素子の底部をはんだ付けする部分である。また、この溝部４は、幅５０μｍ以上であって、深さ５μｍ〜パターン厚み以下の凹部からなる。この半導体装置用回路基板では、配置しようとする半導体素子のサイズの領域３と、それを囲む溝部４を有するので、素子のサイズによらず回路パターンの形状を標準化できる。そこで、異なるサイズの半導体素子を用いる場合にも絶縁基板１に同一の回路パターン２を有し、回路パターンに素子のサイズに合わせた溝部４を設けた半導体装置用回路基板を用いることができる。これによって、コストを減らすことができる。
【００１３】
なお、本発明は、上記実施の形態に記載の、絶縁基板の上の回路パターンに半導体素子を配置する場合に限られない。例えば、絶縁基板の回路パターンにブロックをはんだ付けする場合、電極端子をはんだ付けする場合、ブロックに半導体素子をはんだ付けする場合などにも同様に適用できる。この場合にもブロック、半導体素子又は電極端子等を囲む溝部を設けることによってはんだ流れを防止できる。
【００１４】
この半導体装置用回路基板は、以下の手順で作製される。
（ａ）絶縁基板１を用意する。
（ｂ）絶縁基板１の一方の面に、銅薄膜からなる所定形状の回路パターン２を形成する。この回路パターン２は、例えば、レジストを形成し、所定形状に露光後、残存させたレジストをマスクにしてエッチングを施して得ることができる。
（ｃ）絶縁基板１の回路パターン２において、半導体素子を配置する領域３を囲むようにレーザ光を一筆書き照射して、溝部４を形成する。この溝部４は、幅５０μｍ以上であって、深さ５μｍ〜パターン厚み以下の凹部からなる。なお、エッチング又はプレス加工によって溝部４を形成してもよい。この場合、エッチングではコスト的に高価になり、プレス加工では絶縁基板が割れる場合などが考えられるので、レーザ加工が好ましい。レーザ加工を用いることにより生産性、コスト面で有効である。さらに、レーザ加工において、レーザ光を一筆書き照射することにより生産性を向上させることができる。
以上の手順によって半導体装置用回路基板１０を得ることができる。
【００１５】
実施の形態２．
本発明の実施の形態２に係る半導体装置２０について図１から図３を用いて説明する。図２は、この半導体装置２０の断面図である。図３は、異なる間隔で半導体素子を半導体装置用回路基板に配置した場合の半導体装置の側断面図である。この半導体装置２０は、図１に示す半導体装置用回路基板１０に半導体素子６を配置している。即ち、回路パターン２を有する絶縁基板１と、該回路パターン２の溝部４に囲まれた領域３内にはんだ８によって配置された半導体素子６とを備える。この半導体装置２０では、図１に示すように、回路パターン２に半導体素子６を配置する領域３と、それを囲む溝部４を有している。回路パターン２に溝部４を設けているので、高温条件下でも半導体素子６をはんだ付けする場合に位置決めを確実に行うことができる。また、はんだ流れを溝部４で防止することができる。さらに、隣接する半導体素子６をはんだ付けする場合、図３に示すように、凹状の溝部４を設けたことによって、はんだ８の表面張力に起因して隣接する素子のはんだと付着しにくい。例えば、図３の左側の半導体素子６ａ、６ｂの配置間隔に比べて、右側の半導体素子６ｃ、６ｄを配置する間隔を狭くした場合にも、隣接する半導体素子６ｃ、６ｄの間ではんだ８ｃ、８ｄはそれぞれ付着することなく保持できるので、回路基板の大きさを小さくすることができる。
【００１６】
なお、絶縁基板に回路パターンを有する回路基板に関するいくつかの先行技術が知られている。特開平４−１０３１５０号公報には、セラミックス基板上に融着させた金属板の表面に凹凸を形成したＩＣ実装用基板が記載されている。この場合、ＩＣをはんだ付けする箇所をエッチングで全体として凹ませており、機械的な損傷を受けやすくなる。また過大なコストを必要とする。特開平４−１９２３４０号公報には、絶縁基板に固着させた銅パターンに形成された複数の溝を有する半導体回路用基板が記載されている。この溝は、はんだの巣を閉じ込めるために半導体素子をはんだ付けする面にわたって広く設けられており、素子の位置決めには有効ではない。さらに、特開平８−３１８４８号公報には、支持板表面の金属層にレーザ光照射で酸化金属層を形成し、半導体素体をろう付けする半導体装置の製造方法が記載されている。しかし、この場合に形成される酸化金属膜は溝ではなく逆に凸状に盛り上げられており、レジストの場合と同様の問題を有する。
【００１７】
この半導体装置は、以下の手順で作製される。
（ａ）絶縁基板１を用意する。
（ｂ）絶縁基板１の一方の面に、銅薄膜からなる所定形状の回路パターン２を形成する。この回路パターン２は、例えば、レジストを形成し、所定形状に露光後、残存させたレジストをマスクにしてエッチングを施して得ることができる。
（ｃ）絶縁基板１の回路パターン２において、半導体素子を配置する領域３を囲むようにレーザ光を一筆書き照射して、溝部４を形成する。この溝部は、幅５０μｍ以上であって、深さ５μｍ〜パターン厚み以下の凹部からなる。
（ｄ）半導体素子６を絶縁基板１上の回路パターン２部分に設けられた上記溝部４に囲まれた領域３に対応させて位置合わせを行って、はんだ付けする。
以上の手順によって半導体装置を得ることができる。
【００１８】
【発明の効果】
本発明に係る半導体装置用回路基板によれば、回路パターンの上に半導体素子の大きさに合わせて溝部を形成するので、半導体素子の大きさによらず回路パターンそのものの形状を統一化でき、標準化した回路パターンを用いることができる。これによって、異なるサイズの半導体素子を用いる場合にも同一の回路パターンを有する回路基板を用いることができるので、コストを減らすことができる。
【００１９】
本発明に係る半導体装置によれば、回路パターンに溝部を設けているので、高温条件下でも半導体素子をはんだ付けする場合に位置決めを確実に行うことができる。また、はんだ流れを溝部で防止することができる。さらに、隣接する半導体素子をはんだ付けする場合、従来の凸状のレジストに比べて凹状の溝部でははんだの表面張力で隣接する素子のはんだと付着しにくく、絶縁基板の大きさを小さくすることができる。
【００２０】
また、本発明に係る半導体装置によれば、溝部をレーザ加工により形成している。これによって絶縁基板の割れの発生を抑制でき、コストを抑えることができる。
【図面の簡単な説明】
【図１】本発明の実施の形態１に係る半導体装置用回路基板の平面図である。
【図２】本発明の実施の形態２に係る半導体装置の断面図である。
【図３】本発明の実施の形態２に係る半導体装置において、半導体素子の配置間隔を変化させた例を示す側面図である。
【図４】従来の半導体装置用回路基板の平面図である。
【図５】従来の半導体装置用回路基板に位置決め用のレジストを用いて半導体素子を配置した例を示す側面図である。
【符号の説明】
１　絶縁基板、２　回路パターン、３　半導体素子配置領域、４、４ａ、４ｂ　溝部、６、６ａ、６ｂ、６ｃ、６ｄ　半導体素子、８、８ａ、８ｂ、８ｃ、８ｄはんだ、１０　半導体装置用回路基板、２０　半導体装置、５０　半導体装置用回路基板、５１　絶縁基板、５２　回路パターン、５３　半導体素子配置領域、５４　エッチング部、５５ａ、５５ｂ　レジスト、５６ａ、５６ｂ、５６ｃ、５６ｄ　半道体素子、５８ａ、５８ｂ、５８ｃ、５８ｄ　はんだ[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device having a semiconductor element arranged on a circuit pattern formed on an insulating substrate.
[0002]
[Prior art]
A semiconductor device (power module) includes a circuit board in which a circuit pattern made of a conductive material such as a copper thin film is formed on an insulating substrate, and a semiconductor element (semiconductor chip) arranged on the circuit pattern of the circuit board. It is configured. There are approximately two methods for arranging semiconductor elements at predetermined positions on the circuit board 50. The first method is to form a circuit pattern having a shape corresponding to the size of a semiconductor element to be arranged. The second method is a method in which a resist is formed on a circuit board in a shape corresponding to the arrangement position of a semiconductor element, and the semiconductor element is arranged along the resist. First, the first method will be described. In this case, as shown in FIG. 4, the circuit board 50 is provided with a circuit pattern in which an etching portion 54 having a shape corresponding to a region 53 where a semiconductor element is arranged is formed on an insulating substrate 51. .
[0003]
Next, the second method will be described. As shown in FIG. 5, when the semiconductor elements 56a, 56b, 56c and 56d are soldered to the circuit pattern 52, resists 55a and 55b are formed on the circuit pattern 52 for positioning. Further, the solder resist is prevented by the convex resists 55a and 55b.
[0004]
[Problems to be solved by the invention]
However, in the case of the first method, in order to form the etching portion 54, it is necessary to etch the circuit pattern 52 according to the size of the semiconductor element to be arranged. Therefore, when arranging semiconductor elements of different sizes, it is necessary to form etched portions 54 of different shapes corresponding to the chip size on the circuit pattern 52, which has been costly.
[0005]
Further, in the case of the second method, the resist may be peeled off under high temperature conditions, and the resist cannot be used for positioning the semiconductor element depending on the temperature conditions.
[0006]
Further, it is necessary to increase the width of the positioning resist 55a so that the solder does not stick between the semiconductor elements to be soldered adjacently. For example, the resist 55b is narrower in order to dispose the right semiconductor elements 56c and 56d closer to each other than in the resist 55a for disposing the left semiconductor elements 56a and 56b in FIG. In this case, the solders 58c and 58d may adhere to each other above the resist 55b. In order to avoid this, the width of the resist 55 needs to be at least a certain width, so that the insulating substrate is large. For this reason, it has been difficult to reduce the size of the device in recent years.
[0007]
Therefore, an object of the present invention is to provide a semiconductor device which can position a semiconductor element even under a high temperature condition, can reduce the size of an insulating substrate, and suppress cost even when a semiconductor element of a different size is mounted. It is.
[0008]
[Means for Solving the Problems]
The circuit board for a semiconductor device according to the present invention is a circuit board for a semiconductor device having a circuit pattern made of a conductive material on an insulating substrate,
The semiconductor device has a region where a semiconductor element is arranged and a groove surrounding the region.
[0009]
A semiconductor device according to the present invention, an insulating substrate having a circuit pattern made of a conductive material,
A semiconductor element arranged on the circuit pattern of the insulating substrate,
The semiconductor device includes a region where the semiconductor element is arranged and a groove surrounding the region.
[0010]
Further, the semiconductor device according to the present invention is the semiconductor device, wherein the groove is formed by laser light irradiation.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
A circuit board for a semiconductor device and a semiconductor device according to an embodiment of the present invention will be described with reference to the accompanying drawings. In the drawings, substantially the same members are denoted by the same reference numerals.
[0012]
Embodiment 1 FIG.
First Embodiment A circuit board for a semiconductor device according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a plan view of the semiconductor device circuit board. The circuit board for a semiconductor device has a circuit pattern 2 of a predetermined shape made of a conductive material on an insulating substrate 1. As the circuit pattern 2, for example, a copper thin film, a nickel plating thin film, or the like can be used. Further, it has a region 3 in which a semiconductor element is arranged and a trench 4 surrounding the region 3. The region 3 where the semiconductor element is arranged is a part where the bottom of the semiconductor element is soldered. The groove 4 is formed of a concave portion having a width of 50 μm or more and a depth of 5 μm to a pattern thickness or less. Since the semiconductor device circuit board has the region 3 of the size of the semiconductor element to be arranged and the groove 4 surrounding the area, the shape of the circuit pattern can be standardized regardless of the element size. Therefore, even when semiconductor elements of different sizes are used, it is possible to use a circuit board for a semiconductor device having the same circuit pattern 2 on the insulating substrate 1 and providing the groove 4 in the circuit pattern according to the element size. This can reduce costs.
[0013]
Note that the present invention is not limited to the case where a semiconductor element is arranged in a circuit pattern over an insulating substrate described in the above embodiment. For example, the present invention can be similarly applied to a case where a block is soldered to a circuit pattern of an insulating substrate, a case where an electrode terminal is soldered, a case where a semiconductor element is soldered to a block, and the like. Also in this case, the flow of the solder can be prevented by providing a groove surrounding the block, the semiconductor element, the electrode terminal, and the like.
[0014]
This circuit board for a semiconductor device is manufactured by the following procedure.
(A) An insulating substrate 1 is prepared.
(B) A circuit pattern 2 of a predetermined shape made of a copper thin film is formed on one surface of the insulating substrate 1. The circuit pattern 2 can be obtained, for example, by forming a resist, exposing the resist to a predetermined shape, and performing etching using the remaining resist as a mask.
(C) In the circuit pattern 2 of the insulating substrate 1, a groove 4 is formed by irradiating a single stroke of laser light so as to surround the region 3 where the semiconductor element is arranged. The groove 4 is formed of a concave portion having a width of 50 μm or more and a depth of 5 μm to the pattern thickness. The groove 4 may be formed by etching or pressing. In this case, laser processing is preferable because etching is expensive in terms of cost, and pressing processing may break the insulating substrate. The use of laser processing is effective in terms of productivity and cost. Further, in laser processing, productivity can be improved by irradiating a single stroke of a laser beam.
The semiconductor device circuit board 10 can be obtained by the above procedure.
[0015]
Embodiment 2 FIG.
Second Embodiment A semiconductor device 20 according to a second embodiment of the present invention will be described with reference to FIGS. FIG. 2 is a sectional view of the semiconductor device 20. FIG. 3 is a side sectional view of the semiconductor device when semiconductor elements are arranged on a circuit board for a semiconductor device at different intervals. In this semiconductor device 20, a semiconductor element 6 is arranged on a semiconductor device circuit board 10 shown in FIG. That is, an insulating substrate 1 having a circuit pattern 2 and a semiconductor element 6 arranged by solder 8 in a region 3 surrounded by a groove 4 of the circuit pattern 2 are provided. As shown in FIG. 1, the semiconductor device 20 has a region 3 where the semiconductor element 6 is arranged in the circuit pattern 2 and a groove 4 surrounding the region 3. Since the groove 4 is provided in the circuit pattern 2, positioning can be reliably performed when the semiconductor element 6 is soldered even under a high temperature condition. Further, the flow of the solder can be prevented by the groove 4. Further, when soldering the adjacent semiconductor elements 6, as shown in FIG. 3, the provision of the concave grooves 4 makes it difficult for the adjacent semiconductor elements 6 to adhere to the solder of the adjacent elements due to the surface tension of the solder 8. For example, when the spacing between the right semiconductor elements 6c and 6d is narrower than the spacing between the left semiconductor elements 6a and 6b in FIG. 3, the solder 8c between the adjacent semiconductor elements 6c and 6d can be used. 8d can be held without adhering to each other, so that the size of the circuit board can be reduced.
[0016]
Some prior arts related to a circuit board having a circuit pattern on an insulating substrate are known. Japanese Patent Application Laid-Open No. 4-103150 describes an IC mounting substrate in which irregularities are formed on the surface of a metal plate fused to a ceramic substrate. In this case, the portion where the IC is to be soldered is entirely recessed by etching, so that the IC is easily damaged. It also requires excessive costs. Japanese Patent Application Laid-Open No. 4-192340 describes a semiconductor circuit substrate having a plurality of grooves formed in a copper pattern fixed to an insulating substrate. This groove is provided widely over the surface on which the semiconductor element is soldered in order to confine the solder nest, and is not effective in positioning the element. Further, Japanese Patent Application Laid-Open No. 8-31848 describes a method for manufacturing a semiconductor device in which a metal oxide layer is formed on a metal layer on a surface of a support plate by laser light irradiation and a semiconductor element is brazed. However, the metal oxide film formed in this case is raised not in a groove but in a convex shape, and has the same problem as in the case of a resist.
[0017]
This semiconductor device is manufactured by the following procedure.
(A) An insulating substrate 1 is prepared.
(B) A circuit pattern 2 of a predetermined shape made of a copper thin film is formed on one surface of the insulating substrate 1. The circuit pattern 2 can be obtained, for example, by forming a resist, exposing the resist to a predetermined shape, and performing etching using the remaining resist as a mask.
(C) In the circuit pattern 2 of the insulating substrate 1, a groove 4 is formed by irradiating a single stroke of laser light so as to surround the region 3 where the semiconductor element is arranged. The groove is formed of a concave portion having a width of 50 μm or more and a depth of 5 μm to a pattern thickness or less.
(D) The semiconductor element 6 is aligned and soldered so as to correspond to the area 3 surrounded by the groove 4 provided in the circuit pattern 2 on the insulating substrate 1.
A semiconductor device can be obtained by the above procedure.
[0018]
【The invention's effect】
According to the circuit board for a semiconductor device of the present invention, since the groove is formed on the circuit pattern according to the size of the semiconductor element, the shape of the circuit pattern itself can be unified regardless of the size of the semiconductor element, Standardized circuit patterns can be used. Thus, even when semiconductor elements of different sizes are used, a circuit board having the same circuit pattern can be used, so that cost can be reduced.
[0019]
According to the semiconductor device of the present invention, since the groove is provided in the circuit pattern, the positioning can be reliably performed when the semiconductor element is soldered even under a high temperature condition. Also, the flow of solder can be prevented by the groove. Furthermore, when soldering adjacent semiconductor elements, compared to the conventional convex resist, the concave grooves are less likely to adhere to the solder of the adjacent elements due to the surface tension of the solder, so that the size of the insulating substrate can be reduced. it can.
[0020]
According to the semiconductor device of the present invention, the groove is formed by laser processing. Thereby, the occurrence of cracks in the insulating substrate can be suppressed, and the cost can be reduced.
[Brief description of the drawings]
FIG. 1 is a plan view of a circuit board for a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a sectional view of a semiconductor device according to a second embodiment of the present invention;
FIG. 3 is a side view showing an example in which an arrangement interval of semiconductor elements is changed in a semiconductor device according to a second embodiment of the present invention.
FIG. 4 is a plan view of a conventional circuit board for a semiconductor device.
FIG. 5 is a side view showing an example in which semiconductor elements are arranged on a conventional circuit board for a semiconductor device using a resist for positioning.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Insulating substrate, 2 Circuit pattern, 3 Semiconductor element arrangement area, 4 4a, 4b Groove, 6, 6a, 6b, 6c, 6d Semiconductor element, 8, 8a, 8b, 8c, 8d solder, 10 Circuit board for semiconductor device , 20 semiconductor device, 50 semiconductor device circuit board, 51 insulating substrate, 52 circuit pattern, 53 semiconductor element arrangement region, 54 etching portion, 55a, 55b resist, 56a, 56b, 56c, 56d semi-semiconductor element, 58a, 58b , 58c, 58d Solder

Claims (3)

絶縁基板の上に導電性材料からなる回路パターンを有する半導体装置用回路基板であって、
半導体素子を配置する領域と、前記領域を囲む溝部を有することを特徴とする半導体装置用回路基板。A circuit board for a semiconductor device having a circuit pattern made of a conductive material on an insulating substrate,
A circuit board for a semiconductor device, comprising: a region in which a semiconductor element is arranged; and a groove surrounding the region. 導電性材料からなる回路パターンを有する絶縁基板と、
前記絶縁基板の回路パターンの上に配置された半導体素子と
を備え、
前記半導体素子を配置する領域と、前記領域を囲む溝部とを有することを特徴とする半導体装置。An insulating substrate having a circuit pattern made of a conductive material,
A semiconductor element arranged on the circuit pattern of the insulating substrate,
A semiconductor device comprising: a region in which the semiconductor element is arranged; and a groove surrounding the region. 前記溝部は、レーザ光照射で形成されたことを特徴とする請求項２に記載の半導体装置。The semiconductor device according to claim 2, wherein the groove is formed by laser light irradiation.
JP2002230246A 2002-08-07 2002-08-07 Circuit substrate for semiconductor device and semiconductor device Pending JP2004071888A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002230246A JP2004071888A (en) 2002-08-07 2002-08-07 Circuit substrate for semiconductor device and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002230246A JP2004071888A (en) 2002-08-07 2002-08-07 Circuit substrate for semiconductor device and semiconductor device

Publications (1)

Publication Number Publication Date
JP2004071888A true JP2004071888A (en) 2004-03-04

Family

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Family Applications (1)

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JP2002230246A Pending JP2004071888A (en) 2002-08-07 2002-08-07 Circuit substrate for semiconductor device and semiconductor device

Country Status (1)

Country Link
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2669938A2 (en) 2012-05-28 2013-12-04 Hitachi Ltd. Semiconductor device with an oxide solder flow prevention area on a substrate and corresponding manufacturing method
WO2014065124A1 (en) * 2012-10-25 2014-05-01 シャープ株式会社 Semiconductor device, and electronic device
JP2014216459A (en) * 2013-04-25 2014-11-17 三菱電機株式会社 Semiconductor device
JP2017005187A (en) * 2015-06-15 2017-01-05 株式会社東芝 Manufacturing method for semiconductor device and semiconductor device
JP2018078135A (en) * 2016-11-07 2018-05-17 スタンレー電気株式会社 Semiconductor device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2669938A2 (en) 2012-05-28 2013-12-04 Hitachi Ltd. Semiconductor device with an oxide solder flow prevention area on a substrate and corresponding manufacturing method
US9076774B2 (en) 2012-05-28 2015-07-07 Hitachi Power Semiconductor Device, Ltd. Semiconductor device and a method of manufacturing same
WO2014065124A1 (en) * 2012-10-25 2014-05-01 シャープ株式会社 Semiconductor device, and electronic device
JP2014216459A (en) * 2013-04-25 2014-11-17 三菱電機株式会社 Semiconductor device
JP2017005187A (en) * 2015-06-15 2017-01-05 株式会社東芝 Manufacturing method for semiconductor device and semiconductor device
US10128153B2 (en) 2015-06-15 2018-11-13 Kabushiki Kaisha Toshiba Method of fabricating a semiconductor device and the semiconductor device
JP2018078135A (en) * 2016-11-07 2018-05-17 スタンレー電気株式会社 Semiconductor device

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