JPH0513820A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0513820A JPH0513820A JP3189213A JP18921391A JPH0513820A JP H0513820 A JPH0513820 A JP H0513820A JP 3189213 A JP3189213 A JP 3189213A JP 18921391 A JP18921391 A JP 18921391A JP H0513820 A JPH0513820 A JP H0513820A
- Authority
- JP
- Japan
- Prior art keywords
- submount
- solder
- plating layer
- semiconductor
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置に関する。
詳しくは、接合面を下にして半導体素子をいわゆるエピ
サイドダウン実装した半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device.
More specifically, the present invention relates to a semiconductor device in which a semiconductor element is so-called episide-down mounted with the junction surface facing down.
【０００２】[0002]
【従来の技術】近年、発光ダイオードや半導体レーザ素
子等の半導体発光素子の開発は、高出力化、短波長化の
一途をたどっている。このような状況のもとでは、半導
体発光素子の発熱量も増大してゆくので、半導体発光装
置の放熱性を良好にし、熱特性を向上させる必要があ
る。2. Description of the Related Art In recent years, the development of semiconductor light emitting devices such as light emitting diodes and semiconductor laser devices has been steadily progressing toward higher output and shorter wavelengths. Under such circumstances, the amount of heat generated by the semiconductor light emitting element also increases, so it is necessary to improve the heat dissipation of the semiconductor light emitting device and improve its thermal characteristics.
【０００３】そこで、半導体発光素子の放熱性を良好に
するため、いわゆるエピサイドダウン実装（エピタキシ
ャル成長層を下にして実装する形態。ジャンクションダ
ウン実装とも言う。）が採用されている。Therefore, in order to improve the heat dissipation of the semiconductor light emitting device, so-called episide down mounting (a mode of mounting with the epitaxial growth layer facing down, also called junction down mounting) is adopted.
【０００４】図５は、従来より実施されているエピサイ
ドダウン実装の構造を示している。サブマウント基板５
２の表面に設けられた電極５３の上には、予め半田メッ
キ層５４が施されており、この上にチップ状をした半導
体発光素子１を接合面（ｐｎ接合面）２を下にして載置
し、半導体発光素子１の表面３をサブマウント５１に半
田接合させている。このような構造によると、発熱箇所
である接合面２とサブマウント５１との距離が短くなる
ので、接合面２で発生した熱がサブマウント５１及びス
テムから効率的に放熱される。FIG. 5 shows a structure of episide down mounting which has been conventionally carried out. Submount board 5
A solder plating layer 54 is previously applied on the electrode 53 provided on the surface of the semiconductor light emitting element 2 and the chip-shaped semiconductor light emitting element 1 is mounted thereon with the bonding surface (pn bonding surface) 2 facing downward. Then, the surface 3 of the semiconductor light emitting device 1 is soldered to the submount 51. With such a structure, the distance between the joint surface 2 which is a heat generating portion and the submount 51 is shortened, so that the heat generated at the joint surface 2 is efficiently radiated from the submount 51 and the stem.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、表面３
から接合部２までの距離ｈの小さな半導体発光素子１で
は、例えば１０μｍの厚みＨに対して表面３から接合部
２までの距離ｈが２μｍくらいしかないため、サブマウ
ント５１の半田メッキ層５４の厚みをうまく制御しない
と、半導体発光素子１にショート不良が多発するという
問題があった。すなわち、半田メッキ層５４の厚みが大
きいと、図５に示すように、半田接合時に、溶融した半
田材５４ａが毛細管現象等により半導体発光素子１の接
合面２まで達し、接合面２を電気的にショートさせると
いう問題があった。However, the surface 3
In the semiconductor light emitting element 1 having a small distance h from the bonding portion 2 to the bonding portion 2, the distance h from the surface 3 to the bonding portion 2 is only about 2 μm with respect to the thickness H of 10 μm. If the thickness is not properly controlled, there is a problem in that the semiconductor light emitting device 1 frequently causes a short circuit defect. That is, when the thickness of the solder plating layer 54 is large, as shown in FIG. 5, the molten solder material 54a reaches the bonding surface 2 of the semiconductor light emitting element 1 due to a capillary phenomenon or the like during solder bonding, and the bonding surface 2 is electrically connected. There was a problem of short-circuiting.
【０００６】一方、半田メッキ層５４の厚みを薄くする
ことによって、接合部２におけるショート不良を無くそ
うとすると、半導体発光素子１との密着性が悪くなり、
半導体発光素子１とサブマウント５１との間の熱伝導性
が低下して放熱が悪くなり、熱特性の改善を図り難いと
いう問題があった。On the other hand, if it is attempted to eliminate the short circuit defect in the joint portion 2 by reducing the thickness of the solder plating layer 54, the adhesion with the semiconductor light emitting element 1 will be deteriorated,
There has been a problem that the thermal conductivity between the semiconductor light emitting device 1 and the submount 51 is lowered and the heat radiation is deteriorated, and it is difficult to improve the thermal characteristics.
【０００７】本発明は、叙上の従来例の欠点に鑑みてな
されたものであり、その目的とするところは、半導体素
子の接合面で半田材によるショート不良を発生させるこ
となく、半導体素子のエピサイドダウン実装を可能にす
ることにある。The present invention has been made in view of the above-mentioned drawbacks of conventional examples, and an object of the present invention is to prevent a short circuit defect due to a solder material from occurring at a bonding surface of a semiconductor element. It is to enable episide down implementation.
【０００８】[0008]
【課題を解決するための手段】本発明の半導体装置は、
半導体素子の接合面に近い側の表面を、ステムやサブマ
ウント等の素子固定部に半田接合させた半導体装置にお
いて、前記素子固定部の一部に前記半導体素子以下の面
積を有する銅メッキ層を設け、該銅メッキ層の上に前記
半導体素子を半田材により半田接合させたことを特徴と
している。The semiconductor device of the present invention comprises:
In a semiconductor device in which the surface on the side close to the bonding surface of the semiconductor element is solder-bonded to an element fixing portion such as a stem or a submount, a copper plating layer having an area equal to or smaller than the semiconductor element is provided in part of the element fixing portion. It is characterized in that the semiconductor element is provided and solder-bonded to the semiconductor element by a solder material.
【０００９】また、この銅メッキ層の厚みとしては、１
μｍ以上２０μｍ以下にするのが好ましい。The thickness of the copper plating layer is 1
It is preferable that the thickness is not less than μm and not more than 20 μm.
【００１０】[0010]
【作用】本発明にあっては、素子固定部の上に半導体素
子以下の面積（半導体素子と同一の面積の場合を含
む。）を有する銅メッキ層を設け、素子固定部から突出
した銅メッキ層の上に半導体素子を半田接合させている
ので、半導体素子の半田付け時に半田材が半導体素子の
接合面まで回り込みにくく、半田材による接合面のショ
ート不良を防止することができる。In the present invention, a copper plating layer having an area equal to or smaller than that of the semiconductor element (including the case of the same area as the semiconductor element) is provided on the element fixing portion, and the copper plating protruding from the element fixing portion is provided. Since the semiconductor element is solder-bonded onto the layer, the solder material is less likely to reach the joint surface of the semiconductor element during soldering of the semiconductor element, and short-circuit defects of the joint surface due to the solder material can be prevented.
【００１１】さらに、サブマウントにエッチング等の加
工を施す必要がないので、どのようなサブマウント材に
も適用でき、また、電解メッキ等によって簡単に銅メッ
キ層を形成することができる。Further, since it is not necessary to perform processing such as etching on the submount, it can be applied to any submount material, and a copper plating layer can be easily formed by electrolytic plating or the like.
【００１２】さらに、銅メッキ層の上には半田メッキが
可能であるので、２回のメッキ工程により銅メッキ層と
半田メッキ層を積層させることができ、銅蒸着層などの
場合と比較して製造工程を簡単にできる。Further, since the solder plating can be performed on the copper plating layer, the copper plating layer and the solder plating layer can be laminated by two plating steps, which is more than that of the copper vapor deposition layer. The manufacturing process can be simplified.
【００１３】[0013]
【実施例】図１は本発明の一実施例による半導体装置Ａ
を示す斜視図である。この実施例では、銅製ステム２１
の上にサブマウント１１を実装し、その上に半導体レー
ザ素子や発光ダイオード等の半導体発光素子１をエピサ
イドダウン実装している。ステム２１は半導体発光素子
１で発生した熱を効率よく放熱させ、半導体発光素子１
の温度上昇を防止して熱特性を良好にしている。また、
サブマウント１１は、ステム２１と半導体発光素子１の
間に介在して両者の熱膨張係数の違いによる熱応力を吸
収し、半導体発光素子１の歪みによる破損を防止してい
る。FIG. 1 shows a semiconductor device A according to an embodiment of the present invention.
FIG. In this embodiment, the copper stem 21
The submount 11 is mounted on the above, and the semiconductor light emitting device 1 such as a semiconductor laser device or a light emitting diode is mounted on the above by episide down. The stem 21 efficiently dissipates the heat generated in the semiconductor light emitting device 1,
The temperature rise is prevented and the thermal characteristics are improved. Also,
The submount 11 is interposed between the stem 21 and the semiconductor light emitting device 1 to absorb the thermal stress due to the difference in thermal expansion coefficient between the stem 21 and the semiconductor light emitting device 1 and prevent the semiconductor light emitting device 1 from being damaged by distortion.
【００１４】図２（ａ）〜（ｄ）は、サブマウント１１
の作製プロセスを示しており、特に、図２（ｄ）は作製
されたサブマウント１１の構造を示している。これらの
図に従ってサブマウント１１の作製方法を説明しよう。
まず、シリコンウエハを適当な厚さに研磨してシリコン
製のサブマウント基板１２を得た後、サブマウント基板
１２の表裏両面にオーミック性もしくは非オーミック性
の電極１３ａ，１３ｂを形成する（図２（ａ））。つぎ
に、上面側の電極１３ａの上にフォトレジスト３１を印
刷塗布し、フォトリソグラフィ技術を用いてフォトレジ
スト３１をパターニングし、フォトレジスト３１に半導
体発光素子１の面積と同じ面積のパターン（窓）３２を
開口する（図２（ｂ））。なお、この段階では、サブマ
ウント基板１２の下面側には何も処理しない。2A to 2D show the submount 11
2 (d) shows the structure of the manufactured submount 11 in particular. A method of manufacturing the submount 11 will be described with reference to these drawings.
First, a silicon wafer is polished to an appropriate thickness to obtain a silicon submount substrate 12, and then ohmic or non-ohmic electrodes 13a and 13b are formed on both front and back surfaces of the submount substrate 12 (FIG. 2). (A)). Next, a photoresist 31 is printed and applied on the electrode 13a on the upper surface side, and the photoresist 31 is patterned by using a photolithography technique. A pattern (window) having the same area as the semiconductor light emitting element 1 is formed on the photoresist 31. 32 is opened (FIG. 2B). At this stage, nothing is processed on the lower surface side of the submount substrate 12.
【００１５】この後、フォトレジスト３１に開口された
パターン３２を通して上面側の電極１３ａの上に銅を電
解メッキして銅メッキ層１４ａを形成する。同時に、下
面側の電極１３ｂの表面全体にも電解メッキによって銅
メッキ層１４ｂを形成する。さらに、同じく電解メッキ
法により上下の銅メッキ層１４ａ，１４ｂの上に半田材
をメッキして半田メッキ層１５ａ，１５ｂを形成する
（図２（ｃ））。このようにしてフォトレジスト３１の
マスクを用いて電解メッキすれば、サブマウント基板１
２の上面側では、電極１３ａのフォトレジスト３１から
露出した部分だけに両メッキ層１４ａ，１５ａが形成さ
れるので、無駄なく銅材料及び半田材を使用することが
できる。Then, copper is electroplated on the upper surface side electrode 13a through the pattern 32 opened in the photoresist 31 to form a copper plating layer 14a. At the same time, the copper plating layer 14b is also formed on the entire surface of the lower electrode 13b by electrolytic plating. Further, a solder material is plated on the upper and lower copper plating layers 14a and 14b by the same electrolytic plating method to form solder plating layers 15a and 15b (FIG. 2C). In this way, if electrolytic plating is performed using the mask of the photoresist 31, the submount substrate 1
On the upper surface side of 2, the plating layers 14a and 15a are formed only on the portions of the electrode 13a exposed from the photoresist 31, so that the copper material and the solder material can be used without waste.
【００１６】この後、フォトレジスト３１を除去すれ
ば、図２（ｄ）に示すような構造のサブマウント１１が
作製される。After that, if the photoresist 31 is removed, the submount 11 having the structure as shown in FIG. 2D is manufactured.
【００１７】このようにして作製されたサブマウント１
１は、図１に示すように、ステム２１の上に載置され、
下面側の半田メッキ層１５ｂによってステム２１の表面
に半田接合される。さらに、サブマウント１１の上面に
部分的に突設された銅メッキ層１４ａの上には、接合面
２に近い側の表面３を下にして半導体発光素子１が載置
され、半田メッキ層１５ａによってサブマウント１１の
上にエピサイドダウン実装される。Submount 1 thus manufactured
1 is mounted on the stem 21 as shown in FIG.
It is soldered to the surface of the stem 21 by the solder plating layer 15b on the lower surface side. Further, the semiconductor light emitting element 1 is placed on the copper plating layer 14a partially protruding from the upper surface of the submount 11 with the surface 3 near the bonding surface 2 facing downward, and the solder plating layer 15a. Is mounted on the submount 11 by episide down.
【００１８】このとき、半導体発光素子１の接合面２
は、サブマウント１１に近い側に位置しているが、半田
メッキ層１５ａとサブマウント１１の電極１３ａとの間
には銅メッキ層１４ａの厚み分だけのスペースが存在し
ているので、半田メッキ層１５ａの半田材１５ｃが表面
張力等によって半導体発光素子１の側面に回り込みにく
くなり、図３に示すように半田材１５ｃが接合面２まで
達せず、接合面２のショート不良を防止することができ
る。At this time, the bonding surface 2 of the semiconductor light emitting device 1
Is located on the side close to the submount 11, but since there is a space for the thickness of the copper plating layer 14a between the solder plating layer 15a and the electrode 13a of the submount 11, the solder plating is performed. It is difficult for the solder material 15c of the layer 15a to wrap around the side surface of the semiconductor light emitting element 1 due to surface tension or the like, and the solder material 15c does not reach the joint surface 2 as shown in FIG. it can.
【００１９】ところで、同様な構造は例えばサブマウン
ト基板をエッチングして銅メッキ層に代わる凸部を設け
ることも考えられるが、このような方法では、加工の可
能なサブマウント基板材料の種類が限られ、また、工程
数も多くなる。これに対し、銅メッキ層によれば、あら
ゆるサブマウント材料に適用でき、工程も簡単になる。By the way, in a similar structure, for example, it is conceivable to etch the submount substrate to provide a convex portion instead of the copper plating layer, but in such a method, the kinds of submount substrate materials that can be processed are limited. In addition, the number of steps increases. On the other hand, the copper plating layer can be applied to any submount material, and the process can be simplified.
【００２０】また、銅以外のメッキ層も考えられるが、
半田メッキ層を形成するためには、下地層は銅層に限ら
れる。そして、銅メッキ層と半田メッキ層とを用いれ
ば、２度のメッキ処理によって簡単に銅メッキ層と半田
メッキ層を形成できる。これに対し、蒸着等によって銅
層を形成すれば、蒸着等とメッキとを行なわねばなら
ず、工程が複雑となる。Although a plating layer other than copper is also conceivable,
In order to form the solder plating layer, the base layer is limited to the copper layer. If the copper plating layer and the solder plating layer are used, the copper plating layer and the solder plating layer can be easily formed by performing the plating process twice. On the other hand, if the copper layer is formed by vapor deposition or the like, vapor deposition or the like and plating must be performed, which complicates the process.
【００２１】図４は本発明の別な実施例による半導体装
置Ｂの一部破断した断面図を示す。この実施例において
は、サブマウント１１の上面に設けられた銅メッキ層１
４ａの面積が半導体発光素子１の面積よりも小さくなっ
ているので、半田メッキ層１５ａの半田材１５ｃが半導
体発光素子１の側面までゆかず、接合面２におけるショ
ート不良が一層発生しにくくなっている。FIG. 4 is a partially cutaway sectional view of a semiconductor device B according to another embodiment of the present invention. In this embodiment, the copper plating layer 1 provided on the upper surface of the submount 11
Since the area of 4a is smaller than the area of the semiconductor light emitting element 1, the solder material 15c of the solder plating layer 15a does not move to the side surface of the semiconductor light emitting element 1 and the short-circuit defect in the joint surface 2 is further less likely to occur. There is.
【００２２】[0022]
【発明の効果】本発明によれば、半導体素子の半田付け
時に半田材が半導体素子の接合面まで回り込みにくく、
半田材による接合面のショート不良を防止することがで
きる。しかも、半田を介して半導体素子を素子固定部に
しっかりと密着させて固定することができ、エピサイド
ダウン実装された半導体素子の熱を素子固定部側へ効率
よく放熱させることができる。According to the present invention, when the semiconductor element is soldered, it is difficult for the solder material to reach the joint surface of the semiconductor element,
It is possible to prevent a short circuit defect of the joint surface due to the solder material. In addition, the semiconductor element can be firmly attached and fixed to the element fixing portion via the solder, and the heat of the semiconductor element mounted by episide down mounting can be efficiently radiated to the element fixing portion side.
【００２３】さらに、エッチング等によってサブマウン
トそのものを加工する必要がないので、加工が簡単で、
どのようなサブマウント材にも適用できる。Further, since it is not necessary to process the submount itself by etching or the like, the processing is easy,
It can be applied to any submount material.
【００２４】さらに、銅メッキ層の上には半田メッキが
可能であるので、２回のメッキ工程により銅メッキ層と
半田メッキ層を積層させることができ、銅蒸着層などの
場合と比較して製造工程を簡単にできる。Furthermore, since solder plating can be performed on the copper plating layer, the copper plating layer and the solder plating layer can be laminated by two plating steps, which is more than that of a copper vapor deposition layer. The manufacturing process can be simplified.
【図１】本発明の一実施例による半導体装置を示す斜視
図である。FIG. 1 is a perspective view showing a semiconductor device according to an embodiment of the present invention.
【図２】（ａ）（ｂ）（ｃ）（ｄ）は、同上のサブマウ
ントを製作する工程を示す断面図である。2 (a), (b), (c), and (d) are cross-sectional views showing a process of manufacturing the submount of the above.
【図３】本発明の作用を説明するための断面図である。FIG. 3 is a cross-sectional view for explaining the operation of the present invention.
【図４】本発明の別な実施例による半導体装置を示す一
部破断した断面図である。FIG. 4 is a partially cutaway sectional view showing a semiconductor device according to another embodiment of the present invention.
【図５】従来例を示す断面図である。FIG. 5 is a cross-sectional view showing a conventional example.
１ 半導体発光素子 ２ 接合面 １１ サブマウント １４ａ 銅メッキ層 １５ａ 半田メッキ層 ２１ ステム 1 Semiconductor light emitting element 2 joining surface 11 submount 14a Copper plating layer 15a Solder plating layer 21 stem
Claims (2)
ステムやサブマウント等の素子固定部に半田接合させた
半導体装置において、 前記素子固定部の一部に前記半導体素子以下の面積を有
する銅メッキ層を設け、該銅メッキ層の上に前記半導体
素子を半田材により半田接合させたことを特徴とする半
導体装置。1. A surface of a semiconductor element near a bonding surface is
In a semiconductor device soldered to an element fixing part such as a stem or a submount, a copper plating layer having an area equal to or smaller than the semiconductor element is provided in a part of the element fixing part, and the semiconductor element is provided on the copper plating layer. A semiconductor device in which the solder is joined by a solder material.
μｍ以下にしたことを特徴とする請求項１に記載の半導
体装置。2. The thickness of the copper plating layer is 1 μm or more and 20 or more.
The semiconductor device according to claim 1, wherein the semiconductor device has a thickness of μm or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3189213A JPH0513820A (en) | 1991-07-02 | 1991-07-02 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3189213A JPH0513820A (en) | 1991-07-02 | 1991-07-02 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0513820A true JPH0513820A (en) | 1993-01-22 |
Family
ID=16237446
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3189213A Pending JPH0513820A (en) | 1991-07-02 | 1991-07-02 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0513820A (en) |
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- 1991-07-02 JP JP3189213A patent/JPH0513820A/en active Pending
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