JP3347279B2 - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same

Info

Publication number
JP3347279B2
JP3347279B2 JP35121197A JP35121197A JP3347279B2 JP 3347279 B2 JP3347279 B2 JP 3347279B2 JP 35121197 A JP35121197 A JP 35121197A JP 35121197 A JP35121197 A JP 35121197A JP 3347279 B2 JP3347279 B2 JP 3347279B2
Authority
JP
Japan
Prior art keywords
solder
semiconductor
insulating substrate
joint
protrusion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP35121197A
Other languages
Japanese (ja)
Other versions
JPH11186331A (en
Inventor
吾朗 出田
秀雄 松本
建一 林
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP35121197A priority Critical patent/JP3347279B2/en
Publication of JPH11186331A publication Critical patent/JPH11186331A/en
Application granted granted Critical
Publication of JP3347279B2 publication Critical patent/JP3347279B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/4501Shape
    • H01L2224/45012Cross-sectional shape
    • H01L2224/45015Cross-sectional shape being circular
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00011Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01014Silicon [Si]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0105Tin [Sn]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01327Intermediate phases, i.e. intermetallics compounds
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0058Laminating printed circuit boards onto other substrates, e.g. metallic substrates
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power module, and more particularly to a semiconductor device in which an insulating substrate and a metal plate are joined by soldering, and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 9 is a sectional view showing a solder joint of a conventional semiconductor device. In the figure, 1 is a die pad of a semiconductor lead frame, 2 is a semiconductor die, 3 is solder, 4
Denotes a projection base. FIG. 10 is a perspective view showing a die pad of a conventional semiconductor lead frame. As shown in FIGS. 9 and 10, a protrusion 4 having a flat surface and the same height is provided on the surface of the die pad 1, and the semiconductor die 2 is mounted by attaching solder 3 to the entire surface including the protrusion 4 of the die pad 1. Place. As a result, the lower surface of the semiconductor die 2 is placed on the projection 4 and the solder 3.

[0003]

Generally, when a semiconductor device is actually used, the power is turned on and off, and the temperature of the semiconductor device changes accordingly. Since the components of the semiconductor device have different coefficients of linear expansion, a change in the temperature of the semiconductor device causes distortion in the solder joints of the semiconductor device, and cracks are generated and propagated in the solder joints to improve thermal and electrical reliability. There is a problem that the temperature is significantly reduced.

It is generally well known that a solder joint is formed thickly to suppress the generation and propagation of the crack. However, in a member having a relatively large solder joint area such as a semiconductor chip or a substrate, the thickness of the solder joint is not uniform, and the semiconductor chip or the substrate is inclined. There is a problem that a portion having a small thickness of the solder is always generated, and the margin for crack generation cannot be increased.

In order to solve this problem, in a conventional semiconductor device, as shown in FIGS. 9 and 10, a die pad 1 of a semiconductor lead frame provided with a flat protrusion 4 at a portion in contact with a semiconductor die 2 is used. Thereby, the thickness of the solder joint is formed uniformly. However, as shown in FIG. 11 which is an enlarged cross-sectional view near the contact portion between the projection base and the solder, the intermetallic compound layer 5 is formed at the interface of the contact portion between the projection base 4 and the solder 3. Further, at the contact portion between the projection base 4 and the solder 3, the shape of the solder 3 has a corner, that is, a so-called corner portion 6 .

Here, there is a problem in that stress is generally generated at the corners 6 and cracks are easily generated in the solder 3 in the vicinity of the interface between the protrusion 4 and the solder 3. Furthermore, since the intermetallic compound layer 5 generally has a hard and brittle property, and mechanical properties such as strength and elongation are remarkably inferior to those of the solder 3, there is a problem that cracks are easily generated in the solder 3. Was. The above problems become more serious when the solder joint area is large, such as when the ceramic insulating substrate is soldered to a metal plate.

Further, when a projection is formed at the solder joint between the ceramic insulating substrate and the metal plate, the ceramic insulating substrate does not largely tilt left and right in a molten state of the solder, and the generated voids are naturally discharged. You will lack power. For this reason, there is a problem that voids remain in the solder joint after cooling and solidification, resulting in poor heat dissipation.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and can make the thickness of a solder joint between an insulating substrate and a metal plate uniform, and can prevent cracks in the solder joint. It is an object of the present invention to provide a highly reliable semiconductor device excellent in heat dissipation and capable of suppressing generation and progress and generation of voids, and a method for manufacturing the same.

[0009]

According to a first aspect of the present invention, there is provided a semiconductor device comprising a projection made of Al which does not wet the solder.
The protrusion is attached to the metal plate side of the solder joint by metal bonding.
Fixed on the insulating substrate side of the solder joint
Secured by metal bonding and around the protrusion
A void is formed between the solder joints .

According to a second aspect of the present invention, there is provided a semiconductor device comprising:
Projections a wire piece which does not wet with solder, the wire
The thickness of the solder joint is regulated by the diameter .

According to a third aspect of the present invention, there is provided a semiconductor device comprising:
The wire piece that does not wet with solder is an Al bonding wire having a diameter of 50 to 400 microns.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device , comprising:
Forming Al projections that do not wet wet solder
Comprising the step, the step of solder joint, a step of forming a molten solder to melt the solder under atmospheric pressure, the pressure was reduced to the molten solder, by returning the molten solder to atmospheric pressure, and the surrounding of the projections Formed between the molten solder
And a step of shrinking the voids to be reduced and a step of solidifying the molten solder.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 shows a power module according to Embodiment 1 of the present invention. FIG. 1A is a perspective view, and FIG. 1B is a cross-sectional view. In the figure, 7 is a semiconductor chip made of Si (hereinafter, referred to as a chip), 8 is aluminum nitride (hereinafter, referred to as AlN) which is a ceramic, and 9 and 10 are copper layers which are conductor layers provided on both sides of AlN8. A pattern 11, an insulating substrate 11 composed of AlN 8 and copper patterns 9 and 10, a copper plate 12 as a metal plate, 13 solder used for fixing the chip 7 to the insulating substrate 11, and 14 an insulating substrate 11.
Tin-lead-based solder used for fixing the aluminum plate to the copper plate 12, 15
Are a plurality of protrusions provided at the joint of the solder 14 between the insulating substrate 11 and the copper plate 12, and are made of Al which does not wet the solder 14. Further, reference numeral 16 denotes a void formed around the projection 15.

As shown in FIG. 1, the power module has a structure in which an insulating substrate 11 in which a chip 7 is fixed by solder 13 is fixed on a copper plate 12, and is usually mounted on a heat sink (not shown). . At this time, Si,
The linear expansion coefficients of AlN and Cu are 4 ppm / ° C and 5
ppm / ° C and about 17 ppm / ° C. Therefore,
Although the chip 7 made of Si and the insulating substrate 11 made of AlN have close linear expansion coefficients, the solder 13 has a large margin for crack generation and propagation.
2 shows that the difference in the coefficient of linear expansion is large, and that the solder 14 has a small margin for crack generation and propagation.

In general, the solder 14 has a larger area at the solder joint portion than the solder 13 due to the heat radiation property, and the solder 14 is more susceptible to crack generation and propagation than the solder 13. Has become. Therefore, in the same manner as in the related art, the insulating substrate 11
The thickness of the solder 14 is made uniform by providing the protrusion 15 between the solder 14 and the copper plate 12, so that the solder 14 does not become thin locally, and the generation and propagation of cracks due to the uneven solder thickness Can be prevented.

Further, the protrusions 15 are not wetted by the solder 14
Since it is made of l, a void 16 is formed around the projection 15 so as to surround the projection 15. But void 1
6, the solder has a smooth fillet shape, and the intermetallic compound layer 5 and the corners 6 are not formed at the interface of the contact portion between the projection base 4 and the solder 3 as in the related art. Therefore, the projection 15 does not become a starting point of crack generation.

FIGS. 2A and 2B are enlarged sectional views of the solder portion when a crack is generated from the solder end,
As shown in FIG. 2A, when the crack 17 is generated from the end of the solder 14, the tip of the crack 17 has a sharp and sharp point, and local stress concentration occurs at the tip. The growth of the crack 17 is promoted. However, FIG.
As shown in (1), when the crack 17 reaches the void 16, the crack 17 is integrated with the void 16, thereby eliminating the stress concentration at the tip. As a result, even if a crack is generated from the solder end as described above, the growth of the crack 17 can be stopped.

As described above, since the projections 15 are formed of a material that does not wet the solder 14 at the joint portion of the solder 14, the generation and propagation of the crack 17 can be suppressed, and a semiconductor that has high thermal and electrical reliability can be obtained. The device can be manufactured.

Here, the chip 7 is placed on the insulating substrate 11.
Has been described as an example of a power module in which only one chip 7 is mounted, but a case in which a plurality of chips 7 are mounted on one insulating substrate 11 may be used. Further, the power module in which only one insulating substrate 11 is mounted on the copper plate 12 has been described as an example, but the insulating substrate 1 is mounted on one copper plate 12.
A plurality of 1s may be mounted.

Although AlN8 has been described as a ceramic as a main material of the insulating substrate 11, alumina, silicon nitride or the like may be used. Further, a copper plate 12 is used as a metal plate.
Has been described, but an alloy mainly composed of Al or Cu subjected to surface treatment or an alloy mainly composed of Al subjected to surface treatment may be used. In addition, although the tin-lead-based solder has been described as an example of the solder 14, any solder based on Sn, In, Pb, or Bi may be used.

Embodiment 2 FIG. FIG. 3 shows a configuration of a power module according to Embodiment 2 of the present invention. FIG. 3 (a) is a sectional view, and FIG.
(B) is an enlarged sectional view of a projection part. In the figure, 1
5a is a projection using a wire piece that does not wet with solder,
Reference numeral 18 denotes a metal joint where the projection 15a and the copper plate 12 are fixed by metal joining.

When the projection 15a is a wire piece , the projection 15a
The height of the projections 15a can be easily adjusted because the height of the projection 15a can be easily adjusted. Therefore, the solder 14 joint has excellent flatness and the thickness can be easily controlled, and it is easy to manufacture a semiconductor device having a desired solder 14 thickness in consideration of reliability against cracks and heat dissipation. Can be.

Further, in the first embodiment, no particular reference is made to the fixing of the projections. However, here, the projections 15a are metal-joined to the copper plate 12 at the metal joints 18,
5a and the accompanying voids 16 can be formed at desired positions. Therefore, the position of the void 16 that affects the heat radiation can be reliably controlled, the generation of the void 16 immediately below the chip 7 can be prevented, and the heat radiation of the semiconductor device can be improved.

Further, by forming the projections 15a using an Al bonding wire and using an ultrasonic bonding technique as the metal bonding means, the projection material can be easily obtained, and the workability of fixing the projections 15a is excellent and easy. In addition, the projection 15a can be formed in a short time and at low cost.
Further, the diameter of the bonding wire that determines the height of the projection 15a is preferably about 50 to 400 microns in consideration of heat dissipation and reliability.

FIG. 4 is a perspective view showing a projection on the copper plate. In the figure, a projection 15a is a bonding wire made of Al, and is fixed to the copper plate 12 at a metal bonding portion 18 using an ultrasonic bonding technique. As shown in the figure, the metal joint 18 of the protrusion 15a
Several places are shown. Generally, a thin wire has a metal joint at two places at both ends to prevent deformation of the end, and a thick wire has a metal joint at a central place since the end does not deform. Often. In any of the joining methods, the wire diameter becomes the height of the protrusion 15a, and the thickness of the solder 14 is controlled.

In FIG. 4, one or two metal joints 18 are provided.
Although the case where the protrusions 15a are mixed is shown, only one of them may be used. Although projections 15a is shown for the case of four, the projections 15 a may be a number unless be aligned and three or more.

As described above, if the protrusions 15a are formed of wires , the heights of the protrusions 15a can be easily adjusted, and the solder 14 can have excellent flatness and easily control the thickness. If the projection 15a is metal-bonded to the copper plate 12, the void 16 associated with the projection 15a will
It is possible to avoid being located immediately below, and it is possible to improve heat dissipation. Also, if the projections 15a are formed with Al bonding wires and are metal-bonded by an ultrasonic bonding technique, the projections 15a can be formed easily, quickly, and at low cost.

Embodiment 3 FIG. 5 shows a configuration of a power module according to Embodiment 3 of the present invention. FIG. 5A is a sectional view, and FIG.
(B) is an enlarged sectional view of a projection part. As shown in the figure, the projection 15a made of a wire piece here is the insulating substrate 1
1 is provided with a metal joint 18.

Here, generally, the insulating substrate 11 and the copper plate 12
First, the solder 14 is bonded to an appropriate amount of flux (10% wt.) Using a screen mask for solder printing (hereinafter referred to as a print mask) having openings at predetermined positions.
After the solder printing step of printing and supplying a solder paste containing (about) the copper paste at a predetermined position on the copper plate 12, the insulating substrate 11 is placed at the solder printing position on the copper plate 12. afterwards,
The solder paste is heated and melted to perform solder joining.

Therefore, if the projections 15a are fixed to the insulating substrate 11, since the projections 15a are not formed on the copper plate 12, smooth solder printing can be performed on the copper plate 12 in the solder printing step on the copper plate 12. , Insulating substrate 11
Bonding of the solder 14 with the copper plate 12 can be performed more easily.

Also, in general, the insulating substrate 11 is
Since it is smaller, lighter, and thinner, the insulating substrate 11 is easier to handle than the copper plate 12 even when the projection 15a is metal-joined, and the projection 15a can be fixed smoothly.

FIG. 6 is a sectional view of a power module according to Embodiment 3 of the present invention. As shown in the figure, two insulating substrates 11 are mounted on one copper plate 12,
Since the projections 15a are fixed to the insulating substrate 11, solder can be simultaneously supplied to two predetermined positions on the copper plate 12 in a normal solder printing process, and the solder 14 joining method does not become complicated. .

Embodiment 4 FIG. In the first to third embodiments, the structure of the power module has been described. Here, a method of manufacturing the power module will be described. FIG. 7 is a process sectional view showing a method for soldering a power module according to Embodiment 4 of the present invention. As shown in the drawing, in a solder printing process, a solder paste 19 containing a flux is placed on the copper plate 12.
Is printed and supplied, and the plate solder 20 containing no flux is additionally supplied to adjust the amount of supplied solder so that a desired amount of solder is obtained.

In this manner, both the amount of solder and the amount of flux can be controlled, and the occurrence of voids due to excessive supply of flux can be suppressed. Therefore, even if the thickness of the solder 14 is large, it is possible to form a good solder 14 joint having good flatness and few voids. Although the plate solder has been described here, any solid solder containing no flux, such as a thread solder or a bar solder, may be used.

Embodiment 5 FIG. 8 (a) to 8 (d) are process cross-sectional views illustrating a method for soldering a power module according to Embodiment 5 of the present invention.
The description will be made sequentially according to the drawings. First, as shown in FIG. 8A, the power module is placed under the atmospheric pressure at a temperature equal to or higher than the melting temperature of the solder 14. At this time, the solder 14 is in a molten state and forms a molten solder 14a. Innumerable small-diameter voids 21 are generated in the molten solder 14a.

Next, as shown in FIG.
When the pressure is reduced, the pressure in the void 21 becomes higher than the outside air pressure, so that the void 21 expands and becomes large due to merging with the void 21 in the vicinity. In addition, the voids 21 increase the fluidity due to the increase in size, gradually move in the molten solder 14a, and dissipate to the surrounding air.

Next, as shown in FIG. 8C, if the depressurized state is continued for a while, the voids 21 are almost scattered to the surrounding air, and the voids 16 around the projections 15 and only a few voids 21 are formed. Only.

Next, as shown in FIG. 8D, the pressure is returned to the atmospheric pressure. Since the pressure inside the molten solder 14a is smaller than the outside air pressure, the void 1 existing around the projection 15
6 and the void 21 slightly remaining in the molten solder 14a also shrink and become smaller. Thereafter, the molten solder 14a is solidified to form a solder 1 between the insulating substrate 11 and the copper plate 12.
Four joints are performed.

When the solder 14 bonding step is performed as described above, the voids 16 and 21 at the solder 14 bonded portion having the protrusion 15 are sufficiently small, and do not adversely affect heat radiation.

If the fourth embodiment and the fifth embodiment are combined, the effects of the respective embodiments are synergistic, and the generation of voids can be suppressed more effectively.

[0041]

According to the above manner the present invention according to the present invention, the projection is made of Al not wet the solder, the protrusion of the solder joint
Fixed to the metal plate side by metal bonding, or
Secured by metal bonding to the insulating substrate side of the solder joint
Between the periphery of the protrusion and the solder joint.
Since voids are formed around the protrusions, the solder forms a smooth fillet shape, forming no intermetallic compound layer or corners at the contact interface between the protrusions and the solder, and the protrusions are cracked. There is no starting point for occurrence. Further, even if a crack is generated from the solder end, there is an effect that the growth of the crack can be stopped by the void around the protrusion. In addition, the protrusion is used for metal bonding to the metal plate side of the solder joint.
Therefore, if it is fixed, place the protrusion at any position
The voids associated with the protrusions are located just below the semiconductor chip.
Can be avoided to improve heat dissipation.
There is an effect that can be. In addition, the protrusions
If it is fixed to the edge substrate by metal bonding,
There is no protrusion on the metal plate and the solder printing process on the metal plate is smooth
Solder joint between the insulating substrate and the metal plate.
The effect is that it can simply be done.

Further, since the protrusion is a piece of wire that does not wet with the solder, and the thickness of the solder joint is regulated by the wire diameter , a void forms a fillet shape around the protrusion, and the protrusion and the solder are separated. No intermetallic compound layer or corners are formed at the contact interface of, and the projections do not serve as starting points for crack generation. Also, even if a crack is generated from the solder end, the growth of the crack can be stopped by the void around the protrusion. Furthermore, since the height of the protrusions can be adjusted to the wire diameter, the heights of the protrusions can be easily adjusted, and the solder joints have excellent flatness and the thickness can be easily controlled, so that the reliability against cracks can be improved. There is an effect that can be increased.

The wire piece which does not get wet with the solder has a diameter of 5 mm.
Since it is an Al bonding wire of 0 to 400 microns, it is possible to easily determine the optimum solder thickness for heat dissipation and reliability, and to easily obtain a projection material and to have excellent workability of fixing the projection. Easily, in a short time,
There is an effect that projections can be formed at low cost.

In addition, gold is placed on a metal plate or on the insulating substrate.
Al projections that do not wet the solder fixed by metal bonding
Comprising the step of forming, a step of solder joint, a step of forming a molten solder to melt the solder under atmospheric pressure, the pressure was reduced to the molten solder, by returning the molten solder to atmospheric pressure, the projections Between the surroundings and the above molten solder
A step of reducing by contracting the voids formed, since the step of solidifying the molten solder, the circumferential projections that may harm the heat radiation at the solder joint
There is an effect that generation of voids formed in the surrounding can be suppressed as much as possible.

[Brief description of the drawings]

FIG. 1 is a perspective view and a sectional view showing a power module according to a first embodiment of the present invention.

FIG. 2 is an enlarged sectional view of a solder portion.

FIG. 3 is a cross-sectional view and an enlarged cross-sectional view illustrating a configuration of a power module according to Embodiment 2 of the present invention.

FIG. 4 is a perspective view showing a projection on a copper plate.

FIG. 5 is a cross-sectional view and an enlarged cross-sectional view illustrating a configuration of a power module according to Embodiment 3 of the present invention.

FIG. 6 is a sectional view of a power module according to Embodiment 3 of the present invention.

FIG. 7 is a process cross-sectional view showing a power module soldering method according to Embodiment 4 of the present invention;

FIG. 8 is a process cross-sectional view showing a soldering method for a power module according to Embodiment 5 of the present invention.

FIG. 9 is a cross-sectional view showing a solder joint of a conventional semiconductor device.

FIG. 10 is a perspective view showing a die pad of a conventional semiconductor lead frame.

FIG. 11 is an enlarged cross-sectional view of the vicinity of a contact portion between a projection base and solder of a conventional semiconductor device.

[Explanation of symbols]

7 semiconductor chip, 8 aluminum nitride, 9,10 copper pattern, 11 insulating substrate, 12 copper plate, 13 solder,
14 tin-lead solder, 14a molten solder, 1
5, 15a protrusion, 16, 21 void, 18 metal joint, 19 solder paste containing flux, 20
Sheet solder without flux.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-6-216167 (JP, A) JP-A-9-8168 (JP, A) JP-A-7-249632 (JP, A) JP-A-4- 120741 (JP, A) JP-A-9-148347 (JP, A) JP-A-6-152094 (JP, A) JP-A-6-155081 (JP, A) Japanese Utility Model Application Laid-Open No. 61-86940 (JP, U) (58) Field surveyed (Int. Cl. 7 , DB name) H01L 21/52 H01L 21/60

Claims (4)

    (57) [Claims]
  1. An insulating substrate having a conductor layer which can be soldered on both sides of a main material made of ceramics is provided on a metal plate, a semiconductor chip is provided on the insulating substrate, and the insulating substrate and the metal plate are soldered. Are joined via a joint,
    In a semiconductor device in which a plurality of protrusions for regulating the thickness of the solder joint are provided at the solder joint, the protrusion is made of Al that is not wetted by solder, and the protrusion is
    The solder joint is fixed to the metal plate side by metal bonding.
    Or the insulating base of the solder joint
    It is fixed to the plate side by metal bonding and
    A void is formed between the periphery of the protrusion and the solder joint.
    A semiconductor device characterized in that:
  2. 2. The semiconductor device according to claim 1, wherein the protrusion is a piece of wire that does not wet the solder, and the thickness of the solder joint is regulated by the wire diameter .
  3. 3. A wire piece which does not wet with solder has a diameter of 50 to 50 mm.
    3. The semiconductor device according to claim 2, wherein the bonding device is an Al bonding wire of 400 microns.
  4. 4. A method comprising the steps of: soldering an insulating substrate having a conductor layer that can be soldered on both surfaces of a main material made of ceramics on a metal plate; and mounting a semiconductor chip on the insulating substrate. In the method of manufacturing a semiconductor device, the semiconductor device is fixed on the metal plate or the insulating substrate by metal bonding.
    The process of forming Al projections that do not wet the attached solder
    Provided, said solder joint, a step of forming a molten solder to melt the solder under atmospheric pressure, the pressure was reduced to the molten solder, by returning the molten solder to atmospheric pressure, around the projections and the Formed between the molten solder
    A method of shrinking the voids to reduce the size of the voids, and a step of solidifying the molten solder.
JP35121197A 1997-12-19 1997-12-19 Semiconductor device and method of manufacturing the same Expired - Lifetime JP3347279B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP35121197A JP3347279B2 (en) 1997-12-19 1997-12-19 Semiconductor device and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP35121197A JP3347279B2 (en) 1997-12-19 1997-12-19 Semiconductor device and method of manufacturing the same

Publications (2)

Publication Number Publication Date
JPH11186331A JPH11186331A (en) 1999-07-09
JP3347279B2 true JP3347279B2 (en) 2002-11-20

Family

ID=18415808

Family Applications (1)

Application Number Title Priority Date Filing Date
JP35121197A Expired - Lifetime JP3347279B2 (en) 1997-12-19 1997-12-19 Semiconductor device and method of manufacturing the same

Country Status (1)

Country Link
JP (1) JP3347279B2 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3809806B2 (en) 2002-03-29 2006-08-16 富士電機デバイステクノロジー株式会社 Manufacturing method of semiconductor device
US20070216026A1 (en) * 2006-03-20 2007-09-20 Adams Zhu Aluminum bump bonding for fine aluminum wire
FR2901347B1 (en) * 2006-05-22 2008-07-18 Valeo Vision Sa Thermal dissipating component and diode lighting and / or signaling device equipped with such a component
JP2011228604A (en) * 2010-04-23 2011-11-10 Honda Motor Co Ltd Manufacturing method of circuit board and circuit board
JP2014165255A (en) * 2013-02-22 2014-09-08 Toyota Motor Corp Semiconductor device
DE112014003203B4 (en) * 2013-07-10 2019-08-01 Mitsubishi Electric Corporation Semiconductor unit and method of making the same
JP6165025B2 (en) * 2013-10-31 2017-07-19 三菱電機株式会社 Semiconductor module
JP6242328B2 (en) * 2014-12-02 2017-12-06 三菱電機株式会社 Semiconductor device
CN109314063A (en) * 2016-06-14 2019-02-05 三菱电机株式会社 Power semiconductor device

Also Published As

Publication number Publication date
JPH11186331A (en) 1999-07-09

Similar Documents

Publication Publication Date Title
JP3923258B2 (en) Power control system electronic circuit device and manufacturing method thereof
JP4246243B2 (en) Semiconductor integrated circuit device
JP4756200B2 (en) Metal ceramic circuit board
KR970005526B1 (en) Method for forming solder bump interconnections to a solder plated circuit trace
US7936569B2 (en) Circuit device and method of manufacturing the same
US8232144B2 (en) Non-pull back pad package with an additional solder standoff
JP3971296B2 (en) Metal-ceramic bonding substrate and manufacturing method thereof
US6661087B2 (en) Lead frame and flip chip semiconductor package with the same
US4814855A (en) Balltape structure for tape automated bonding, multilayer packaging, universal chip interconnection and energy beam processes for manufacturing balltape
US7221045B2 (en) Flat chip semiconductor device and manufacturing method thereof
US5874784A (en) Semiconductor device having external connection terminals provided on an interconnection plate and fabrication process therefor
JP3706533B2 (en) Semiconductor device and semiconductor module
EP2214201B1 (en) Process for producing substrate for power module, substrate for power module, and power module
US7362580B2 (en) Electronic assembly having an indium wetting layer on a thermally conductive body
KR100239406B1 (en) Surface mounted semiconductor package and method of manufacturing the same
US6828173B2 (en) Semiconductor device including edge bond pads and methods
KR100957078B1 (en) Electrically isolated power device package
US6376907B1 (en) Ball grid array type package for semiconductor device
DE10013189B4 (en) Substrate for a power module
JP4699353B2 (en) Alternative FLMP package design and package manufacturing method
US4920074A (en) Surface mount plastic package semiconductor integrated circuit, manufacturing method thereof, as well as mounting method and mounted structure thereof
US6657124B2 (en) Advanced electronic package
US6259608B1 (en) Conductor pattern for surface mount devices and method therefor
TWI311348B (en) Semiconductor device
US6100475A (en) Solder bonding printed circuit boards

Legal Events

Date Code Title Description
FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080906

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080906

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090906

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090906

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100906

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110906

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110906

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120906

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130906

Year of fee payment: 11

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

EXPY Cancellation because of completion of term