JP3347279B2 - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same

Info

Publication number
JP3347279B2
JP3347279B2 JP35121197A JP35121197A JP3347279B2 JP 3347279 B2 JP3347279 B2 JP 3347279B2 JP 35121197 A JP35121197 A JP 35121197A JP 35121197 A JP35121197 A JP 35121197A JP 3347279 B2 JP3347279 B2 JP 3347279B2
Authority
JP
Japan
Prior art keywords
solder
insulating substrate
semiconductor device
joint
protrusion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP35121197A
Other languages
Japanese (ja)
Other versions
JPH11186331A (en
Inventor
建一 林
吾朗 出田
秀雄 松本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
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Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP35121197A priority Critical patent/JP3347279B2/en
Publication of JPH11186331A publication Critical patent/JPH11186331A/en
Application granted granted Critical
Publication of JP3347279B2 publication Critical patent/JP3347279B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
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    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】この発明はパワーモジュール
に関し、特に絶縁基板と金属板とをはんだ接合した半導
体装置およびその製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power module, and more particularly to a semiconductor device in which an insulating substrate and a metal plate are joined by soldering, and a method of manufacturing the same.

【０００２】[0002]

【従来の技術】図９は従来の半導体装置のはんだ接合部
を示す断面図である。図において、１は半導体リードフ
レームのダイパッド、２は半導体ダイ、３ははんだ、４
は突起台である。また、図１０は従来の半導体リードフ
レームのダイパッドを示す斜視図である。図９および図
１０に示すように、ダイパッド１の表面に表面が平坦な
同一高さの突起台４を設け、ダイパッド１の突起台４を
含む全面にはんだ３を付着させて半導体ダイ２を載置す
る。これにより半導体ダイ２の下面は突起台４およびは
んだ３によって載置される。2. Description of the Related Art FIG. 9 is a sectional view showing a solder joint of a conventional semiconductor device. In the figure, 1 is a die pad of a semiconductor lead frame, 2 is a semiconductor die, 3 is solder, 4
Denotes a projection base. FIG. 10 is a perspective view showing a die pad of a conventional semiconductor lead frame. As shown in FIGS. 9 and 10, a protrusion 4 having a flat surface and the same height is provided on the surface of the die pad 1, and the semiconductor die 2 is mounted by attaching solder 3 to the entire surface including the protrusion 4 of the die pad 1. Place. As a result, the lower surface of the semiconductor die 2 is placed on the projection 4 and the solder 3.

【０００３】[0003]

【発明が解決しようとする課題】一般に、半導体装置を
実際に使用する場合、電源をオン・オフするのである
が、これに伴って半導体装置に温度変化が生じる。半導
体装置の各構成部材の線膨張係数が異なることから半導
体装置の温度変化によって半導体装置のはんだ接合部に
歪みが生じ、はんだ接合部に亀裂が発生・進展して熱的
および電気的信頼性を著しく低下させるという問題点が
あった。Generally, when a semiconductor device is actually used, the power is turned on and off, and the temperature of the semiconductor device changes accordingly. Since the components of the semiconductor device have different coefficients of linear expansion, a change in the temperature of the semiconductor device causes distortion in the solder joints of the semiconductor device, and cracks are generated and propagated in the solder joints to improve thermal and electrical reliability. There is a problem that the temperature is significantly reduced.

【０００４】この亀裂の発生・進展を抑制するものとし
てはんだ接合部を厚く形成することが一般に良く知られ
ている。しかし、半導体チップや基板等の比較的大きな
はんだ接合面積を有する部材では、はんだ接合部の厚さ
は均一にならず半導体チップや基板等に傾きが生じ、単
に供給するはんだ量を多くしてもはんだ厚さの薄い部分
がかならず発生し、亀裂発生に対する余裕度を高めるこ
とにはならないという問題点があった。It is generally well known that a solder joint is formed thickly to suppress the generation and propagation of the crack. However, in a member having a relatively large solder joint area such as a semiconductor chip or a substrate, the thickness of the solder joint is not uniform, and the semiconductor chip or the substrate is inclined. There is a problem that a portion having a small thickness of the solder is always generated, and the margin for crack generation cannot be increased.

【０００５】これを解決するものとして従来の半導体装
置では図９，図１０に示すように、半導体ダイ２と接触
する部分に平坦な突起台４を設けた半導体リードフレー
ムのダイパッド１を使用することによりはんだ接合部の
厚さを均一に形成している。ところが、突起台とはんだ
との接触部近傍の拡大断面図である図１１に示すよう
に、突起台４とはんだ３との接触部界面において金属間
化合物層５が形成される。また、突起台４とはんだ３と
の接触部においてははんだ３の形状は角を持ち、いわゆ
る角部６となる。In order to solve this problem, in a conventional semiconductor device, as shown in FIGS. 9 and 10, a die pad 1 of a semiconductor lead frame provided with a flat protrusion 4 at a portion in contact with a semiconductor die 2 is used. Thereby, the thickness of the solder joint is formed uniformly. However, as shown in FIG. 11 which is an enlarged cross-sectional view near the contact portion between the projection base and the solder, the intermetallic compound layer 5 is formed at the interface of the contact portion between the projection base 4 and the solder 3. Further, at the contact portion between the projection base 4 and the solder 3, the shape of the solder 3 has a corner, that is, a so-called corner portion 6 .

【０００６】ここで、一般に角部６には応力集中が生
じ、突起台４とはんだ３との界面近傍部においてはんだ
３に亀裂が発生しやすいという問題点があった。さら
に、金属間化合物層５が一般に硬くて脆い性質を有して
おり、強度や伸び等の機械的物性がはんだ３に比べて著
しく劣るためにはんだ３に亀裂が発生しやすいという問
題点があった。以上のような問題点は、セラミックス製
絶縁基板と金属板とのはんだ接合のようにはんだ接合面
積の大きな場合により大きな問題となる。Here, there is a problem in that stress is generally generated at the corners 6 and cracks are easily generated in the solder 3 in the vicinity of the interface between the protrusion 4 and the solder 3. Furthermore, since the intermetallic compound layer 5 generally has a hard and brittle property, and mechanical properties such as strength and elongation are remarkably inferior to those of the solder 3, there is a problem that cracks are easily generated in the solder 3. Was. The above problems become more serious when the solder joint area is large, such as when the ceramic insulating substrate is soldered to a metal plate.

【０００７】更に、セラミックス製絶縁基板と金属板と
のはんだ接合部において突起台を形成すると、はんだ溶
融状態においてセラミックス製絶縁基板が大きく左右に
傾くことがなく、発生したボイドを自然に排出する駆動
力に欠けることになる。そのために、冷却凝固後のはん
だ接合部にボイドが残存してしまい、放熱性が悪くなる
という問題点があった。Further, when a projection is formed at the solder joint between the ceramic insulating substrate and the metal plate, the ceramic insulating substrate does not largely tilt left and right in a molten state of the solder, and the generated voids are naturally discharged. You will lack power. For this reason, there is a problem that voids remain in the solder joint after cooling and solidification, resulting in poor heat dissipation.

【０００８】この発明は上記のような問題点を解消する
ために成されたもので、絶縁基板と金属板との間のはん
だ接合部の厚さを均一にできるとともに、はんだ接合部
において亀裂の発生および進展を抑制でき、ボイドの発
生も抑えることのできる放熱性に優れた信頼性の高い半
導体装置およびその製造方法を提供することを目的とし
ている。SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and can make the thickness of a solder joint between an insulating substrate and a metal plate uniform, and can prevent cracks in the solder joint. It is an object of the present invention to provide a highly reliable semiconductor device excellent in heat dissipation and capable of suppressing generation and progress and generation of voids, and a method for manufacturing the same.

【０００９】[0009]

【課題を解決するための手段】この発明の請求項１に係
る半導体装置は、突起がはんだに濡れないＡｌからな
り、突起ははんだ接合部の金属板側に金属接合によって
固着されている、または 、はんだ接合部の絶縁基板側に
金属接合によって固着されているとともに、突起の周囲
とはんだ接合部との間にボイドが形成されるものであ
る。According to a first aspect of the present invention, there is provided a semiconductor device comprising a projection made of Al which does not wet the solder.
The protrusion is attached to the metal plate side of the solder joint by metal bonding.
Fixed on the insulating substrate side of the solder joint
Secured by metal bonding and around the protrusion
A void is formed between the solder joints .

【００１０】この発明の請求項２に係る半導体装置は、
突起がはんだに濡れないワイヤ片であって、上記ワイヤ
径によってはんだ接合部の厚さを規制するようにしたも
のである。According to a second aspect of the present invention, there is provided a semiconductor device comprising:
Projections a wire piece which does not wet with solder, the wire
The thickness of the solder joint is regulated by the diameter .

【００１１】この発明の請求項３に係る半導体装置は、
はんだに濡れないワイヤ片が直径５０〜４００ミクロン
のＡｌのボンディングワイヤであるものである。According to a third aspect of the present invention, there is provided a semiconductor device comprising:
The wire piece that does not wet with solder is an Al bonding wire having a diameter of 50 to 400 microns.

【００１２】この発明の請求項４に係る半導体装置の製
造方法は、金属板上または上記絶縁基板上に金属接合に
より固着されたはんだに濡れないＡｌの突起を形成する
工程を備え、はんだ接合する工程が、大気圧下ではんだ
を溶融し溶融はんだを形成する工程と、上記溶融はんだ
を減圧した後に、上記溶融はんだを大気圧に戻すことに
より、上記突起の周囲と上記溶融はんだとの間に形成さ
れるボイドを収縮して小さくする工程と、上記溶融はん
だを凝固する工程からなるものである。According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device , comprising:
Forming Al projections that do not wet wet solder
Comprising the step, the step of solder joint, a step of forming a molten solder to melt the solder under atmospheric pressure, the pressure was reduced to the molten solder, by returning the molten solder to atmospheric pressure, and the surrounding of the projections Formed between the molten solder
And a step of shrinking the voids to be reduced and a step of solidifying the molten solder.

【００１３】[0013]

【発明の実施の形態】実施の形態１． 図１はこの発明の実施の形態１のパワーモジュールを示
したもので、図１（ａ）は斜視図であり、図１（ｂ）は
断面図である。図において、７はＳｉ製の半導体チップ
（以下、チップと称す）、８はセラミックスである窒化
アルミ（以下、ＡｌＮと称す）、９，１０はＡｌＮ８の
両面に備えられた導体層である銅製のパターン、１１は
ＡｌＮ８と銅製のパターン９，１０とからなる絶縁基
板、１２は金属板としての銅板、１３はチップ７と絶縁
基板１１との固着に用いたはんだ、１４は絶縁基板１１
と銅板１２との固着に用いたすず−鉛系のはんだ、１５
は絶縁基板１１と銅板１２とのはんだ１４接合部に複数
個設置された突起であり、はんだ１４に濡れないＡｌ製
でできている。更に、１６は突起１５の周囲に生じるボ
イドである。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 shows a power module according to Embodiment 1 of the present invention. FIG. 1A is a perspective view, and FIG. 1B is a cross-sectional view. In the figure, 7 is a semiconductor chip made of Si (hereinafter, referred to as a chip), 8 is aluminum nitride (hereinafter, referred to as AlN) which is a ceramic, and 9 and 10 are copper layers which are conductor layers provided on both sides of AlN8. A pattern 11, an insulating substrate 11 composed of AlN 8 and copper patterns 9 and 10, a copper plate 12 as a metal plate, 13 solder used for fixing the chip 7 to the insulating substrate 11, and 14 an insulating substrate 11.
Tin-lead-based solder used for fixing the aluminum plate to the copper plate 12, 15
Are a plurality of protrusions provided at the joint of the solder 14 between the insulating substrate 11 and the copper plate 12, and are made of Al which does not wet the solder 14. Further, reference numeral 16 denotes a void formed around the projection 15.

【００１４】図１に示すように、パワーモジュールはチ
ップ７をはんだ１３によって固着した絶縁基板１１を銅
板１２上に固着した構造をしており、通常はヒートシン
ク（図示なし）上に搭載されている。このとき、Ｓｉ，
ＡｌＮ，Ｃｕの線膨張係数はそれぞれ４ｐｐｍ／℃，５
ｐｐｍ／℃，１７ｐｐｍ／℃程度である。したがって、
Ｓｉからなるチップ７とＡｌＮからなる絶縁基板１１と
は線膨張係数が近くはんだ１３では亀裂発生・進展に対
する余裕度は大きいのであるが、絶縁基板１１と銅板１
２とでは線膨張係数の差が大きくはんだ１４では亀裂発
生・進展に対する余裕度が小さいことがわかる。As shown in FIG. 1, the power module has a structure in which an insulating substrate 11 in which a chip 7 is fixed by solder 13 is fixed on a copper plate 12, and is usually mounted on a heat sink (not shown). . At this time, Si,
The linear expansion coefficients of AlN and Cu are 4 ppm / ° C and 5
ppm / ° C and about 17 ppm / ° C. Therefore,
Although the chip 7 made of Si and the insulating substrate 11 made of AlN have close linear expansion coefficients, the solder 13 has a large margin for crack generation and propagation.
2 shows that the difference in the coefficient of linear expansion is large, and that the solder 14 has a small margin for crack generation and propagation.

【００１５】また、はんだ１３よりもはんだ１４の方が
放熱性の関係から、はんだ接合部の面積が大きいのが一
般的であり、はんだ１４ははんだ１３に比べて更に亀裂
発生・進展が起こりやすくなっている。そこで、従来と
同様にして、はんだ１４接合部においては絶縁基板１１
と銅板１２との間に突起１５を設けることによりはんだ
１４の厚さを均一に形成し、局部的にはんだ１４が薄く
なるようなことがなく、はんだ厚さの不均一による亀裂
の発生・進展は防止することができる。In general, the solder 14 has a larger area at the solder joint portion than the solder 13 due to the heat radiation property, and the solder 14 is more susceptible to crack generation and propagation than the solder 13. Has become. Therefore, in the same manner as in the related art, the insulating substrate 11
The thickness of the solder 14 is made uniform by providing the protrusion 15 between the solder 14 and the copper plate 12, so that the solder 14 does not become thin locally, and the generation and propagation of cracks due to the uneven solder thickness Can be prevented.

【００１６】更に、突起１５ははんだ１４に濡れないＡ
ｌ製であるので、突起１５の周囲にはボイド１６が突起
１５を取り囲むように生じてしまう。しかし、ボイド１
６の周囲では、はんだは滑らかなフィレット形状とな
り、従来のように突起台４とはんだ３との接触部界面に
おいて金属間化合物層５や角部６が形成されることがな
い。したがって、突起１５の部分が亀裂発生の起点とな
ることがない。Further, the protrusions 15 are not wetted by the solder 14
Since it is made of l, a void 16 is formed around the projection 15 so as to surround the projection 15. But void 1
6, the solder has a smooth fillet shape, and the intermetallic compound layer 5 and the corners 6 are not formed at the interface of the contact portion between the projection base 4 and the solder 3 as in the related art. Therefore, the projection 15 does not become a starting point of crack generation.

【００１７】また、図２（ａ）（ｂ）ははんだ端部から
亀裂が発生した場合のはんだ部分の拡大断面図であり、
図２（ａ）に示すように、亀裂１７がはんだ１４の端部
から発生したとき、亀裂１７の先端部の形状は先が細く
鋭く尖った形状となり、先端部に局部的な応力集中が生
じ亀裂１７の進展を促進させる。ところが、図２（ｂ）
に示すように、亀裂１７がボイド１６に達すると、亀裂
１７はボイド１６と一体化することにより先端部の応力
集中を解消する。その結果、たとえこのように、はんだ
端部から亀裂が発生したとしても、亀裂１７の進展を停
止させることができる。FIGS. 2A and 2B are enlarged sectional views of the solder portion when a crack is generated from the solder end,
As shown in FIG. 2A, when the crack 17 is generated from the end of the solder 14, the tip of the crack 17 has a sharp and sharp point, and local stress concentration occurs at the tip. The growth of the crack 17 is promoted. However, FIG.
As shown in (1), when the crack 17 reaches the void 16, the crack 17 is integrated with the void 16, thereby eliminating the stress concentration at the tip. As a result, even if a crack is generated from the solder end as described above, the growth of the crack 17 can be stopped.

【００１８】この様に、はんだ１４接合部において、は
んだ１４に濡れることのない材料で突起１５を形成した
ので、亀裂１７の発生・進展を抑制でき、熱的、電気的
に信頼性の高い半導体装置を製造することができる。As described above, since the projections 15 are formed of a material that does not wet the solder 14 at the joint portion of the solder 14, the generation and propagation of the crack 17 can be suppressed, and a semiconductor that has high thermal and electrical reliability can be obtained. The device can be manufactured.

【００１９】また、ここでは絶縁基板１１上にチップ７
が一個だけ実装されたパワーモジュールを例にとって説
明したが、一枚の絶縁基板１１上にチップ７が複数個実
装されている場合であっても良い。また、銅板１２上に
絶縁基板１１が一枚だけ実装されたパワーモジュールを
例にとって説明したが、一枚の銅板１２上に絶縁基板１
１が複数枚実装されていても良い。Here, the chip 7 is placed on the insulating substrate 11.
Has been described as an example of a power module in which only one chip 7 is mounted, but a case in which a plurality of chips 7 are mounted on one insulating substrate 11 may be used. Further, the power module in which only one insulating substrate 11 is mounted on the copper plate 12 has been described as an example, but the insulating substrate 1 is mounted on one copper plate 12.
A plurality of 1s may be mounted.

【００２０】また、絶縁基板１１の主材としてのセラミ
ックスとしてＡｌＮ８について説明をしたが、アルミ
ナ，窒化珪素等でもよい。また、金属板として銅板１２
について説明をしたが、表面処理を施したＡｌ，Ｃｕを
主体とする合金，表面処理を施したＡｌを主体とする合
金でも良い。また、はんだ１４としてすず−鉛系のはん
だを例に説明をしたが、Ｓｎ，Ｉｎ，Ｐｂ，Ｂｉを基と
するはんだであればよい。Although AlN8 has been described as a ceramic as a main material of the insulating substrate 11, alumina, silicon nitride or the like may be used. Further, a copper plate 12 is used as a metal plate.
Has been described, but an alloy mainly composed of Al or Cu subjected to surface treatment or an alloy mainly composed of Al subjected to surface treatment may be used. In addition, although the tin-lead-based solder has been described as an example of the solder 14, any solder based on Sn, In, Pb, or Bi may be used.

【００２１】実施の形態２． 図３はこの発明の実施の形態２のパワーモジュールの構
成を示したもので、図３（ａ）は断面図であり、図３
（ｂ）は突起部分の拡大断面図である。図において、１
５ａははんだに濡れないワイヤ片を用いた突起であり、
１８は突起１５ａと銅板１２とが金属接合によって固着
している金属接合部である。Embodiment 2 FIG. FIG. 3 shows a configuration of a power module according to Embodiment 2 of the present invention. FIG. 3 (a) is a sectional view, and FIG.
(B) is an enlarged sectional view of a projection part. In the figure, 1
5a is a projection using a wire piece that does not wet with solder,
Reference numeral 18 denotes a metal joint where the projection 15a and the copper plate 12 are fixed by metal joining.

【００２２】突起１５ａをワイヤ片とすると突起１５ａ
の高さはワイヤ径できまるので突起１５ａの高さを容易
に揃えることができる。したがって、はんだ１４接合部
は平坦性に優れるとともに厚さを容易に制御することが
でき、亀裂に対する信頼性と放熱性とを考慮した所望の
はんだ１４厚さを有する半導体装置を容易に製造するこ
とができる。When the projection 15a is a wire piece , the projection 15a
The height of the projections 15a can be easily adjusted because the height of the projection 15a can be easily adjusted. Therefore, the solder 14 joint has excellent flatness and the thickness can be easily controlled, and it is easy to manufacture a semiconductor device having a desired solder 14 thickness in consideration of reliability against cracks and heat dissipation. Can be.

【００２３】更に、実施の形態１では突起の固着につい
ては特に言及しなかったが、ここでは、突起１５ａは金
属接合部１８で銅板１２に金属接合されており、突起１
５ａとそれに伴うボイド１６とを所望の位置に形成する
ことができる。したがって、放熱性に影響を及ぼすボイ
ド１６の位置を確実にコントロールすることができ、チ
ップ７直下におけるボイド１６の発生を防止することが
でき、半導体装置の放熱性を向上させることができる。Further, in the first embodiment, no particular reference is made to the fixing of the projections. However, here, the projections 15a are metal-joined to the copper plate 12 at the metal joints 18,
5a and the accompanying voids 16 can be formed at desired positions. Therefore, the position of the void 16 that affects the heat radiation can be reliably controlled, the generation of the void 16 immediately below the chip 7 can be prevented, and the heat radiation of the semiconductor device can be improved.

【００２４】また、突起１５ａをＡｌ製のボンディング
ワイヤを用いて形成し、金属接合手段として超音波ボン
ディング技術を用いることにより、突起材料を容易に入
手でき、突起１５ａの固着作業性に優れ、簡単に、短時
間に、低コストで突起１５ａを作成することができる。
更に、突起１５ａの高さを決めるボンディングワイヤの
直径は放熱性および信頼性を考慮して５０〜４００ミク
ロン程度が良い。Further, by forming the projections 15a using an Al bonding wire and using an ultrasonic bonding technique as the metal bonding means, the projection material can be easily obtained, and the workability of fixing the projections 15a is excellent and easy. In addition, the projection 15a can be formed in a short time and at low cost.
Further, the diameter of the bonding wire that determines the height of the projection 15a is preferably about 50 to 400 microns in consideration of heat dissipation and reliability.

【００２５】図４は銅板上の突起を示した斜視図であ
る。図において、突起１５ａはＡｌ製のボンディングワ
イヤであり、銅板１２へは超音波ボンディング技術を用
いて金属接合部１８で固着させている。図に示すよう
に、、突起１５ａの金属接合部１８が２か所のものと１
か所のものが示されている。一般に、ワイヤ径の細いも
のは端部の変形を防ぐために両端の２か所で金属接合さ
れ、ワイヤ径の太いものは端部が変形することがないの
で中央の１か所で金属接合されることが多い。いずれの
接合方法でもワイヤ径が突起１５ａの高さとなり、はん
だ１４の厚さを制御する。FIG. 4 is a perspective view showing a projection on the copper plate. In the figure, a projection 15a is a bonding wire made of Al, and is fixed to the copper plate 12 at a metal bonding portion 18 using an ultrasonic bonding technique. As shown in the figure, the metal joint 18 of the protrusion 15a
Several places are shown. Generally, a thin wire has a metal joint at two places at both ends to prevent deformation of the end, and a thick wire has a metal joint at a central place since the end does not deform. Often. In any of the joining methods, the wire diameter becomes the height of the protrusion 15a, and the thickness of the solder 14 is controlled.

【００２６】図４では金属接合部１８が１か所または２
か所の突起１５ａが混在する場合について示したが、ど
ちらか一方のみでも良い。また、突起１５ａが４個の場
合について示したが、突起１５ａは３個以上でかつ一直
線に並ぶことがなければ幾つであっても良い。In FIG. 4, one or two metal joints 18 are provided.
Although the case where the protrusions 15a are mixed is shown, only one of them may be used. Although projections 15a is shown for the case of four, the projections 15 a may be a number unless be aligned and three or more.

【００２７】この様に、突起１５ａをワイヤで形成すれ
ば、突起１５ａの高さを容易に揃えることができ、はん
だ１４接合部は平坦性に優れるとともに厚さを容易に制
御することができる。また、突起１５ａを銅板１２上に
金属接合すれば突起１５ａに伴うボイド１６がチップ７
直下に位置することを避けることができ、放熱性を向上
させることができる。また、突起１５ａをＡｌ製のボン
ディングワイヤで形成し超音波ボンディング技術で金属
接合すれば、突起１５ａを簡単に、短時間に、低コスト
で作成することができる。As described above, if the protrusions 15a are formed of wires , the heights of the protrusions 15a can be easily adjusted, and the solder 14 can have excellent flatness and easily control the thickness. If the projection 15a is metal-bonded to the copper plate 12, the void 16 associated with the projection 15a will
It is possible to avoid being located immediately below, and it is possible to improve heat dissipation. Also, if the projections 15a are formed with Al bonding wires and are metal-bonded by an ultrasonic bonding technique, the projections 15a can be formed easily, quickly, and at low cost.

【００２８】実施の形態３． 図５はこの発明の実施の形態３のパワーモジュールの構
成を示したもので、図５（ａ）は断面図であり、図５
（ｂ）は突起部分の拡大断面図である。図に示すよう
に、ここではワイヤ片からなる突起１５ａは絶縁基板１
１に金属接合部１８を設けている。Embodiment 3 FIG. 5 shows a configuration of a power module according to Embodiment 3 of the present invention. FIG. 5A is a sectional view, and FIG.
(B) is an enlarged sectional view of a projection part. As shown in the figure, the projection 15a made of a wire piece here is the insulating substrate 1
1 is provided with a metal joint 18.

【００２９】ここで、一般に、絶縁基板１１と銅板１２
とのはんだ１４接合方法は、まず、所定の位置に開口部
を設けたはんだ印刷用スクリーンマスク（以下、印刷マ
スクと称す）を用いて、適量にフラックス（１０％ｗｔ
程度）を含有したはんだペーストを銅板１２の所定位置
に印刷、供給するはんだ印刷工程の後、この銅板１２上
のはんだ印刷位置に絶縁基板１１を載置する。その後、
はんだペーストを加熱溶融させ、はんだ接合を行う。Here, generally, the insulating substrate 11 and the copper plate 12
First, the solder 14 is bonded to an appropriate amount of flux (10% wt.) Using a screen mask for solder printing (hereinafter referred to as a print mask) having openings at predetermined positions.
After the solder printing step of printing and supplying a solder paste containing (about) the copper paste at a predetermined position on the copper plate 12, the insulating substrate 11 is placed at the solder printing position on the copper plate 12. afterwards,
The solder paste is heated and melted to perform solder joining.

【００３０】したがって、突起１５ａを絶縁基板１１へ
固着しておけば、銅板１２上には突起１５ａがないの
で、銅板１２上へのはんだ印刷工程において銅板１２上
へのスムーズなはんだ印刷が可能となり、絶縁基板１１
と銅板１２とのはんだ１４接合をより簡単に行うことが
できる。Therefore, if the projections 15a are fixed to the insulating substrate 11, since the projections 15a are not formed on the copper plate 12, smooth solder printing can be performed on the copper plate 12 in the solder printing step on the copper plate 12. , Insulating substrate 11
Bonding of the solder 14 with the copper plate 12 can be performed more easily.

【００３１】また、一般に、絶縁基板１１の方が銅板１
２よりも小さく、軽く、薄いので、突起１５ａを金属接
合する場合にも銅板１２よりも絶縁基板１１のほうが取
り扱いやすく、突起１５ａの固着をスムーズに行える。Also, in general, the insulating substrate 11 is
Since it is smaller, lighter, and thinner, the insulating substrate 11 is easier to handle than the copper plate 12 even when the projection 15a is metal-joined, and the projection 15a can be fixed smoothly.

【００３２】更に、図６はこの発明の実施の形態３のパ
ワーモジュールの断面図である。図に示すように、一枚
の銅板１２上に２個の絶縁基板１１を搭載しているが、
突起１５ａは絶縁基板１１に固着されているので、通常
のはんだ印刷工程において銅板１２上の２か所の所定位
置に同時にはんだを供給することができ、はんだ１４接
合方法が複雑になることがない。FIG. 6 is a sectional view of a power module according to Embodiment 3 of the present invention. As shown in the figure, two insulating substrates 11 are mounted on one copper plate 12,
Since the projections 15a are fixed to the insulating substrate 11, solder can be simultaneously supplied to two predetermined positions on the copper plate 12 in a normal solder printing process, and the solder 14 joining method does not become complicated. .

【００３３】実施の形態４． 上記実施の形態１〜３ではパワーモジュールの構造につ
いて説明を行なってきたが、ここではパワーモジュール
の製造方法について説明する。図７はこの発明の実施の
形態４のパワーモジュールのはんだ接合方法を示す工程
断面図である。図に示すように、はんだ印刷工程におい
て、銅板１２上にフラックスを含むはんだペースト１９
を印刷・供給後、フラックスを含まない板はんだ２０を
追加供給して所望のはんだ量となるようにはんだ供給量
を調節する。Embodiment 4 FIG. In the first to third embodiments, the structure of the power module has been described. Here, a method of manufacturing the power module will be described. FIG. 7 is a process sectional view showing a method for soldering a power module according to Embodiment 4 of the present invention. As shown in the drawing, in a solder printing process, a solder paste 19 containing a flux is placed on the copper plate 12.
Is printed and supplied, and the plate solder 20 containing no flux is additionally supplied to adjust the amount of supplied solder so that a desired amount of solder is obtained.

【００３４】この様にすれば、はんだ量とフラックス量
との両方のコントロールが可能となり、フラックスの過
剰供給によるボイドの発生を抑えることができる。した
がって、はんだ１４の厚さが厚くても平坦性の良い、ボ
イドの少ない良好なはんだ１４接合部を形成することが
できる。なお、ここでは板はんだについて説明を行った
が、糸はんだや棒はんだなどフラックスを含有しない固
形のはんだであれば良い。In this manner, both the amount of solder and the amount of flux can be controlled, and the occurrence of voids due to excessive supply of flux can be suppressed. Therefore, even if the thickness of the solder 14 is large, it is possible to form a good solder 14 joint having good flatness and few voids. Although the plate solder has been described here, any solid solder containing no flux, such as a thread solder or a bar solder, may be used.

【００３５】実施の形態５． 図８（ａ）〜（ｄ）はこの発明の実施の形態５のパワー
モジュールのはんだ接合方法を示す工程断面図である。
図にしたがって順次説明をする。まず、図８（ａ）に示
すように、パワーモジュールをはんだ１４の溶融温度以
上の温度で大気圧下におく。このとき、はんだ１４は溶
融状態となり、溶融はんだ１４ａを形成する。溶融はん
だ１４ａ中には無数の小径ボイド２１が発生している。Embodiment 5 FIG. 8 (a) to 8 (d) are process cross-sectional views illustrating a method for soldering a power module according to Embodiment 5 of the present invention.
The description will be made sequentially according to the drawings. First, as shown in FIG. 8A, the power module is placed under the atmospheric pressure at a temperature equal to or higher than the melting temperature of the solder 14. At this time, the solder 14 is in a molten state and forms a molten solder 14a. Innumerable small-diameter voids 21 are generated in the molten solder 14a.

【００３６】次に、図８（ｂ）に示すように、その後、
減圧を行うと、ボイド２１中の圧力が外気圧に比べて高
くなるためボイド２１は膨張し、近辺のボイド２１と合
併するなどして大型化する。また、ボイド２１は大型化
することによって流動性を増し溶融はんだ１４ａ中を徐
々に移動して周囲の外気に散逸する。Next, as shown in FIG.
When the pressure is reduced, the pressure in the void 21 becomes higher than the outside air pressure, so that the void 21 expands and becomes large due to merging with the void 21 in the vicinity. In addition, the voids 21 increase the fluidity due to the increase in size, gradually move in the molten solder 14a, and dissipate to the surrounding air.

【００３７】次に、図８（ｃ）に示すように、減圧状態
を暫く続けると、ボイド２１はほとんど周囲の外気に散
逸してしまい、突起１５の周囲のボイド１６とほんの僅
かのボイド２１とだけになる。Next, as shown in FIG. 8C, if the depressurized state is continued for a while, the voids 21 are almost scattered to the surrounding air, and the voids 16 around the projections 15 and only a few voids 21 are formed. Only.

【００３８】次に、図８（ｄ）に示すように、圧力を大
気圧に戻す。溶融はんだ１４ａ内部の圧力が外気圧に比
べて小さくなるため突起１５の周囲に存在するボイド１
６も溶融はんだ１４ａ中に僅かに残ったボイド２１も収
縮し、小さくなる。その後、溶融はんだ１４ａを凝固さ
せることによって絶縁基板１１と銅板１２とのはんだ１
４接合を行う。Next, as shown in FIG. 8D, the pressure is returned to the atmospheric pressure. Since the pressure inside the molten solder 14a is smaller than the outside air pressure, the void 1 existing around the projection 15
6 and the void 21 slightly remaining in the molten solder 14a also shrink and become smaller. Thereafter, the molten solder 14a is solidified to form a solder 1 between the insulating substrate 11 and the copper plate 12.
Four joints are performed.

【００３９】以上のようにはんだ１４接合工程を行え
ば、突起１５を有するはんだ１４接合部においてボイド
１６，２１は充分小さくなり放熱性に悪影響を及ぼすこ
とがない。When the solder 14 bonding step is performed as described above, the voids 16 and 21 at the solder 14 bonded portion having the protrusion 15 are sufficiently small, and do not adversely affect heat radiation.

【００４０】なお、上記実施の形態４と実施の形態５と
を併せて行えば各々の実施の形態の効果が相乗され、よ
り効果的にボイドの発生を抑制することができる。If the fourth embodiment and the fifth embodiment are combined, the effects of the respective embodiments are synergistic, and the generation of voids can be suppressed more effectively.

【００４１】[0041]

【発明の効果】以上のようにこの発明によれば、突起が
はんだに濡れないＡｌからなり、突起 ははんだ接合部の
金属板側に金属接合によって固着されている、または、
はんだ接合部の絶縁基板側に金属接合によって固着され
ているとともに、突起の周囲とはんだ接合部との間にボ
イドが形成されるので、突起の周囲のボイドにより、は
んだが滑らかなフィレット形状を作り、突起とはんだと
の接触界面において金属間化合物層や角部を形成するこ
とがなく、突起の部分が亀裂発生の起点となることがな
い。また、はんだ端部から亀裂が発生しても突起周囲の
ボイドで亀裂の進展を停止させることができる効果があ
る。また、突起がはんだ接合部の金属板側に金属接合に
よって固着している場合には、突起を任意の位置におく
ことができ、突起に伴うボイドが半導体チップ直下に位
置することを避けることができ、放熱性を向上させるこ
とができる効果がある。また、突起がはんだ接合部の絶
縁基板側に金属接合によって固着している場合には、金
属板に突起が無く、金属板上へのはんだ印刷工程がスム
ーズにでき、絶縁基板と金属板とのはんだ接合をより簡
単に行うことができるという効果がある。 According to the above manner the present invention according to the present invention, the projection is made of Al not wet the solder, the protrusion of the solder joint
Fixed to the metal plate side by metal bonding, or
Secured by metal bonding to the insulating substrate side of the solder joint
Between the periphery of the protrusion and the solder joint.
Since voids are formed around the protrusions, the solder forms a smooth fillet shape, forming no intermetallic compound layer or corners at the contact interface between the protrusions and the solder, and the protrusions are cracked. There is no starting point for occurrence. Further, even if a crack is generated from the solder end, there is an effect that the growth of the crack can be stopped by the void around the protrusion. In addition, the protrusion is used for metal bonding to the metal plate side of the solder joint.
Therefore, if it is fixed, place the protrusion at any position
The voids associated with the protrusions are located just below the semiconductor chip.
Can be avoided to improve heat dissipation.
There is an effect that can be. In addition, the protrusions
If it is fixed to the edge substrate by metal bonding,
There is no protrusion on the metal plate and the solder printing process on the metal plate is smooth
Solder joint between the insulating substrate and the metal plate.
The effect is that it can simply be done.

【００４２】また、突起がはんだに濡れないワイヤ片で
あって、上記ワイヤ径によってはんだ接合部の厚さを規
制するようにしたので、突起の周囲にボイドがフィレッ
ト形状を作り、突起とはんだとの接触界面において金属
間化合物層や角部を形成することがなく、突起の部分が
亀裂発生の起点となることがない。また、はんだ端部か
ら亀裂が発生しても突起周囲のボイドで亀裂の進展を停
止させることができる。更に、突起の高さはワイヤ径で
きまるので突起の高さを容易に揃えることができ、はん
だ接合部は平坦性に優れるとともに厚さを容易に制御す
ることができ、亀裂に対する信頼性をより高めることが
できる効果がある。Further, since the protrusion is a piece of wire that does not wet with the solder, and the thickness of the solder joint is regulated by the wire diameter , a void forms a fillet shape around the protrusion, and the protrusion and the solder are separated. No intermetallic compound layer or corners are formed at the contact interface of, and the projections do not serve as starting points for crack generation. Also, even if a crack is generated from the solder end, the growth of the crack can be stopped by the void around the protrusion. Furthermore, since the height of the protrusions can be adjusted to the wire diameter, the heights of the protrusions can be easily adjusted, and the solder joints have excellent flatness and the thickness can be easily controlled, so that the reliability against cracks can be improved. There is an effect that can be increased.

【００４３】また、はんだに濡れないワイヤ片が直径５
０〜４００ミクロンのＡｌのボンディングワイヤである
ので、放熱性および信頼性に最適なはんだの厚さを容易
に決定することができるとともに、突起材料を容易に入
手でき、突起の固着作業性に優れ、簡単に、短時間に、
低コストで突起を作成することができる効果がある。The wire piece which does not get wet with the solder has a diameter of 5 mm.
Since it is an Al bonding wire of 0 to 400 microns, it is possible to easily determine the optimum solder thickness for heat dissipation and reliability, and to easily obtain a projection material and to have excellent workability of fixing the projection. Easily, in a short time,
There is an effect that projections can be formed at low cost.

【００４４】また、金属板上または上記絶縁基板上に金
属接合により固着されたはんだに濡れないＡｌの突起を
形成する工程を備え、はんだ接合する工程が、大気圧下
ではんだを溶融し溶融はんだを形成する工程と、上記溶
融はんだを減圧した後に、上記溶融はんだを大気圧に戻
すことにより、上記突起の周囲と上記溶融はんだとの間
に形成されるボイドを収縮して小さくする工程と、上記
溶融はんだを凝固する工程からなるので、はんだ接合部
において放熱性に悪影響を及ぼす可能性のある突起の周
囲に形成されるボイドの発生を極力抑えることができる
効果がある。In addition, gold is placed on a metal plate or on the insulating substrate.
Al projections that do not wet the solder fixed by metal bonding
Comprising the step of forming, a step of solder joint, a step of forming a molten solder to melt the solder under atmospheric pressure, the pressure was reduced to the molten solder, by returning the molten solder to atmospheric pressure, the projections Between the surroundings and the above molten solder
A step of reducing by contracting the voids formed, since the step of solidifying the molten solder, the circumferential projections that may harm the heat radiation at the solder joint
There is an effect that generation of voids formed in the surrounding can be suppressed as much as possible.

【図面の簡単な説明】[Brief description of the drawings]

【図１】 この発明の実施の形態１のパワーモジュール
を示した斜視図および断面図である。FIG. 1 is a perspective view and a sectional view showing a power module according to a first embodiment of the present invention.

【図２】 はんだ部分の拡大断面図である。FIG. 2 is an enlarged sectional view of a solder portion.

【図３】 この発明の実施の形態２のパワーモジュール
の構成を示した断面図および拡大断面図である。FIG. 3 is a cross-sectional view and an enlarged cross-sectional view illustrating a configuration of a power module according to Embodiment 2 of the present invention.

【図４】 銅板上の突起を示した斜視図である。FIG. 4 is a perspective view showing a projection on a copper plate.

【図５】 この発明の実施の形態３のパワーモジュール
の構成を示した断面図および拡大断面図である。FIG. 5 is a cross-sectional view and an enlarged cross-sectional view illustrating a configuration of a power module according to Embodiment 3 of the present invention.

【図６】 この発明の実施の形態３のパワーモジュール
の断面図である。FIG. 6 is a sectional view of a power module according to Embodiment 3 of the present invention.

【図７】 この発明の実施の形態４のパワーモジュール
のはんだ接合方法を示す工程断面図である。FIG. 7 is a process cross-sectional view showing a power module soldering method according to Embodiment 4 of the present invention;

【図８】 この発明の実施の形態５のパワーモジュール
のはんだ接合方法を示す工程断面図である。FIG. 8 is a process cross-sectional view showing a soldering method for a power module according to Embodiment 5 of the present invention.

【図９】 従来の半導体装置のはんだ接合部を示す断面
図である。FIG. 9 is a cross-sectional view showing a solder joint of a conventional semiconductor device.

【図１０】 従来の半導体リードフレームのダイパッド
を示す斜視図である。FIG. 10 is a perspective view showing a die pad of a conventional semiconductor lead frame.

【図１１】 従来の半導体装置の突起台とはんだとの接
触部近傍の拡大断面図である。FIG. 11 is an enlarged cross-sectional view of the vicinity of a contact portion between a projection base and solder of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

７ 半導体チップ、８ 窒化アルミ、９，１０ 銅製パ
ターン、１１ 絶縁基板、１２ 銅板、１３ はんだ、
１４ すず−鉛系のはんだ、１４ａ 溶融はんだ、１
５，１５ａ 突起、１６，２１ ボイド、１８ 金属接
合部、１９ フラックスを含むはんだペースト、２０
フラックスを含まない板はんだ。7 semiconductor chip, 8 aluminum nitride, 9,10 copper pattern, 11 insulating substrate, 12 copper plate, 13 solder,
14 tin-lead solder, 14a molten solder, 1
5, 15a protrusion, 16, 21 void, 18 metal joint, 19 solder paste containing flux, 20
Sheet solder without flux.

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平６−216167（ＪＰ，Ａ) 特開 平９−8168（ＪＰ，Ａ) 特開 平７−249632（ＪＰ，Ａ) 特開 平４−120741（ＪＰ，Ａ) 特開 平９−148347（ＪＰ，Ａ) 特開 平６−152094（ＪＰ，Ａ) 特開 平６−155081（ＪＰ，Ａ) 実開 昭61−86940（ＪＰ，Ｕ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/52 H01L 21/60 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-6-216167 (JP, A) JP-A-9-8168 (JP, A) JP-A-7-249632 (JP, A) JP-A-4- 120741 (JP, A) JP-A-9-148347 (JP, A) JP-A-6-152094 (JP, A) JP-A-6-155081 (JP, A) Japanese Utility Model Application Laid-Open No. 61-86940 (JP, U) (58) Field surveyed (Int. Cl. 7 , DB name) H01L 21/52 H01L 21/60

Claims (4)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 金属板上に、セラミックスからなる主材
の両面にはんだ接合可能な導体層を有する絶縁基板を備
え、上記絶縁基板上に半導体チップを備え、上記絶縁基
板と金属板とがはんだ接合部を介して接合されており、
上記はんだ接合部に上記はんだ接合部の厚さを規制する
複数個の突起が設けられている半導体装置において、 上記突起ははんだに濡れないＡｌからなり、上記突起は
上記はんだ接合部の上記金属板側に金属接合によって固
着されている、または、上記はんだ接合部の上記絶縁基
板側に金属接合によって固着されているとともに、上記
突起の周囲と上記はんだ接合部との間にボイドが形成さ
れることを特徴とする半導体装置。 An insulating substrate having a conductor layer which can be soldered on both sides of a main material made of ceramics is provided on a metal plate, a semiconductor chip is provided on the insulating substrate, and the insulating substrate and the metal plate are soldered. Are joined via a joint,
In a semiconductor device in which a plurality of protrusions for regulating the thickness of the solder joint are provided at the solder joint, the protrusion is made of Al that is not wetted by solder, and the protrusion is
The solder joint is fixed to the metal plate side by metal bonding.
Or the insulating base of the solder joint
It is fixed to the plate side by metal bonding and
A void is formed between the periphery of the protrusion and the solder joint.
A semiconductor device characterized in that: 【請求項２】 突起がはんだに濡れないワイヤ片であっ
て、上記ワイヤ径によってはんだ接合部の厚さを規制す
るようにしたことを特徴とする請求項１記載の半導体装
置。2. The semiconductor device according to claim 1, wherein the protrusion is a piece of wire that does not wet the solder, and the thickness of the solder joint is regulated by the wire diameter . 【請求項３】 はんだに濡れないワイヤ片が直径５０〜
４００ミクロンのＡｌのボンディングワイヤであること
を特徴とする請求項２記載の半導体装置。3. A wire piece which does not wet with solder has a diameter of 50 to 50 mm.
3. The semiconductor device according to claim 2, wherein the bonding device is an Al bonding wire of 400 microns. 【請求項４】 金属板上に、セラミックスからなる主材
の両面にはんだ接合可能な導体層を有する絶縁基板をは
んだ接合する工程と、上記絶縁基板上に半導体チップを
搭載する工程とを備えた半導体装置の製造方法におい
て、上記金属板上または上記絶縁基板上に金属接合により固
着されたはんだに濡れないＡｌの突起を形成する工程を
備え、 上記はんだ接合する工程が、大気圧下ではんだを
溶融し溶融はんだを形成する工程と、上記溶融はんだを
減圧した後に、上記溶融はんだを大気圧に戻すことによ
り、上記突起の周囲と上記溶融はんだとの間に形成され
るボイドを収縮して小さくする工程と、上記溶融はんだ
を凝固する工程からなることを特徴とする半導体装置の
製造方法。4. A method comprising the steps of: soldering an insulating substrate having a conductor layer that can be soldered on both surfaces of a main material made of ceramics on a metal plate; and mounting a semiconductor chip on the insulating substrate. In the method of manufacturing a semiconductor device, the semiconductor device is fixed on the metal plate or the insulating substrate by metal bonding.
The process of forming Al projections that do not wet the attached solder
Provided, said solder joint, a step of forming a molten solder to melt the solder under atmospheric pressure, the pressure was reduced to the molten solder, by returning the molten solder to atmospheric pressure, around the projections and the Formed between the molten solder
A method of shrinking the voids to reduce the size of the voids, and a step of solidifying the molten solder.
JP35121197A 1997-12-19 1997-12-19 Semiconductor device and method of manufacturing the same Expired - Lifetime JP3347279B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP35121197A JP3347279B2 (en) 1997-12-19 1997-12-19 Semiconductor device and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP35121197A JP3347279B2 (en) 1997-12-19 1997-12-19 Semiconductor device and method of manufacturing the same

Publications (2)

Publication Number Publication Date
JPH11186331A JPH11186331A (en) 1999-07-09
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US20070216026A1 (en) * 2006-03-20 2007-09-20 Adams Zhu Aluminum bump bonding for fine aluminum wire
FR2901347B1 (en) * 2006-05-22 2008-07-18 Valeo Vision Sa THERMAL DISSIPATING COMPONENT AND DIODE LIGHTING AND / OR SIGNALING DEVICE EQUIPPED WITH SUCH A COMPONENT
JP2011228604A (en) * 2010-04-23 2011-11-10 Honda Motor Co Ltd Manufacturing method of circuit board and circuit board
JP2014165255A (en) * 2013-02-22 2014-09-08 Toyota Motor Corp Semiconductor device
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JP6165025B2 (en) * 2013-10-31 2017-07-19 三菱電機株式会社 Semiconductor module
JP6242328B2 (en) * 2014-12-02 2017-12-06 三菱電機株式会社 Semiconductor device
JP6487122B2 (en) * 2016-06-14 2019-03-20 三菱電機株式会社 Power semiconductor device
JP6685470B2 (en) 2017-03-30 2020-04-22 三菱電機株式会社 Semiconductor device, manufacturing method thereof, and power conversion device
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JP6641524B1 (en) * 2018-02-26 2020-02-05 新電元工業株式会社 Method for manufacturing semiconductor device
JP6885522B1 (en) * 2020-09-03 2021-06-16 三菱電機株式会社 Semiconductor device, power conversion device and manufacturing method of semiconductor device
JPWO2023214450A1 (en) * 2022-05-02 2023-11-09

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