JP3216620B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a semiconductor chip mounted on a package substrate, and more particularly to a semiconductor device having a plated heat sink (PHS) structure in which a metal film is formed on the back surface of the semiconductor chip to enhance heat dissipation. About.

[0002]

2. Description of the Related Art With the recent increase in output power of semiconductor devices, reduction in electrical characteristics and reliability due to temperature rise due to heat generated in semiconductor chips is becoming a serious problem. For this reason, it is one of the important factors to suppress such a rise in temperature. Particularly, in a semiconductor device using a GaAs substrate having poor heat conduction characteristics, the thickness of the GaAs substrate is reduced and a ground electrode is provided on the back surface. PHS for heat dissipation
In this case, a method of improving the heat radiation characteristics by providing an Au layer having a two-layer structure of GaAs / Au is adopted. Figure 4 shows PH
FIG. 3 is a diagram showing an example of a semiconductor device having an S structure. The semiconductor chip 1 is a P-type semiconductor device having an Au layer 12 provided on a lower surface of a GaAs substrate 11.
The semiconductor chip 1 has an HS structure, and the semiconductor chip 1 is mounted on a mount substrate 2B made of a metal plate such as Cu by a solder 3 such as AuSn.
Mount on top. Further, lead terminals 5 are supported on the mount substrate 2B by an insulating plate 4, and the electrode pads 13 of the semiconductor chip 1 and the lead terminals 5 are electrically connected by bonding wires 6. Therefore, in this semiconductor device, heat generated in the semiconductor chip 1 is quickly heated to the mount substrate 2B via the Au layer 12 having high thermal conductivity, and is radiated with high efficiency from the surface of the mount substrate 2B. And the temperature rise of the semiconductor device can be suppressed.

[0003]

However, this P
In the semiconductor device having the HS structure, the following problem occurs because the semiconductor chip 1 has a two-layer structure of a semiconductor (GaAs substrate 11) and a metal (Au layer 12). That is, when looking at the method of manufacturing the semiconductor device described above, first, as shown in FIG.
A semiconductor chip 1 having a two-layer structure of
The mounting substrate 2B made of a single-layer substrate made of an alloy mainly containing u or Cu is heated. By this heating, FIG.
As shown in (b), the mount substrate 2B having a single-layer substrate structure remains flat, but since the semiconductor chip 1 has a two-layer structure, the bimetal effect accompanying the difference in the coefficient of thermal expansion between GaAs and Au causes The semiconductor chip 1 has an upwardly concave warpage. Next, as shown in FIG.
The semiconductor chip 1 is pressed on the AuSn solder 3 after the Sn3 is placed on the mount substrate 2B and melted. At this time, the thickness of the AuSn solder 3 varies depending on the location due to the warpage of the semiconductor chip 1 described above. Then, when cooling is performed in this state, the AuSn solder 3 is solidified while maintaining the thickness distribution, so that the warpage of the semiconductor chip 1 does not return. Therefore, in the completed semiconductor device, the mount substrate 2B is flat as shown in FIG.
The semiconductor chip 1 has a configuration in which warpage is maintained.

For this reason, in a semiconductor device in which the semiconductor chip is warped, the mark detection rate caused by the deviation of the light reflection direction due to the inclination of the surface of the semiconductor chip in the next wire bonding step is reduced. A drop occurs.
In addition, since the electrode pad is inclined, the bonding tool is not brought into contact with the electrode pad surface with an appropriate force, and there is a problem that a bonding failure of the bonding wire occurs. Furthermore, since the coefficient of thermal expansion of a mount substrate usually made of metal is larger than the coefficient of thermal expansion of a semiconductor, here, a semiconductor chip made of GaAs, a compressive stress is applied to the semiconductor chip from the mount substrate during cooling after mounting.
There is also a problem that the reliability of the semiconductor device is reduced, such as cracking or chipping of the semiconductor chip.

In order to prevent such a warpage of the semiconductor chip, the technique described in Japanese Patent No. 2629653 discloses a structure in which two opposing sides of the semiconductor chip are pressed against a mount substrate by a support. However, this structure requires a separate support member, which is an obstacle to miniaturization and cost reduction of the semiconductor device. Further, in Japanese Patent No. 2757805, the PHS structure formed on the lower surface of the semiconductor chip is formed in a plurality of layers of different metals to prevent the warpage of the semiconductor chip itself. In addition, there is a problem that the number of manufacturing steps increases and the price becomes high.

One of the objects of the present invention is to provide a semiconductor device capable of preventing the occurrence of warpage in a semiconductor chip even when a semiconductor chip having a PHS structure is mounted on a mounting substrate and enabling the manufacture of a highly reliable semiconductor device. To provide.

[0007]

According to the present invention, there is provided a semiconductor device in which a semiconductor chip having a PHS structure in which a metal layer is formed on the back surface of a semiconductor layer is mounted on a mounting substrate.
At least a part of the mount substrate has a multilayer structure made of materials having different coefficients of thermal expansion, and is configured such that a warp when heated matches a warp when the semiconductor chip is heated. . Here, the mount substrate has a multilayer structure in which the entire area of the plane or a portion extending along the long side of the semiconductor chip to be mounted is formed. For example, in the present invention, the semiconductor chip is a PHS in which an Au layer is integrally formed on the back surface of a GaAs substrate.
And the mounting substrate has A
The structure is such that the l layer or the W layer is laminated in a part of the region.

In the semiconductor device of the present invention, the mount substrate has a multilayer structure having different coefficients of thermal expansion, and by adjusting the thickness of each layer, a warp matched with the semiconductor chip is generated on the mount substrate by the bimetal effect. . When the semiconductor chip is mounted in this state, the solder is formed with a uniform thickness because the warpage with the mounting substrate is matched. For this reason, when cooled to room temperature, the solder is solidified and the warpage is eliminated, and the mount substrate becomes flat and the semiconductor chip becomes flat. Accordingly, in the next bonding step, the mark detection rate caused by the inclination of the surface of the semiconductor chip is reduced, and the bonding failure of the bonding wire caused by the inclination of the electrode pad is improved.

[Detailed Description of the Invention] Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a perspective view of a semiconductor device according to a first embodiment of the present invention, which is an example having the same configuration as the semiconductor device shown in FIG. The semiconductor chip 1 has a PHS structure, and has GaAs as a microwave high-power element.
Although it is configured using the s substrate 11, the GaAs substrate 1
1 is thinly polished, and an Au layer 12 serving as a PHS for heat dissipation is provided on the lower surface thereof, also serving as a ground electrode. Also, Ga
A plurality of electrode pads 13 are provided on the surface of the As substrate 11. On the other hand, the mount substrate 2 is formed as a multilayer metal structure in which metals having different coefficients of thermal expansion are stacked. Here, an Al (aluminum) layer 22 is integrally laminated below the Cu (copper) layer 21. Then, the semiconductor chip 1 is mounted on the surface of the mount substrate 2 with the AuSn solder 3. Lead terminals 5 are supported on the mount substrate 2 via an insulating plate 4, and the electrode pads 13 of the semiconductor chip 1 and the lead terminals 5 are electrically connected by bonding wires 6.

FIG. 2 is a diagram showing a method of manufacturing the semiconductor device of FIG. 1 in the order of steps. First, as shown in FIG.
PHS in which Au layer 12 is integrally formed on the lower surface of s substrate 11
A semiconductor chip 1 having a structure and an Al layer 2 under the Cu layer 21
A mounting substrate 2 having a two-layer structure in which the mounting substrate 2 is integrally formed is prepared. Then, as shown in FIG.
And the mounting substrate 2 at the melting temperature of AuSn (about 280).
C.) and heated to about 300.degree. At this time, the semiconductor chip 1 is made of GaAs and A
Due to the difference in coefficient of thermal expansion from u, warpage occurs due to the bimetal effect. On the other hand, the mounting substrate 2 is made of Cu and A
1 and a warp occurs due to a bimetal effect due to a difference in thermal expansion coefficient between the two. Here, the coefficient of thermal expansion of Cu constituting the mount substrate 2 is about 17E-6 / K.
, And the coefficient of thermal expansion of Al is about 23.7E-6 / K. On the other hand, the thermal expansion coefficient of GaAs constituting the semiconductor chip 1 is about 5.9E-6 / K, and the thermal expansion coefficient of Au is about 14.2E-6 / K. Therefore, the semiconductor chip 1 and the mount substrate 2 each have a warp that is concave upward due to the bimetal effect. At this time, C
By appropriately selecting the thicknesses of the u layer 21 and the Al layer 22,
The difference between the curvature radius of the semiconductor chip 1 and the curvature radius of the back surface (Au surface) of the semiconductor chip 1 and the curvature radius of the front surface (Cu surface) of the mount substrate 2 is determined by the AuSn. The thickness is set to be equal to the thickness of the solder 3.

Then, as shown in FIG. 2C, when the AuSn solder 3 is placed on the mount substrate 2, the AuSn solder 3 is melted by the heat of the mount substrate 2, and after the AuSn solder 3 is melted, the AuSn solder 3 is melted. By pressing the semiconductor chip 1 on the solder 3, the semiconductor chip 1 is mounted on the surface of the mounting substrate 2, and the two are integrated. At this time, as described above, since the difference between the radius of curvature of the Au surface of the semiconductor chip 1 and the radius of curvature of the Cu surface of the mount substrate 2 is equal to the thickness of the AuSn solder 3,
The semiconductor chip 1 and the mounting substrate 2 are mounted in a state where the distance between them is kept uniform, in other words, in a state where the AuSn solder 3 is kept in a uniform thickness. By cooling the semiconductor chip 1 and the mounting substrate 2, the warpage of the semiconductor chip 1 and the mounting substrate 2 returns to a flat state as shown in FIG. 2D, but at this time, the thickness of the AuSn solder 3 is reduced. Because of the uniformity, the warpage of the semiconductor chip 1 is parallel to the mount substrate 2 and becomes flat. Normally, since the thickness of the mount substrate 2 is thicker than the thickness of the semiconductor chip 1 from the point of strength, the effect of the semiconductor chip 1 on the flatness of the mount substrate 2 after cooling is small.

As described above, after the semiconductor chip 1 is mounted, the surface of the semiconductor chip 1 is in a flat state. Therefore, in the next wire bonding step, the mark caused by the inclination of the surface of the semiconductor chip 1 is a factor. Adhesion failure of the bonding wire 6 caused by a decrease in the detection rate and an inclination of the surface of the electrode pad 13 is improved. Further, usually, the thermal expansion coefficient of the mounting substrate 2 is GaAs.
Since s is larger than the thermal expansion coefficient of the main semiconductor chip 1,
Compressive stress is applied to the semiconductor chip 1 during cooling, which may cause a decrease in reliability. However, since compressive stress is generated on the concave side surface of the mount substrate 2 along the upper concave portion during heating, As a result, the expansion due to thermal expansion is alleviated, the compressive stress applied to the semiconductor chip 1 during cooling can be alleviated, and the above-described problem can be suppressed.
Therefore, in the semiconductor device of the first embodiment, a highly reliable semiconductor device can be obtained.

FIG. 3 is a perspective view of a second embodiment of the present invention, and portions equivalent to those in FIG. 1 are denoted by the same reference numerals. In the first embodiment, the entire mounting substrate is made of Cu and A
Although it is configured as a two-layer structure of l, only the part that determines the warpage of the mount substrate may be formed as a two-layer structure. Normally, a semiconductor chip for high output has a configuration in which basic FETs are connected in parallel, so that it is a horizontally long chip, and warping in the long side direction often becomes a problem. Therefore, in the second embodiment, a W / Cu two-layer structure in which a tungsten (W) layer 23 is laminated on the surface side of the Cu layer 21 is adopted as the mount substrate 2A. It is formed only in the region along both sides. That is, when the entire area of the mount substrate 2 has a two-layer structure of W / Cu, W
However, even if another solder is applied, the thermal conductivity of W is poor, so that sufficient heat radiation characteristics cannot be obtained. Therefore, in the second embodiment, the mounting substrate 2A is formed of the W layer 23 and the Cu layer 21 so as to be continuous in the long side direction of the semiconductor chip 1 in a portion other than the region where the semiconductor chip 1 having the PHS structure is mounted. 2
On the other hand, the mounting region of the semiconductor chip 1 has a single-layer structure of the Cu layer 21 instead of the two-layer structure. In FIG. 3, a lead terminal 5 is supported on a mount substrate 2A via an insulating plate 4, and it is possible that the lead terminal 5 and the electrode pad 13 of the semiconductor chip 1 are electrically connected by a bonding wire 6. This is the same as the first embodiment.

In this configuration, the coefficient of thermal expansion of W is about 4.5E
−6 / K, and the coefficient of thermal expansion of Cu is about 17E-6 / K.
K, the area of the W / Cu two-layer structure is C
In the case where the area is sufficiently larger than the area of the single-layer region of u, FIG.
By mounting the semiconductor chip 1 on the mounting substrate 2A by the mounting method described in (1), there is an effect of flattening the semiconductor chip 1 in the long side direction of the semiconductor chip 1 as in the first embodiment. Although the semiconductor chip 1 slightly warps in the short side direction, since the length of the side is short, the inclination of the semiconductor chip surface and the inclination of the electrode pad due to the warp are slight, and do not cause any particular problem. In order to prevent warpage in the short side direction, the mounting substrate 2 shown in FIG.
Both ends of the single-layer region of A may have a two-layer structure of W / Cu. In the second embodiment, without considering the adhesiveness between the semiconductor chip 1 and the mounting substrate 2A and the heat radiation characteristics,
A material having a two-layer structure can be selected only for controlling the warpage of the semiconductor chip, and the degree of freedom in design can be increased.

Here, although no particular mention is made of the layer thicknesses of the materials having different coefficients of thermal expansion constituting the two-layer structure of the mount substrate in the first and second embodiments, this is due to the warpage occurring in the semiconductor chip. The layer thickness may be calculated according to the amount. Also, the material constituting the mounting substrate is
The material is not limited to metal, and any material having good heat conductivity can be adopted. Further, the mount substrate is not limited to two layers, and may have a configuration of three or more layers.

[0016]

As described above, according to the present invention, a mounting substrate for mounting a semiconductor chip having a PHS structure has a multilayer structure at least partially formed of materials having different coefficients of thermal expansion and is heated. Since the warpage at the time is configured to match the warpage when the semiconductor chip is heated, after mounting in a heated state, the surface of the semiconductor chip is flattened together with the mount substrate, In the next step, mark detection and bonding wire connection can be suitably performed, and a highly reliable semiconductor device can be obtained. In addition, the above-described effect can be enhanced by forming the entire area of the mounting substrate in a multilayer structure, and the portion extending along the long side of the semiconductor chip is formed in a multilayer structure, so that the semiconductor chip has a multilayer structure. The above-described effects can be obtained without impairing the mountability.

[Brief description of the drawings]

FIG. 1 is an external perspective view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a view showing a mounting step of a semiconductor chip in the method of manufacturing the semiconductor device of FIG. 1 in the order of steps;

FIG. 3 is an external perspective view of a semiconductor device according to a second embodiment of the present invention.

FIG. 4 is an external perspective view of a conventional semiconductor device.

FIG. 5 is a view showing a semiconductor chip mounting step in a conventional method of manufacturing a semiconductor device in the order of steps.

[Explanation of symbols]

 Reference Signs List 1 semiconductor chip 2 mount substrate 2A mount substrate 2B mount substrate 3 AuSn solder 4 insulating plate 5 lead terminal 6 bonding wire 11 GaAs substrate 12 Au layer 13 electrode pad 21 Cu layer 22 Al layer 23 W layer

Claims (7)

(57) [Claims] 1. A semiconductor device comprising a metal layer formed on a back surface of a semiconductor layer.
In a semiconductor device in which a semiconductor chip having an HS structure is mounted on a mount substrate, at least a part of the mount substrate has a multilayer structure made of a material having a different coefficient of thermal expansion, and the semiconductor chip is warped when heated. A semiconductor device, which is configured to match warpage when heated. 2. The semiconductor device according to claim 1, wherein the mount substrate has a multilayer structure over the entire plane. 3. The semiconductor device according to claim 1, wherein a portion of the mount substrate extending along a long side of the semiconductor chip to be mounted has a multilayer structure. Wherein said semiconductor chip is an Au layer is formed integrally on the rear surface of the GaAs substrate, the mounting substrate is a semiconductor device according to claim 2 in which an Al layer is laminated on the entire area of the Cu substrate. 5. The semiconductor device according to claim 1, wherein the semiconductor chip is a back surface of a GaAs substrate.
And an Au layer is integrally formed, and the mounting substrate is
4. A W layer is laminated on a partial region of the Cu substrate.
3. The semiconductor device according to claim 1. 6. The semiconductor chip is mounted on the mount substrate by solder, and a difference between a curvature radius of the semiconductor chip when warped and a curvature radius of the mount substrate when warped is equal to the thickness of the solder. Claims 1 to 5
The semiconductor device according to any one of the above. Wherein said semiconductor chip electrode pads on the surface is arranged, the electrode pads as described in any one of the claims 1 to be electrically connected by bonding wires to the lead terminal mounted on the mounting substrate 6 Semiconductor device.