JPH10107176A - Method and structure for connecting electronic part and substrate, and solder bump forming method in them - Google Patents

Method and structure for connecting electronic part and substrate, and solder bump forming method in them

Info

Publication number
JPH10107176A
JPH10107176A JP8256416A JP25641696A JPH10107176A JP H10107176 A JPH10107176 A JP H10107176A JP 8256416 A JP8256416 A JP 8256416A JP 25641696 A JP25641696 A JP 25641696A JP H10107176 A JPH10107176 A JP H10107176A
Authority
JP
Japan
Prior art keywords
solder
substrate
wiring
electronic component
wiring pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8256416A
Other languages
Japanese (ja)
Inventor
Hiroshi Okada
浩志 岡田
Haruo Sankai
春夫 三階
Hideo Nakamura
中村  秀男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Plant Technologies Ltd
Original Assignee
Hitachi Techno Engineering Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Techno Engineering Co Ltd filed Critical Hitachi Techno Engineering Co Ltd
Priority to JP8256416A priority Critical patent/JPH10107176A/en
Publication of JPH10107176A publication Critical patent/JPH10107176A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/12Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
    • H05K3/1216Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns by screen printing or stencil printing
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • H05K3/3436Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components

Landscapes

  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To eliminate poor connection by, even an electronic part is bent, perfectly and electrically connecting the wiring pad of the electronic part and the wiring pattern of a substrate, individually, through a solder. SOLUTION: In order that a wiring pad 2 and a wiring pattern 10 are individually perfectly connected each other, a solder 16 is supplied whose amount is almost proportional to the curvature of a BGA(ball grid array) 8 and/or substrate 9, and the wed area of the solder 16 when the wiring pad 2 and/or wiring pattern 10 are heated and melted. As a result, poor connection is eliminated while the wiring pad 2 of the BGA 8 and the wiring pattern 10 of the substrate 9 are, through the solder 16, perfectly, electrically, and individually connected together.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、電子部品と基板と
の接続構造及びその接続方法、並びにその接続構造及び
接続方法におけるはんだバンプ形成法に係り、特に、電
子部品(BGA(Ball Grid Array)やCSP(Chip Si
ze Package)などのパッケ−ジ形態の表面実装型電子部
品)の配線パッドと基板(電子部品を搭載するプリント
配線基板など)の配線パターンとがはんだを介して個々
に電気的に完全に接続されていて接続不良が無い電子部
品と基板との接続構造及びその接続方法、並びにその接
続構造及び接続方法におけるはんだバンプ形成法に関す
るものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a connection structure between an electronic component and a substrate, a method of connecting the same, and a method of forming a solder bump in the connection structure and the connection method, and more particularly to an electronic component (BGA (Ball Grid Array)). And CSP (Chip Si)
Wiring pads of package-type surface-mounted electronic components such as ze Package) and the wiring pattern of the board (eg, printed wiring board on which electronic components are mounted) are electrically and completely connected individually via solder. The present invention relates to a connection structure between an electronic component and a substrate having no connection failure and a connection method thereof, and a method of forming a solder bump in the connection structure and the connection method.

【0002】[0002]

【従来の技術】最近、電子機器の高機能化の要求から電
子部品の接続点数の増加が望まれている。このため、電
子部品のパッケ−ジ側面にリ−ドを配した表面実装型電
子部品よりも、電子部品のパッケ−ジにおける一方の主
面全域を利用するBGA型あるいはCSP型の表面実装
型電子部品が脚光を浴びつつある。CSP型はパッケ−
ジサイズをICチップとほぼ同一サイズにまとめたもの
で、BGA型はパッケ−ジサイズがCSP型より大き
い。パッケ−ジにおける一方の主面となっている基材の
主面に備えられている複数個の配線パッドの構成はCS
P型及びBGA型両者同様である。そこで、以下BGA
型の表面実装型電子部品を代表として説明する。なお、
簡略化のためBGAと略記する。
2. Description of the Related Art Recently, an increase in the number of connection points of electronic parts has been desired due to a demand for higher performance of electronic equipment. For this reason, a BGA type or CSP type surface mount type electronic device that uses the entire one main surface of the package of the electronic component is better than a surface mount type electronic component in which leads are arranged on the package side surface of the electronic component. Parts are in the limelight. CSP type is package
The package size of the BGA type is larger than that of the CSP type. The configuration of a plurality of wiring pads provided on the main surface of the base material which is one main surface of the package is CS
The same applies to both P-type and BGA-type. Therefore, BGA
A description will be given by taking a surface-mount type electronic component as a representative. In addition,
Abbreviated as BGA for simplicity.

【0003】以下、BGAと基板との接続構造を図7
(a)(b)(c)(d)を参照して説明する。図7
(a)において、1はBGA8の基材である。この基材
1の主面には複数個の配線パッド2が備えられている。
同じく図7(a)において、3はモールド部で、モール
ド部3の内部にはICチップとそれを配線パッド2と接
続するための導体パターンやボンディングワイヤなどが
内包されている。図7(b)において、9はプリント配
線基板などの基板(以下、基板と略記する)である。こ
の基板9の前記BGA8を搭載する側の面には配線パタ
ーン10が設けられている。この配線パターン10は、
例えば図7(c)に示すように、円形部10bと、引回
部10aとから構成されている。また、必要に応じて、
はんだの広がりを阻止するはんだレジスト層12が前記
円形部10bの周囲の円形部分を除いて設けられている
場合がある。そして、図7(d)に示すように、上述の
BGA8の配線パッド2と上述の基板9の配線パターン
10とがはんだ16を介して個々に電気的に接続されて
BGA8が基板9に搭載されることとなる。
FIG. 7 shows a connection structure between a BGA and a substrate.
A description will be given with reference to (a), (b), (c), and (d). FIG.
In (a), 1 is a base material of BGA8. A plurality of wiring pads 2 are provided on the main surface of the substrate 1.
Similarly, in FIG. 7A, reference numeral 3 denotes a mold portion, and the inside of the mold portion 3 includes an IC chip, a conductor pattern for connecting the IC chip to the wiring pad 2, a bonding wire, and the like. In FIG. 7B, reference numeral 9 denotes a substrate such as a printed wiring board (hereinafter abbreviated as a substrate). A wiring pattern 10 is provided on a surface of the substrate 9 on which the BGA 8 is mounted. This wiring pattern 10
For example, as shown in FIG. 7C, it is composed of a circular portion 10b and a routing portion 10a. Also, if necessary,
In some cases, a solder resist layer 12 for preventing spread of the solder is provided except for a circular portion around the circular portion 10b. Then, as shown in FIG. 7D, the above-mentioned wiring pads 2 of the BGA 8 and the above-mentioned wiring patterns 10 of the substrate 9 are individually electrically connected via solder 16, and the BGA 8 is mounted on the substrate 9. The Rukoto.

【0004】次に、上述のBGA8を基板9に搭載する
プロセスを図8(a)(b)(c)(d)(e)を参照
して説明する。まず、基材1の主面に金属製のスクリー
ンマスク(以下、メタルマスクと略記)4を配設する。
このメタルマスク4には、容量が一定の複数個の開口部
4aが配線パッド2の位置および形状に対応して設けら
れている。このメタルマスク4の上面に置かれたはんだ
ペースト6をスキージ5により開口部4aに圧入する。
このスキージ5が図の左側より右側(矢印イの方向)へ
移動することにより、メタルマスク4の上面でスキージ
5の移動方向前面に置かれたはんだペースト6がスキー
ジ5からメタルマスク4の表面で基材1に向かう方向の
作用力と表面上での回転力を受けて、一定量のはんだペ
ースト6aが開口部4a内に充填される(図8(a)参
照)。次に、メタルマスク4を基材1から離すことによ
り、配線パッド2上に一定量のはんだペースト6aが残
って印刷されたことになる(図8(b)参照)。さら
に、上記の一定量のはんだペースト6aが印刷された基
材1をリフロー装置を通過させることにより、はんだは
溶融され、そのはんだの表面張力によって欠球形状のは
んだバンプ7が形成される(図8(c)参照)。なお、
はんだバンプ形成法を紹介したものとして、特開平7−
201869号公報や特開平7−202401号公報が
ある。
Next, a process of mounting the above BGA 8 on the substrate 9 will be described with reference to FIGS. 8 (a), 8 (b), 8 (c), 8 (d) and 8 (e). First, a metal screen mask (hereinafter abbreviated as a metal mask) 4 is provided on the main surface of the substrate 1.
The metal mask 4 is provided with a plurality of openings 4 a having a constant capacity corresponding to the positions and shapes of the wiring pads 2. The solder paste 6 placed on the upper surface of the metal mask 4 is pressed into the opening 4a by the squeegee 5.
When the squeegee 5 moves from the left side to the right side (in the direction of arrow A), the solder paste 6 placed on the upper surface of the metal mask 4 in the moving direction of the squeegee 5 moves from the squeegee 5 to the surface of the metal mask 4. The opening 4a is filled with a certain amount of solder paste 6a under the action force in the direction toward the base material 1 and the rotational force on the surface (see FIG. 8A). Next, by separating the metal mask 4 from the base material 1, a certain amount of the solder paste 6a remains on the wiring pads 2 and printing is performed (see FIG. 8B). Further, the base material 1 on which the fixed amount of the solder paste 6a is printed is passed through a reflow device, so that the solder is melted, and a chipped solder bump 7 is formed by the surface tension of the solder. 8 (c)). In addition,
Japanese Patent Application Laid-Open No.
2018869 and JP-A-7-202401.

【0005】それから、基板9上の配線パターン10上
に一定量のはんだペースト11を塗布して、この基板9
上に上下逆さにしたBGA8を置く。すなわち、基板9
側のはんだペースト11とBGA8側のはんだバンプ7
とを対向させる(図8(d)参照)。そして、上述の図
8(d)の状態でリフローすることにより、はんだバン
プ7及びはんだペースト11がリフロ−して、そのはん
だ16は配線パッド2及び配線パターン10に濡れ、基
材1が冷却することにより、はんだ16が固化して、上
述のBGA8の配線パッド2と上述の基板9の配線パタ
ーン10とがはんだ16を介して個々に電気的に接続さ
れて、BGA8が基板9に搭載されることとなる(図8
(e)参照)。
Then, a certain amount of solder paste 11 is applied on the wiring pattern 10 on the substrate 9 to
Place BGA8 upside down on top. That is, the substrate 9
Side solder paste 11 and BGA 8 side solder bump 7
Are opposed to each other (see FIG. 8D). 8D, the solder bumps 7 and the solder paste 11 are reflowed, and the solder 16 wets the wiring pads 2 and the wiring patterns 10, and the base material 1 is cooled. Thereby, the solder 16 is solidified, and the wiring pads 2 of the BGA 8 and the wiring patterns 10 of the substrate 9 are individually electrically connected via the solder 16, and the BGA 8 is mounted on the substrate 9. (Fig. 8
(E)).

【0006】[0006]

【発明が解決しようとする課題】ところが、上述の従来
の電子部品と基板との接続構造には次のような課題があ
る。すなわち、図7及び図8に示すように、基材1の配
線パッド2側の面とモールド部3側の面に配線パターン
(図示せず)を製作した時の残留応力や基材1とモール
ド部3は素材の熱膨張係数差に基づくモ−ルド時の熱収
縮量の差(バイメタル効果)などで、基材1側が凸にな
る湾曲を持つ傾向にある。この結果、はんだ16(BG
A8側のはんだバンプ7となるはんだペースト6及び又
は基板9側のはんだペースト11)の供給量が一定の場
合、上述の基材1の反り(湾曲)により、BGA8の配
線パッド2と基板9の配線パターン10とは、内側にお
いてはんだ16を介して接続されているが、外側におい
てはんだ16がBGA8側16aと基板9側16bとに
分れていてはんだ16を介して接続されていない。すな
わち、接続不良が発生する場合がある。
However, the above-described conventional connection structure between an electronic component and a substrate has the following problems. That is, as shown in FIGS. 7 and 8, residual stress when a wiring pattern (not shown) is manufactured on the surface of the base 1 on the side of the wiring pad 2 and the surface of the mold 3 side, The portion 3 tends to have a curved shape in which the substrate 1 side is convex due to a difference in the amount of thermal contraction during molding (bimetal effect) based on a difference in the coefficient of thermal expansion of the material. As a result, the solder 16 (BG
When the supply amount of the solder paste 6 to be the solder bump 7 on the A8 side and / or the solder paste 11) on the substrate 9 side is constant, the warpage (curvature) of the base material 1 causes the wiring pad 2 of the BGA 8 and the The wiring pattern 10 is connected via the solder 16 on the inner side, but is separated on the outer side into the BGA 8 side 16a and the substrate 9 side 16b and is not connected via the solder 16. That is, a connection failure may occur.

【0007】さらに、詳細に説明すると、図7及び図8
に示すように、基材1には反り(湾曲)が発生してお
り、このままでは一定量のはんだバンプ7の頂点が同一
平面(図8(c)中の一点鎖線にて示す)上にない。こ
のために、図8(d)に示すように、基板9上に上下逆
さまにしたBGA8を置くと、はんだバンプ7ははんだ
ペースト11に大半が接触するが、外側のはんだバンプ
7ははんだペースト11に接触しないことがある。この
状態でリフローすると、バイメタル効果が薄れて全ての
はんだバンプ7ははんだペースト11とリフロ−し、一
旦は接載される。ところが、リフロ−後の冷却で再び基
材1が湾曲すると、BGA8は内側のはんだ16で基板
9に搭載できてはいるものの、図7(d)及び図8
(e)に示すように、外側のはんだ16はBGA8側1
6aと基板9側16bとに分れていて、BGA8の配線
パッド2と基板9の配線パターン10とははんだ16を
介して接続されていないことがある。
More specifically, FIG. 7 and FIG.
As shown in FIG. 8, the substrate 1 is warped (curved), and in this state, a certain amount of the vertices of the solder bumps 7 are not on the same plane (indicated by the dashed line in FIG. 8C). . For this purpose, as shown in FIG. 8D, when the BGA 8 which is turned upside down is placed on the substrate 9, most of the solder bumps 7 come into contact with the solder paste 11, but the outer solder bumps 7 May not come into contact with. When reflow is performed in this state, the bimetal effect is weakened, and all the solder bumps 7 reflow with the solder paste 11 and are once mounted. However, when the substrate 1 is bent again by cooling after the reflow, the BGA 8 can be mounted on the substrate 9 with the solder 16 on the inside, but FIG.
As shown in (e), the outer solder 16 is the BGA 8 side 1
6a and the substrate 9 side 16b, the wiring pads 2 of the BGA 8 and the wiring pattern 10 of the substrate 9 may not be connected via the solder 16.

【0008】上述の接続不良は基材1の湾曲度合いだけ
でなく、基板9上の引回部10aと円形部10bとから
構成されている配線パターン10にも左右される。すな
わち、配線パターン10以外の領域ははんだとのぬれ性
が低いので、個々のはんだバンプ7が一定量(はんだ量
が同等)であると、引回部10aが多いほどはんだ16
は引回部10aにも拡がってしまい円形部10bでの盛
り上がり度合いは小となり、上述の接続不良が増加す
る。
[0008] The above-mentioned poor connection depends not only on the degree of curvature of the base material 1 but also on the wiring pattern 10 composed of the routing portion 10a and the circular portion 10b on the substrate 9. That is, since the region other than the wiring pattern 10 has low wettability with the solder, if the individual solder bumps 7 have a fixed amount (the amount of the solder is equal), the more the wiring portions 10a, the more the solder 16
Is spread to the routing part 10a, and the degree of swelling at the circular part 10b becomes small, and the above-mentioned connection failure increases.

【0009】本発明の目的は、電子部品の配線パッドと
基板の配線パターンとがはんだを介して個々に電気的に
完全に接続されていて接続不良が無い電子部品と基板と
の接続構造及びその接続方法、並びにその接続構造及び
接続方法におけるはんだバンプ形成法を提供することに
ある。
SUMMARY OF THE INVENTION It is an object of the present invention to provide a connection structure between an electronic component and a substrate in which the wiring pads of the electronic component and the wiring pattern of the substrate are electrically and completely connected individually via solder, and there is no poor connection. An object of the present invention is to provide a connection method, a connection structure thereof, and a solder bump forming method in the connection method.

【0010】[0010]

【課題を解決するための手段】本発明は、上記の目的を
達成するために、はんだの供給において、配線パッドと
配線パターンとが個々に完全に接続するように、電子部
品及び又は基板の湾曲度と、配線パッド及び又は配線パ
ターンの加熱溶融時のはんだの濡れ面積と、ほぼ比例し
た量のはんだを供給することを特徴とする。
SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor device, comprising the steps of: providing a wiring pad and a wiring pattern so as to completely and individually connect a wiring pad and a wiring pattern to each other; The method is characterized in that a solder is supplied in an amount substantially proportional to the degree of soldering and the wet area of the solder when the wiring pad and / or the wiring pattern is heated and melted.

【0011】この結果、本発明の電子部品と基板との接
続構造及びその接続方法、並びにその接続構造及び接続
方法におけるはんだバンプ形成法は、電子部品の配線パ
ッドと基板の配線パターンとがはんだを介して個々に電
気的に完全に接続されていて接続不良が無い。
As a result, the connection structure of the electronic component and the substrate according to the present invention and the method of connecting the same, and the method of forming the solder bumps in the connection structure and the connection method, require that the wiring pad of the electronic component and the wiring pattern of the substrate form a solder. Are completely electrically connected to each other through the connection and there is no connection failure.

【0012】[0012]

【発明の実施の形態】以下、本発明の電子部品と基板と
の接続構造及びその接続方法、並びにその接続構造及び
接続方法におけるはんだバンプ形成法の実施形態のうち
の4例を図1乃至図6を参照して詳細に説明する。な
お、図1乃至図6において図7及び図8に示したものと
同一物あるいは相当品には同一符号を付けて、説明の反
復を避けることにした。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, four examples of embodiments of a connection structure between an electronic component and a substrate of the present invention, a connection method thereof, and a solder bump forming method in the connection structure and the connection method will be described with reference to FIGS. This will be described in detail with reference to FIG. In FIGS. 1 to 6, the same or corresponding parts as those shown in FIGS. 7 and 8 are denoted by the same reference numerals, and the description will not be repeated.

【0013】図1(a)(b)(c)(d)(e)は本
発明の電子部品と基板との接続構造及びその接続方法、
並びにその接続構造及び接続方法におけるはんだバンプ
形成法の第1の実施形態を示し、BGAを基板に搭載す
るプロセスを示した説明図である。この第1の実施の形
態は、はんだ16の供給量を、配線パッド2及び配線パ
ターン10の濡れ面積を一定として基材1の湾曲度に対
して調整するものである。この調整は、配線パッド2上
にはんだペースト6を印刷して供給する際にメタルマス
ク4の開口部4aの容量により行うものであって、上に
凸の形状を持つ基材1と基板9の間隙を考慮して行われ
る。
1 (a), 1 (b), 1 (c), 1 (d), and 1 (e) show a connection structure between an electronic component and a substrate according to the present invention and a connection method thereof.
FIG. 4 is an explanatory diagram showing a first embodiment of a solder bump forming method in the connection structure and the connection method, and showing a process of mounting a BGA on a substrate. In the first embodiment, the supply amount of the solder 16 is adjusted with respect to the curvature of the substrate 1 while keeping the wet area of the wiring pad 2 and the wiring pattern 10 constant. This adjustment is performed by the capacity of the opening 4a of the metal mask 4 when the solder paste 6 is printed and supplied on the wiring pad 2, and the base 1 and the substrate 9 having the upward convex shape are formed. This is performed in consideration of the gap.

【0014】すなわち、基材1の配線パッド2と基板9
の配線パタ−ン10はそれぞれ同等として、基材1の湾
曲度を考慮して、中心付近の開口部4aに比べ外側の開
口部4aの開口度を大きくしたメタルマスク4を使用し
て、基材1にはんだペースト6を印刷する(図1(a)
参照)。すると、印刷されたはんだペースト6aは外側
に行くに従って供給量は増えている(図1(b)参
照)。この状態でリフローすると、中心(内側)付近の
はんだバンプ7に比べ外側のはんだバンプ7のバンプ高
さが高く(バンプ径が大と)なり、BGA8における各
はんだバンプ7の頂点が同一平面(図1(c)中の一点
鎖線にて示す)上に配される(図1(c)参照)。一
方、基板9の各配線パタ−ン10上に同量のはんだペ−
スト11を印刷し、そこで上述のBGA8を上下逆さに
して、このBGA8のはんだバンプ7と基板9のはんだ
ペースト11とを合わせる(図1(d)参照)。そし
て、上述の状態で、リフロ−を行うと、外側のはんだ1
6の供給量は内側のはんだ16の供給量と比較して大で
あるから、基材1が湾曲していても、基材1の配線パッ
ド2と基板9の配線パタ−ン10とははんだ16を介し
て個々に電気的に接続されて、特に外側において接続不
良が無く、BGA8が基板9に搭載されることとなる
(図1(e)参照)。
That is, the wiring pads 2 of the substrate 1 and the substrate 9
In consideration of the curvature of the base material 1, the wiring patterns 10 of the present embodiment are made equivalent to each other, using a metal mask 4 in which the opening degree of the outer opening 4a is larger than that of the opening 4a near the center. Printing solder paste 6 on material 1 (FIG. 1 (a))
reference). Then, the supply amount of the printed solder paste 6a increases toward the outside (see FIG. 1B). When the reflow is performed in this state, the bump height of the outer solder bump 7 is larger (bump diameter is larger) than the solder bump 7 near the center (inner side), and the vertices of the solder bumps 7 in the BGA 8 are on the same plane (FIG. 1 (c)) (refer to FIG. 1 (c)). On the other hand, the same amount of solder paste is placed on each wiring pattern 10 of the substrate 9.
The strike 11 is printed, and the above-mentioned BGA 8 is turned upside down so that the solder bumps 7 of the BGA 8 and the solder paste 11 of the substrate 9 are combined (see FIG. 1D). When reflow is performed in the above-described state, the outer solder 1
6 is larger than the supply amount of the inner solder 16, even if the base material 1 is curved, the wiring pattern 2 of the base material 1 and the wiring pattern 10 of the The BGA 8 is mounted on the substrate 9 without any connection failure, particularly on the outside, through the electrical connection via the reference numeral 16 (see FIG. 1E).

【0015】図2(a)及び(b)は上述の第1の実施
の形態におけるメタルマスク4の変形例を示した説明図
である。図2(a)に示すメタルマスク4は、基材1の
湾曲度に合わせて階段状に段差をつけて開口部4aの容
量を調整したものである。また、図2(b)に示すメタ
ルマスク4は、緩やかに傾斜をつけて(立体的には曲面
を形成して)開口部4aの容量を調整したものである。
FIGS. 2A and 2B are explanatory views showing a modified example of the metal mask 4 in the above-described first embodiment. The metal mask 4 shown in FIG. 2A is obtained by adjusting the capacity of the opening 4 a by providing a step-like step according to the curvature of the base material 1. The metal mask 4 shown in FIG. 2 (b) is obtained by adjusting the capacity of the opening 4a with a gentle inclination (three-dimensionally forming a curved surface).

【0016】図3(a)(b)(c)は本発明の電子部
品と基板との接続構造及びその接続方法、並びにその接
続構造及び接続方法におけるはんだバンプ形成法の第2
の実施形態を示した説明図である。この第2の実施形態
は、上述の第1の実施形態の変形例であって、厚さが上
述の第1の実施の形態に使用されるメタルマスク4より
も薄いメタルマスク4を使用するものである。すなわ
ち、この第2の実施の形態におけるはんだ16の供給量
の調整は、配線パッド2上にはんだペースト6を印刷し
て供給する際に厚さが薄いメタルマスク4の開口部4a
の容量により行うものである(図3(a)参照)。それ
から、この薄いメタルマスク4を用いることに基いて、
はんだ供給量が減少することを補うために印刷後の各は
んだペ−スト6aに同一径(同一量)のはんだボール1
3を真空吸着治具14で供給する(図3(b)参照)。
上述の真空吸着治具14の吸着穴14aで外側にあたる
はんだボ−ル13が大きくなるように選択的に吸着する
ことは困難であるから、印刷するはんだペ−スト6aの
量を予め調整しておくことが実作業上では有利である。
FIGS. 3 (a), 3 (b) and 3 (c) show a connection structure between an electronic component and a substrate according to the present invention, a connection method therefor, and a solder bump formation method in the connection structure and connection method.
It is explanatory drawing which showed embodiment of FIG. The second embodiment is a modification of the above-described first embodiment, and uses a metal mask 4 having a thickness smaller than that of the metal mask 4 used in the above-described first embodiment. It is. That is, the supply amount of the solder 16 in the second embodiment is adjusted by printing the solder paste 6 on the wiring pad 2 and supplying the solder paste 6 to the opening 4 a of the thin metal mask 4.
(See FIG. 3A). Then, based on using this thin metal mask 4,
Solder balls 1 of the same diameter (same amount) are provided on each solder paste 6a after printing to compensate for the decrease in the amount of supplied solder.
3 is supplied by a vacuum suction jig 14 (see FIG. 3B).
Since it is difficult to selectively suck the solder ball 13 on the outside with the suction hole 14a of the vacuum suction jig 14 so as to be large, it is necessary to adjust the amount of the solder paste 6a to be printed in advance. This is advantageous in actual work.

【0017】そして、それぞれの配線パッド2につい
て、印刷したはんだペ−スト6aと供給したはんだボー
ル13の和が上述の第1の実施形態の図1(b)に示す
ように印刷したはんだペ−スト6aの量に相当していれ
ば、リフロー後には中心付近のはんだバンプ7に比べ外
側のはんだバンプ7のバンプ高さが高く(バンプ径が大
と)なり、各はんだバンプ7の頂点が同一平面(図3
(c)中の一点鎖線にて示す)上に揃って配列されるこ
ととなる(図3(c)参照。)この結果、上述の第1の
実施形態の図1(d)(e)に示すように、図3(c)
のBGA8を基板9に搭載することにより、基材1が湾
曲していても、基材1の配線パッド2と基板9の配線パ
タ−ン10とははんだ16を介して個々に電気的に接続
されて、特に外側において接続不良が無い。
Then, for each wiring pad 2, the sum of the printed solder paste 6a and the supplied solder ball 13 is equal to the printed solder paste as shown in FIG. 1B of the first embodiment. If the amount corresponds to the amount of the strike 6a, the bump height of the outer solder bump 7 is higher (bump diameter is larger) than the solder bump 7 near the center after reflow, and the apex of each solder bump 7 is the same. Plane (Fig. 3
(See (c) in FIG. 3 (c).) As a result, the arrangement is made as shown in FIGS. 1 (d) and (e) of the first embodiment. As shown in FIG.
By mounting the BGA 8 on the substrate 9, even if the substrate 1 is curved, the wiring pads 2 of the substrate 1 and the wiring patterns 10 of the substrate 9 are individually electrically connected via the solder 16. Therefore, there is no connection failure especially on the outside.

【0018】図4(a)(b)(c)は本発明の電子部
品と基板との接続構造及びその接続方法、並びにその接
続構造及び接続方法におけるはんだバンプ形成法の第3
の実施形態を示した説明図である。この第3の実施の形
態は上述の第1の実施形態及び第2の実施形態の変形例
であって、この第3の実施形態におけるはんだ16の供
給量の調整は、配線パッド2の周囲にはんだレジスト層
15を設けかつ配線パッド2上にはんだペースト6を印
刷して供給する際にはんだレジスト層15の開口部15
aの容量により行うものである。すなわち、基材1には
んだレジスト層15を設ける。このはんだレジスト層1
5の開口部15aは基材1の湾曲度を考慮し、中心側で
小さく、外側ほど大きくしている。その上にメタルマス
ク4を置いて、スキ−ジ5で配線パッド2上にはんだペ
ースト6を印刷する。このメタルマスク4の開口部4a
の開口度は同等である(図4(a)参照)。このスクリ
−ン印刷の結果、配線パッド2とはんだレジスト層15
の間隙からはんだペ−スト6aが行き渡り、印刷された
はんだペ−スト6aの量は、上述の第1の実施の形態の
図1(b)及び第2の実施の形態の図3(b)と同様
に、中心側で少なく、外側ほど多くなっている(図4
(b)参照)。そして、これをリフロ−すると、はんだ
は基材1にぬれないので、各配線パッド2のはんだバン
プ7の高さが揃ったBGA8が得られる。なお、リフロ
−後にはんだレジスト層15を除去している(図4
(c)参照。この結果、上述の第1の実施形態及び第2
の実施の形態と同様に、BGA8を基板9に搭載した際
に、基材1が湾曲していても接続不良が無い。
FIGS. 4 (a), 4 (b) and 4 (c) show a third embodiment of a connection structure between an electronic component and a substrate according to the present invention, a connection method thereof, and a solder bump forming method in the connection structure and connection method.
It is explanatory drawing which showed embodiment of FIG. The third embodiment is a modification of the first and second embodiments described above. The supply amount of the solder 16 in the third embodiment is adjusted around the wiring pad 2. When the solder resist layer 15 is provided and the solder paste 6 is printed and supplied on the wiring pad 2, the opening 15 of the solder resist layer 15 is provided.
This is performed with the capacity of a. That is, the solder resist layer 15 is provided on the substrate 1. This solder resist layer 1
The opening 15a of No. 5 is smaller on the center side and larger on the outer side in consideration of the degree of curvature of the base material 1. A metal mask 4 is placed thereon, and a solder paste 6 is printed on the wiring pads 2 with a squeegee 5. Opening 4a of this metal mask 4
Are the same (see FIG. 4A). As a result of the screen printing, the wiring pads 2 and the solder resist layer 15 are formed.
The solder paste 6a spreads out from the gap, and the amount of the printed solder paste 6a is as shown in FIG. 1 (b) of the above-described first embodiment and FIG. 3 (b) of the second embodiment. In the same manner as in FIG.
(B)). Then, when this is reflowed, the solder does not wet the base material 1, so that the BGA 8 in which the height of the solder bumps 7 of each wiring pad 2 is uniform is obtained. After the reflow, the solder resist layer 15 is removed (FIG. 4).
See (c). As a result, the first embodiment and the second
Similarly to the embodiment, when the BGA 8 is mounted on the substrate 9, there is no connection failure even if the base material 1 is curved.

【0019】図5(a)(b)(c)は本発明の電子部
品と基板との接続構造及びその接続方法、並びにその接
続構造及び接続方法におけるはんだバンプ形成法の第4
の実施形態を示した説明図である。図6は同じく供給は
んだ量が一定のときの配線パッド径とバンプ高さの関係
を示した図(グラフ)である。この第4の実施形態は、
はんだ16の供給量を一定にして、基材1の湾曲度に対
して配線パッド2及び配線パターン10の濡れ面積を調
整するものである。すなわち、はんだペーストのリフロ
−後におけるはんだバンプのバンプ高さ(径)は、はん
だバンプ(はんだペースト)量を同一とすると、図6に
示すように、円形状配線パッドの直径(パッド径)が大
きいほど低く(小と)なるトレ−ドオフの関係を持つ。
そこで、この第4の実施形態では、配線パッド2の形状
を調整して有る。調整の方法としては、基材1の湾曲度
から中心付近の配線パッド2に比べ外側の配線パッド2
のパッド径を小さくしている(図5(a)参照)。次
に、開口部の容量が一定のメタルマスクを使用して上述
の配線パッド2にはんだペースト6aを印刷する。この
印刷されたはんだペースト6aの体積(容量)はどの配
線パッド2上においても同一である(図5(b)参
照)。この状態でリフローすると、中心付近のはんだバ
ンプ7に比べ外側のはんだバンプ7のバンプ高さが高く
なり、各はんだバンプ7の頂点が同一平面上に配され
る。この結果、BGA8を基板9に搭載した際に、基材
1が湾曲していても接続不良が無い。
FIGS. 5 (a), 5 (b) and 5 (c) show a fourth embodiment of a connection structure between an electronic component and a substrate according to the present invention, a connection method thereof, and a solder bump forming method in the connection structure and connection method.
It is explanatory drawing which showed embodiment of FIG. FIG. 6 is a graph (graph) showing the relationship between the wiring pad diameter and the bump height when the amount of supplied solder is constant. In this fourth embodiment,
The supply amount of the solder 16 is fixed, and the wet area of the wiring pad 2 and the wiring pattern 10 is adjusted with respect to the curvature of the substrate 1. That is, assuming that the amount of the solder bumps (solder paste) is the same, the diameter (pad diameter) of the circular wiring pad is the same as the bump height (diameter) of the solder bumps after the reflow of the solder paste, as shown in FIG. The larger the value, the lower (small) the trade-off relationship.
Therefore, in the fourth embodiment, the shape of the wiring pad 2 is adjusted. As an adjustment method, the wiring pads 2 on the outer side compared to the wiring pads 2 near the center are determined based on the curvature of the base material 1.
(See FIG. 5A). Next, a solder paste 6a is printed on the above-mentioned wiring pad 2 using a metal mask having a constant opening capacity. The volume (capacity) of the printed solder paste 6a is the same on any of the wiring pads 2 (see FIG. 5B). When reflow is performed in this state, the bump height of the outer solder bump 7 becomes higher than that of the solder bump 7 near the center, and the apex of each solder bump 7 is arranged on the same plane. As a result, when the BGA 8 is mounted on the substrate 9, there is no connection failure even if the substrate 1 is curved.

【0020】この実施形態においては、図4の特性曲線
を考慮し配線パッド2のパッド径を調整することによっ
て、各配線パッド上に供給するはんだペ−スト量を基材
1の湾曲度に対し相対的に比例させている。
In this embodiment, by adjusting the pad diameter of the wiring pads 2 in consideration of the characteristic curve of FIG. It is relatively proportional.

【0021】以上の個々の実施形態での各はんだバンプ
頂点同一平面化の手法は組み合わせて実施しても良い。
また、反りの方向が逆であったり、その他の原因によっ
てはんだバンプの頂点と基板の間隙が発生しても同様の
効果が得られる。また基板にはんだバンプを形成する場
合でも同様の効果(接続不良が無い)が得られる。
The methods of making the solder bump vertices flush with each other in the individual embodiments described above may be implemented in combination.
The same effect can be obtained even if the direction of warpage is reversed or a gap occurs between the apex of the solder bump and the substrate due to other causes. Similar effects (no connection failure) can be obtained even when solder bumps are formed on the substrate.

【0022】[0022]

【発明の効果】以上のように、本発明は、はんだの供給
において、配線パッドと配線パターンとが個々に完全に
接続するように、電子部品及び又は基板の湾曲度と、配
線パッド及び又は配線パターンの加熱溶融時のはんだの
濡れ面積と、ほぼ比例した量のはんだを供給するもので
あるから、電子部品の配線パッドと基板の配線パターン
とがはんだを介して個々に電気的に完全に接続されてい
て接続不良が無い。
As described above, according to the present invention, the degree of curvature of an electronic component and / or a substrate, and the degree of curvature of a wiring pad and / or a wiring so that a wiring pad and a wiring pattern are individually and completely connected in the supply of solder. Since the solder is supplied in an amount approximately proportional to the wet area of the solder when the pattern is heated and melted, the wiring pads of the electronic component and the wiring pattern of the board are electrically and completely connected individually via the solder There is no connection failure.

【図面の簡単な説明】[Brief description of the drawings]

【図1】(a)(b)(c)(d)(e)は、本発明の
電子部品と基板との接続構造及びその接続方法、並びに
その接続構造及び接続方法におけるはんだバンプ形成法
の第1の実施の形態を示し、BGAの製造プロセスとB
GAを基板に搭載するプロセスを簡略化して示す図であ
る。
1 (a), (b), (c), (d) and (e) show a connection structure between an electronic component and a substrate according to the present invention, a connection method thereof, and a solder bump formation method in the connection structure and connection method. 1A and 1B show a first embodiment, wherein a BGA manufacturing process and BGA
FIG. 4 is a diagram schematically illustrating a process of mounting a GA on a substrate.

【図2】(a)(b)は、メタルマスクの開口部の変形
例を示した説明図である。
FIGS. 2A and 2B are explanatory views showing a modification of an opening of a metal mask.

【図3】(a)(b)(c)は、本発明の電子部品と基
板との接続構造及びその接続方法、並びにその接続構造
及び接続方法におけるはんだバンプ形成法はんだバンプ
形成法の第2の実施の形態を示したBGAの製造プロセ
スを簡略化して示す図である。
FIGS. 3A, 3B, and 3C are diagrams showing a connection structure between an electronic component and a substrate according to the present invention, a connection method thereof, and a solder bump formation method in the connection structure and connection method; FIG. FIG. 17 is a diagram schematically illustrating a manufacturing process of a BGA according to the embodiment.

【図4】(a)(b)(c)は、本発明の電子部品と基
板との接続構造及びその接続方法、並びにその接続構造
及び接続方法におけるはんだバンプ形成法の第3の実施
の形態を示したBGAの製造プロセスを簡略化して示す
図である。
FIGS. 4 (a), (b) and (c) show a third embodiment of a connection structure between an electronic component and a substrate of the present invention, a connection method thereof, and a solder bump forming method in the connection structure and connection method; FIG. 3 is a simplified diagram showing a manufacturing process of a BGA showing the above.

【図5】(a)(b)(c)は本発明の電子部品と基板
との接続構造及びその接続方法、並びにその接続構造及
び接続方法におけるはんだバンプ形成法の第3の実施の
形態を示したBGAの製造プロセスを簡略化して示す図
である。
FIGS. 5A, 5B, and 5C show a third embodiment of a connection structure between an electronic component and a substrate according to the present invention, a connection method thereof, and a solder bump forming method in the connection structure and the connection method; It is a figure which shows the manufacturing process of the shown BGA in a simplified form.

【図6】供給はんだ量が一定のときの配線パッド径とバ
ンプ高さの関係を示した図(グラフ)である。
FIG. 6 is a graph (graph) showing a relationship between a wiring pad diameter and a bump height when a supplied amount of solder is constant.

【図7】(a)はBGAの概略図、(b)は基板の概略
図、(c)は(b)におけるc−c線矢視図、(d)は
従来のプロセスでBGAを基板に搭載した状態の概略図
である。
7A is a schematic view of a BGA, FIG. 7B is a schematic view of a substrate, FIG. 7C is a view taken along a line cc in FIG. 7B, and FIG. It is the schematic of the state in which it was mounted.

【図8】(a)(b)(c)(d)(e)は、従来のB
GAの製造プロセスとBGAを基板に搭載するプロセス
を簡略化して示す図である。
8 (a), (b), (c), (d), and (e) show conventional B
It is a figure which shows the manufacturing process of GA, and the process which mounts a BGA on a board in simplified form.

【符号の説明】 1…基材 2…配線パッド 3…モールド部 4…メタルマスク 4a…メタルマスクの開口部 5…スキージ 6、11…はんだペースト 7…はんだバンプ 8…BGA 9…基板 10…配線パターン 10a…引回部 10b…円形部 12、15…はんだレジスト層 13…はんだボール 14…真空吸着治具 16…はんだ[Description of Signs] 1 ... Base material 2 ... Wiring pad 3 ... Mold part 4 ... Metal mask 4a ... Opening of metal mask 5 ... Squeegee 6, 11 ... Solder paste 7 ... Solder bump 8 ... BGA 9 ... Substrate 10 ... Wiring Pattern 10a: routing portion 10b: circular portion 12, 15: solder resist layer 13: solder ball 14: vacuum suction jig 16: solder

───────────────────────────────────────────────────── フロントページの続き (72)発明者 中村 秀男 茨城県竜ケ崎市向陽台5丁目2番 日立テ クノエンジニアリング 株式会社開発研究 所内 ──────────────────────────────────────────────────の Continued on the front page (72) Inventor Hideo Nakamura 5-2-2 Koyodai, Ryugasaki-shi, Ibaraki Pref. Hitachi Techno Engineering Co., Ltd.

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】 電子部品の配線パッドと基板の配線パタ
ーンとがはんだを介して個々に電気的に接続されている
電子部品と基板との接続構造であって、 前記はんだの供給量は、前記配線パッドと前記配線パタ
ーンとが個々に完全に接続するように、前記電子部品及
び又は前記基板の湾曲度と、前記配線パッド及び又は前
記配線パターンの加熱溶融時のはんだの濡れ面積と、ほ
ぼ比例した量であることを特徴とする電子部品と基板と
の接続構造。
1. A connection structure between an electronic component and a substrate, wherein a wiring pad of the electronic component and a wiring pattern of the substrate are individually electrically connected via solder, wherein the supply amount of the solder is The degree of curvature of the electronic component and / or the substrate and the wet area of the solder when the wiring pad and / or the wiring pattern is heated and melted are substantially proportional so that the wiring pad and the wiring pattern are completely connected individually. A connection structure between an electronic component and a substrate, characterized in that the amount is a predetermined amount.
【請求項2】 請求項1に記載の電子部品と基板との接
続構造において、 前記はんだの供給量は、前記湾曲度に対して前記濡れ面
積を調整することにより一定であること、及び又は、前
記濡れ面積を一定として前記湾曲度に対して調整するこ
とを特徴とする電子部品と基板との接続構造。
2. The connection structure between an electronic component and a substrate according to claim 1, wherein a supply amount of the solder is constant by adjusting the wetting area with respect to the degree of curvature, and / or A connection structure between an electronic component and a substrate, wherein the degree of curvature is adjusted while keeping the wet area constant.
【請求項3】 電子部品の配線パッドと基板の配線パタ
ーンとをはんだを介して個々に電気的に接続する電子部
品と基板との接続方法であって、 前記配線パッドと前記配線パターンとが個々に完全に接
続するように、前記電子部品及び又は前記基板の湾曲度
と、前記配線パッド及び又は前記配線パターンの加熱溶
融時のはんだの濡れ面積と、ほぼ比例した量のはんだを
供給することを特徴とする電子部品と基板との接続方
法。
3. A method of connecting an electronic component and a substrate, wherein the wiring pad of the electronic component and the wiring pattern of the substrate are individually electrically connected via solder, wherein the wiring pad and the wiring pattern are individually Supplying the solder in an amount substantially proportional to the degree of curvature of the electronic component and / or the substrate and the wet area of the solder when the wiring pad and / or the wiring pattern is heated and melted so that the solder is completely connected. Characteristic connection method between electronic components and substrate.
【請求項4】 請求項3に記載の電子部品と基板との接
続方法において、 前記はんだの供給量は、前記湾曲度に対して前記濡れ面
積を調整することにより一定であること、及び又は、前
記濡れ面積を一定として前記湾曲度に対して調整するこ
とを特徴とする電子部品と基板との接続方法。
4. The method for connecting an electronic component and a substrate according to claim 3, wherein the supply amount of the solder is constant by adjusting the wetting area with respect to the degree of curvature, and / or A method for connecting an electronic component and a substrate, wherein the degree of curvature is adjusted while keeping the wet area constant.
【請求項5】 電子部品の配線パッドと基板の配線パタ
ーンとがはんだを介して個々に電気的に接続されている
電子部品と基板との接続構造、及び電子部品の配線パッ
ドと基板の配線パターンとをはんだを介して個々に電気
的に接続する電子部品と基板との接続方法において、 前記電子部品の配線パッド及び又は前記基板の配線パタ
ーン上にはんだを供給し、その後前記はんだを加熱溶融
させてはんだバンプを形成する方法であって、 前記配線パッド及び又は前記配線パターン上にはんだを
供給する際に、前記配線パッドと前記配線パターンとが
個々に完全に接続するように、前記電子部品及び又は前
記基板の湾曲度と、前記配線パッド及び又は前記配線パ
ターンの加熱溶融時のはんだの濡れ面積と、ほぼ比例し
た量のはんだを供給することを特徴とするはんだバンプ
形成法。
5. A connection structure between an electronic component and a substrate, wherein a wiring pad of the electronic component and a wiring pattern of the substrate are individually electrically connected via solder, and a wiring pattern between the wiring pad of the electronic component and the substrate. And a method of connecting an electronic component and a substrate to each other electrically via a solder, by supplying solder to the wiring pads of the electronic component and / or the wiring pattern of the substrate, and then heating and melting the solder. A method of forming solder bumps by supplying solder on the wiring pads and / or the wiring patterns so that the wiring pads and the wiring patterns are completely connected individually. Or supplying the solder in an amount substantially proportional to the degree of curvature of the substrate and the wet area of the solder when the wiring pad and / or the wiring pattern is heated and melted. The solder bump forming method according to claim.
【請求項6】 請求項5に記載のはんだバンプ形成法に
おいて、 前記はんだの供給量は、前記湾曲度に対して前記濡れ面
積を調整することにより一定であること、及び又は、前
記濡れ面積を一定として前記湾曲度に対して調整するこ
とを特徴とするはんだバンプ形成法。
6. The solder bump forming method according to claim 5, wherein the supply amount of the solder is constant by adjusting the wetting area with respect to the degree of curvature, and / or A method for forming a solder bump, wherein the curvature is adjusted to be constant.
【請求項7】 請求項5に記載のはんだバンプ形成法に
おいて、 前記はんだの供給量は、前記配線パッド及び又は前記配
線パターン上にはんだペーストを印刷して供給する際に
スクリーンマスクの開口部の容量により調整すること、
及び又は、前記配線パッド及び又は前記配線パターン上
にはんだペーストを印刷しかつその上にはんだボールを
供給する際にスクリーンマスクの開口部の容量により調
整すること、及び又は、前記配線パッド及び又は前記配
線パターンの周囲にはんだレジスト層を設けかつ前記配
線パッド及び又は前記配線パターン上にはんだペースト
を印刷して供給する際に前記はんだレジスト層の開口部
の容量により調整することを特徴とするはんだバンプ形
成法。
7. The solder bump forming method according to claim 5, wherein the supply amount of the solder is such that the solder paste is printed on and supplied to the wiring pad and / or the wiring pattern at an opening of a screen mask. Adjusting by capacity,
And or or, by printing a solder paste on the wiring pads and or the wiring pattern and when supplying the solder balls thereon, to adjust by the capacity of the opening of the screen mask, and / or the wiring pads and or A solder bump, wherein a solder resist layer is provided around a wiring pattern, and when the solder paste is printed and supplied on the wiring pad and / or the wiring pattern, the solder paste is adjusted by a capacity of an opening of the solder resist layer. Forming method.
JP8256416A 1996-09-27 1996-09-27 Method and structure for connecting electronic part and substrate, and solder bump forming method in them Pending JPH10107176A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8256416A JPH10107176A (en) 1996-09-27 1996-09-27 Method and structure for connecting electronic part and substrate, and solder bump forming method in them

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8256416A JPH10107176A (en) 1996-09-27 1996-09-27 Method and structure for connecting electronic part and substrate, and solder bump forming method in them

Publications (1)

Publication Number Publication Date
JPH10107176A true JPH10107176A (en) 1998-04-24

Family

ID=17292373

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JPH10107176A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1174312A (en) * 1997-08-28 1999-03-16 Mitsubishi Electric Corp Semiconductor device and method for forming solder bump
JP2002164473A (en) * 2000-11-29 2002-06-07 Sharp Corp Semiconductor device and method for manufacturing the same
JP2007115789A (en) * 2005-10-19 2007-05-10 Matsushita Electric Ind Co Ltd Laminated semiconductor device and its manufacturing method
JP2009267117A (en) * 2008-04-25 2009-11-12 Nec Corp Semiconductor device, substrate, and method for mounting semiconductor device
US9345133B2 (en) 2012-02-28 2016-05-17 Canon Kabushiki Kaisha Printed circuit board and method of mounting components on the printed circuit board
JP2019009470A (en) * 2018-10-09 2019-01-17 パナソニックIpマネジメント株式会社 Mounting structure
WO2020158807A1 (en) * 2019-01-30 2020-08-06 京セラ株式会社 Optical sensor and optical sensor device using same

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1174312A (en) * 1997-08-28 1999-03-16 Mitsubishi Electric Corp Semiconductor device and method for forming solder bump
JP2002164473A (en) * 2000-11-29 2002-06-07 Sharp Corp Semiconductor device and method for manufacturing the same
JP2007115789A (en) * 2005-10-19 2007-05-10 Matsushita Electric Ind Co Ltd Laminated semiconductor device and its manufacturing method
JP4703356B2 (en) * 2005-10-19 2011-06-15 パナソニック株式会社 Multilayer semiconductor device
JP2009267117A (en) * 2008-04-25 2009-11-12 Nec Corp Semiconductor device, substrate, and method for mounting semiconductor device
US9345133B2 (en) 2012-02-28 2016-05-17 Canon Kabushiki Kaisha Printed circuit board and method of mounting components on the printed circuit board
JP2019009470A (en) * 2018-10-09 2019-01-17 パナソニックIpマネジメント株式会社 Mounting structure
WO2020158807A1 (en) * 2019-01-30 2020-08-06 京セラ株式会社 Optical sensor and optical sensor device using same

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