JP2011228604A - Manufacturing method of circuit board and circuit board - Google Patents

Manufacturing method of circuit board and circuit board Download PDF

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Publication number
JP2011228604A
JP2011228604A JP2010099442A JP2010099442A JP2011228604A JP 2011228604 A JP2011228604 A JP 2011228604A JP 2010099442 A JP2010099442 A JP 2010099442A JP 2010099442 A JP2010099442 A JP 2010099442A JP 2011228604 A JP2011228604 A JP 2011228604A
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solder
insulating substrate
circuit board
conductive layer
circuit element
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Tomoko Yamada
友子 山田
Tsugio Masuda
次男 増田
Masami Ogura
正巳 小倉
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Honda Motor Co Ltd
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Honda Motor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]

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  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Supply And Installment Of Electrical Components (AREA)
  • Die Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a circuit board capable of securing an endurance reliability and a heat characteristic at a specific level or above.SOLUTION: The circuit board includes an insulating substrate having a conductive layer and a circuit element, and the conductive layer of the insulating substrate and the circuit element are bonded by a solder. The manufacturing method of the circuit board includes an arranging process (step ST1) for arranging a regulating member for regulating an interval between the conductive layer of the insulating substrate and the circuit element on a solder sheet constituted of the solder, a laminating process (step ST2) for laminating the insulating substrate, the solder sheet where the regulating member is arranged and the circuit element in this order, and a bonding process (step ST3) for heating the insulating substrate, the solder sheet and the circuit element, which are laminated, under a reduction atmosphere and for fusing the solder sheet so as to bond the insulating substrate and the circuit element.

Description

本発明は、はんだシートを用いて回路素子と絶縁基板とが接合される回路基板の製造方法及び回路基板に関する。詳しくは、耐久信頼性及び熱特性を一定以上に確保することが可能な回路基板の製造方法及び回路基板に関する。   The present invention relates to a method for manufacturing a circuit board in which a circuit element and an insulating substrate are bonded using a solder sheet, and a circuit board. Specifically, the present invention relates to a circuit board manufacturing method and a circuit board capable of ensuring a certain level of durability reliability and thermal characteristics.

従来より、パワーモジュール用半導体素子等の回路素子の絶縁基板への接合には、熱伝導及び電気伝導が共に良好でかつ安価なはんだが用いられている。はんだには、一般的に、酸化防止と接合性向上の役割を持つ活性剤が含有されていることが多い。この活性剤は、回路素子の絶縁基板への接合にも寄与する。この活性剤を含有したはんだによる回路素子の接合は、後の製造工程において、ワイヤボンディングの密着力低下や樹脂封入不足等を誘発する。このため、当該はんだから活性剤を洗浄して完全に除去する必要があるが、洗浄管理不足による残渣の発生や、洗浄不足を招くことが多かった。そのため、活性剤を含有しないはんだと、水素や蟻酸等の還元ガスとを用いた回路基板の製造方法も提供されている。   Conventionally, solder having good heat conduction and electric conduction and low cost has been used for bonding circuit elements such as power module semiconductor elements to an insulating substrate. In general, the solder often contains an activator having the role of preventing oxidation and improving the bondability. This activator also contributes to the bonding of the circuit element to the insulating substrate. The joining of the circuit element with the solder containing the activator induces a decrease in the adhesion of wire bonding, insufficient resin encapsulation, and the like in a later manufacturing process. For this reason, it is necessary to clean and remove the activator from the solder, but there are many cases in which a residue is generated due to insufficient cleaning management or insufficient cleaning. Therefore, a circuit board manufacturing method using a solder that does not contain an activator and a reducing gas such as hydrogen or formic acid is also provided.

このような製造方法においては、回路素子と絶縁基板との間の接合面での密着力を得るために、回路素子に対して錘荷重が加えられて、回路素子と絶縁基板とが、はんだにより接合される。このようなはんだによる接合を以下、「はんだ接合」という。
このような製造方法に適用可能な技術として、例えば、セラミックス回路基板（絶縁基板）の裏面へワイヤバンプを施し、当該裏面とヒートシンクとをはんだにより接合する技術が、例えば特許文献１に記載されている。なお、このような技術を、以下、「特許文献１に記載の技術」という。特許文献１に記載の手法を適用することで、はんだの接合時に発生するセラミックス回路基板の傾きを抑制することが可能になる。
また、はんだの濡れ性を良好にし、はんだが想定外の領域を超えて流出しないようにする流出抑止手段を備えた回路基板を提供する技術が、特許文献２に記載されている。なお、このような技術を、以下、「特許文献２に記載の技術」という。 In such a manufacturing method, in order to obtain adhesion at the joint surface between the circuit element and the insulating substrate, a weight load is applied to the circuit element, and the circuit element and the insulating substrate are soldered. Be joined. Hereinafter, such solder bonding is referred to as “solder bonding”.
As a technique applicable to such a manufacturing method, for example, Patent Document 1 discloses a technique in which wire bumps are applied to the back surface of a ceramic circuit board (insulating substrate) and the back surface and the heat sink are joined by solder. . Such a technique is hereinafter referred to as “a technique described in Patent Document 1”. By applying the method described in Patent Document 1, it is possible to suppress the tilt of the ceramic circuit board that occurs during solder bonding.
Further, Patent Document 2 discloses a technique for providing a circuit board provided with outflow suppressing means that improves solder wettability and prevents the solder from flowing out beyond an unexpected region. Such a technique is hereinafter referred to as “a technique described in Patent Document 2”.

特開２００２−１５８３２８号公報JP 2002-158328 A 特開２００４−１１９９４４号公報JP 2004-119944 A

しかし、上記特許文献１に記載の技術は、セラミックス回路基板の傾きを抑制しているものの、回路素子の傾きが考慮されていない。そのため、はんだ接合時に回路素子の傾きが発生すると、はんだ接合部における厚みの薄い箇所は、回路素子とはんだの線膨張係数の差により歪が発生し、素子側のはんだ部分の亀裂進展が加速され、熱特性（放熱性）の悪化や耐久信頼性の低下を招く虞があった。   However, although the technique described in Patent Document 1 suppresses the tilt of the ceramic circuit board, the tilt of the circuit element is not taken into consideration. For this reason, if a tilt of the circuit element occurs during solder joining, distortion occurs in the thin part of the solder joint due to the difference in linear expansion coefficient between the circuit element and the solder, and the crack progress of the solder part on the element side is accelerated. There is a risk of deteriorating thermal characteristics (heat dissipation) and lowering durability reliability.

また、上記特許文献２に記載の技術は、はんだが想定外の領域を超えて流出しないものの、回路素子の傾きを抑制する手段を備えていない。そのため、上記特許文献１に記載の技術の場合と同様に、はんだ接合時に回路素子の傾きが発生すると、素子側のはんだ部分の亀裂進展が加速され、熱特性の悪化や耐久信頼性の低下を招く虞があった。   Moreover, although the technique of the said patent document 2 is not provided with the means to suppress the inclination of a circuit element, although a solder does not flow out exceeding the area | region beyond assumption. Therefore, as in the case of the technique described in Patent Document 1, when the inclination of the circuit element occurs at the time of soldering, the crack progress of the solder portion on the element side is accelerated, which deteriorates the thermal characteristics and the durability reliability. There was a risk of inviting.

従って、耐久信頼性及び熱特性を一定以上に確保することが可能な回路基板が近年要求されている。   Therefore, there is a recent demand for a circuit board capable of ensuring a certain level of durability reliability and thermal characteristics.

本発明は、このような状況に鑑みてなされたものであり、はんだシートを用いて回路素子と絶縁基板とが接合される回路基板の製造方法及び回路基板であって、耐久信頼性及び熱特性を一定以上に確保することが可能な回路基板の製造方法及び回路基板を提供することを目的とする。   The present invention has been made in view of such a situation, and is a circuit board manufacturing method and a circuit board in which a circuit element and an insulating substrate are bonded using a solder sheet, and includes durability reliability and thermal characteristics. It is an object of the present invention to provide a circuit board manufacturing method and a circuit board capable of ensuring a certain level or more.

本発明は、導電層（例えば、後述の表面側導電層３，裏面側導電層４）を有する絶縁基板（例えば、後述の絶縁基板２）と回路素子（例えば、後述の半導体素子５）とを備え、前記絶縁基板の前記導電層と前記回路素子とがはんだにより接合される回路基板（例えば、後述の半導体基板１）の製造方法であって、前記はんだで構成されるはんだシート（例えば、後述のはんだシート７）に、前記絶縁基板の前記導電層と前記回路素子との間隔（例えば、後述の間隔ｄ）を規制する規制部材（例えば、後述の突起部材８）を配設する配設工程（例えば、後述のステップＳＴ１の配設工程）と、前記絶縁基板、前記規制部材が配設された前記はんだシート、及び前記回路素子を、その順番で積層する積層工程（例えば、後述のステップＳＴ２の積層工程）と、積層されている前記絶縁基板、前記はんだシート及び前記回路素子を、還元雰囲気（例えば、後述の還元ガス１２）下において加熱して前記はんだシートを溶融することによって、前記絶縁基板と前記回路素子とを接合する接合工程（例えば、後述のステップＳＴ３の接合工程）と、を含むことを特徴とする。   In the present invention, an insulating substrate (for example, an insulating substrate 2 to be described later) having a conductive layer (for example, a surface side conductive layer 3 and a back surface side conductive layer 4 to be described later) and a circuit element (for example, a semiconductor element 5 to be described later) are provided. And a manufacturing method of a circuit board (for example, a semiconductor substrate 1 described later) in which the conductive layer of the insulating substrate and the circuit element are joined by solder, and a solder sheet (for example, described later) made of the solder A disposing step of disposing a regulating member (for example, a protruding member 8 described later) for controlling a distance (for example, a space d described later) between the conductive layer of the insulating substrate and the circuit element on the solder sheet 7). (E.g., an arrangement process in step ST <b> 1 described later), and a lamination process (e.g., step ST <b> 2 described later) in which the insulating substrate, the solder sheet on which the regulating member is disposed, and the circuit element are stacked in that order. Product of Step) and heating the laminated insulating substrate, the solder sheet, and the circuit element under a reducing atmosphere (for example, a reducing gas 12 described later) to melt the solder sheet, A bonding step of bonding the circuit elements (for example, a bonding step in step ST3 described later).

この発明によれば、はんだシートに規制部材が配設されることにより、はんだシートと回路素子との間に、規制部材の高さに相当する隙間が形成される。そのため、この隙間に還元雰囲気が十分に供給され、接合面におけるはんだの濡れ性を向上することができ、接合の信頼性を向上することができる。また、回路素子が、絶縁基板に対して傾いて接合されることを抑制することができ、はんだの厚みを均一にすることができる。つまり、はんだ厚みの不均一に基づく亀裂の発生及び進展を抑制することができ、放熱性の悪化（熱特性の信頼性の低下）を抑制することができる。従って、回路基板の耐久信頼性及び熱特性を一定以上に確保することができる。   According to this invention, by providing the restriction member on the solder sheet, a gap corresponding to the height of the restriction member is formed between the solder sheet and the circuit element. Therefore, a reducing atmosphere is sufficiently supplied to the gap, so that the wettability of the solder on the joint surface can be improved, and the reliability of the joint can be improved. Moreover, it can suppress that a circuit element inclines and is joined with respect to an insulated substrate, and can make thickness of solder uniform. That is, it is possible to suppress the generation and progress of cracks based on the unevenness of the solder thickness, and it is possible to suppress deterioration in heat dissipation (decrease in reliability of thermal characteristics). Therefore, the durability reliability and thermal characteristics of the circuit board can be ensured to a certain level or more.

この場合、前記規制部材（例えば、後述の突起部材８）は、前記はんだよりも、融点が高く、かつ、はんだ濡れ性が低い金属素材からなることが好ましい。   In this case, it is preferable that the regulating member (for example, a protruding member 8 described later) is made of a metal material having a higher melting point and lower solder wettability than the solder.

この発明によれば、はんだシートが、はんだの融点よりも高く、かつ、規制部材の融点よりも低い所定の温度で加熱される場合に、はんだシートのみが溶融し、規制部材は、溶融せずにはんだ内に固体の状態で残る。また、規制部材は、はんだよりも、はんだ濡れ性が低いので、溶融したはんだは、規制部材の周囲に容易に流動する。
従って、絶縁基板の導電層と回路素子との間に、規制部材の高さに相当する間隔が確実に設定され、はんだの厚みを均一にすることができる。 According to the present invention, when the solder sheet is heated at a predetermined temperature higher than the melting point of the solder and lower than the melting point of the regulating member, only the solder sheet is melted, and the regulating member is not melted. It remains in a solid state in the solder. Further, since the regulating member has lower solder wettability than solder, the melted solder easily flows around the regulating member.
Therefore, an interval corresponding to the height of the regulating member is reliably set between the conductive layer of the insulating substrate and the circuit element, and the thickness of the solder can be made uniform.

この場合、前記規制部材（例えば、後述の突起部材８）には、アルミニウムを主成分とする金属素材（例えば、後述のアルミニウム合金）を用いることができる。   In this case, a metal material (for example, an aluminum alloy described later) containing aluminum as a main component can be used for the regulating member (for example, a protruding member 8 described later).

この発明によれば、規制部材に汎用性のある金属素材を用いることにより、製造コストを低減することができる。   According to this invention, the manufacturing cost can be reduced by using a versatile metal material for the regulating member.

この場合、前記規制部材（例えば、後述の突起部材８）は、ボンディングワイヤからなることが好ましい。   In this case, it is preferable that the restriction member (for example, a protruding member 8 described later) is made of a bonding wire.

この発明によれば、規制部材を、ボンディングワイヤとすることで、ワイヤボンディングするための新たな装置は不要であり、既存の装置を利用することできる。また、ワイヤボンディングすることにより、規制部材をはんだシートに容易かつ迅速に配設することができる。特に、規制部材を、予めはんだシートにワイヤボンディングすることで、量産工程への自動供給が可能となる。   According to the present invention, since the regulating member is a bonding wire, a new device for wire bonding is unnecessary, and an existing device can be used. Further, by performing wire bonding, the regulating member can be easily and quickly disposed on the solder sheet. In particular, the regulation member can be automatically supplied to the mass production process by wire bonding to the solder sheet in advance.

この場合、前記はんだシート（例えば、後述のはんだシート７）は、平面視で矩形状に形成され、前記規制部材（例えば、後述の突起部材８）は、前記はんだシートにおける対向する二辺（例えば、後述の辺７ｃ，７ｄ）に沿って配設されることが好ましい。   In this case, the solder sheet (for example, a later-described solder sheet 7) is formed in a rectangular shape in a plan view, and the regulation member (for example, a later-described projecting member 8) is formed on two opposite sides (for example, the solder sheet, for example). It is preferable to be disposed along the sides 7c and 7d) described later.

この発明によれば、前記積層工程において、はんだシートの規制部材の上に回路素子を安定して載置することができると共に、前記接合工程において、はんだシートが溶融した場合にも規制部材によって回路素子を支持することができる。これにより、絶縁基板に対する回路素子の傾きの発生を抑制することができ、はんだの厚みを均一化することができる。従って、はんだからなる接合部に亀裂（クラック）が発生することを抑制することができ、回路基板の耐久信頼性を向上することができる。   According to the present invention, in the laminating step, the circuit element can be stably placed on the restriction member of the solder sheet, and the circuit is also provided by the restriction member even when the solder sheet is melted in the joining step. The element can be supported. Thereby, generation | occurrence | production of the inclination of the circuit element with respect to an insulated substrate can be suppressed, and the thickness of solder can be equalize | homogenized. Therefore, it is possible to suppress the occurrence of cracks in the joint portion made of solder, and it is possible to improve the durability reliability of the circuit board.

この場合、前記はんだシート（例えば、後述のはんだシート７）は、鉛フリーはんだからなることが好ましい。   In this case, the solder sheet (for example, a solder sheet 7 described later) is preferably made of lead-free solder.

この発明によれば、回路基板において、鉛を含まないはんだ接合部を構成することができ、環境に優しい回路基板を提供することができる。   According to the present invention, a solder joint that does not contain lead can be formed in a circuit board, and an environment-friendly circuit board can be provided.

また、本発明の回路基板（例えば、後述の半導体基板１）は、導電層（例えば、後述の表面側導電層３，裏面側導電層４）を有する絶縁基板（例えば、後述の絶縁基板２）と、回路素子（例えば、後述の半導体素子５）と、前記絶縁基板の前記導電層と前記回路素子とをはんだにより接合している接合部（例えば、後述の接合部６）と、を備え、前記接合部には、前記絶縁基板の前記導電層と前記回路素子との間隔（例えば、後述の間隔ｄ）を規制する規制部材（例えば、後述の突起部材８）が設けられていることを特徴とする。   A circuit board (for example, a semiconductor substrate 1 described later) of the present invention is an insulating substrate (for example, an insulating substrate 2 described later) having a conductive layer (for example, a front surface side conductive layer 3 and a back surface side conductive layer 4 described later). And a circuit element (for example, a semiconductor element 5 described later), and a joint (for example, a joint 6 described later) for joining the conductive layer of the insulating substrate and the circuit element by solder, The joint is provided with a regulating member (for example, a projection member 8 to be described later) that regulates an interval (for example, a distance d to be described later) between the conductive layer of the insulating substrate and the circuit element. And

この発明によれば、規制部材を設けたことによって、回路素子が絶縁基板に対して傾いて接合されることを抑制することができ、接合部（はんだ）の厚みを均一にすることができる。従って、はんだ厚みの不均一に基づく亀裂の発生及び進展を抑制することができ、放熱性の悪化（熱特性の信頼性の低下）を抑制することができる。従って、耐久信頼性及び熱特性を一定以上に確保することができる。   According to this invention, by providing the regulating member, it is possible to suppress the circuit element from being inclined and joined to the insulating substrate, and the thickness of the joint (solder) can be made uniform. Therefore, it is possible to suppress the generation and progress of cracks based on the unevenness of the solder thickness, and it is possible to suppress the deterioration of heat dissipation (reduction in the reliability of the thermal characteristics). Therefore, durability reliability and thermal characteristics can be secured above a certain level.

本発明によれば、耐久信頼性及び熱特性を一定以上に確保することが可能な回路基板の製造方法及び回路基板を提供することができる。   ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method and circuit board of a circuit board which can ensure durability reliability and thermal characteristics more than fixed can be provided.

本発明の実施形態の半導体基板を示す断面図である。It is sectional drawing which shows the semiconductor substrate of embodiment of this invention. 半導体基板の積層構造を分解して示す断面図である。It is sectional drawing which decomposes | disassembles and shows the laminated structure of a semiconductor substrate. はんだシートの表面に配設された突起部材を示す平面図である。It is a top view which shows the protrusion member arrange | positioned on the surface of a solder sheet. 突起部材の配設位置とはんだ歪みとの関係を示す図である。It is a figure which shows the relationship between the arrangement | positioning position of a protrusion member, and solder distortion. 本発明の実施形態の半導体基板の製造方法を示すフローチャートである。It is a flowchart which shows the manufacturing method of the semiconductor substrate of embodiment of this invention. 図５の製造方法における接合工程において絶縁基板と半導体素子との間に還元ガスが供給される様子を示す図である。It is a figure which shows a mode that a reducing gas is supplied between an insulated substrate and a semiconductor element in the joining process in the manufacturing method of FIG.

以下に、本発明の実施形態の半導体基板について図１から図４を参照しながら説明する。図１は、本発明の実施形態の半導体基板を示す断面図であり、完成した半導体基板を示している。図２は、半導体基板の積層構造を分解して示す断面図であり、完成前の半導体基板を示している。図３は、はんだシートの表面に配設された突起部材を示す平面図である。図４は、突起部材の配設位置とはんだ歪みとの関係を示す図である。   Hereinafter, a semiconductor substrate according to an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a sectional view showing a semiconductor substrate according to an embodiment of the present invention, and shows a completed semiconductor substrate. FIG. 2 is an exploded cross-sectional view showing the laminated structure of the semiconductor substrate, and shows the semiconductor substrate before completion. FIG. 3 is a plan view showing a protruding member disposed on the surface of the solder sheet. FIG. 4 is a diagram illustrating the relationship between the position where the protruding member is disposed and the solder strain.

本実施形態の回路基板として、自動車等における電源装置（例えば、モータ駆動用の電源装置）のパワーモジュール（半導体装置）に用いられる半導体基板１を例にして説明する。
半導体基板１は、導電層としての表面側導電層３及び裏面側導電層４を有する絶縁基板２と、回路素子としての半導体素子５と、絶縁基板２と半導体素子５とをはんだにより接合している接合部６と、接合部６に設けられる規制部材としての突起部材８と、を備える。 As a circuit board of this embodiment, a semiconductor substrate 1 used for a power module (semiconductor device) of a power supply device (for example, a power supply device for driving a motor) in an automobile or the like will be described as an example.
The semiconductor substrate 1 is formed by joining an insulating substrate 2 having a front-side conductive layer 3 and a back-side conductive layer 4 as conductive layers, a semiconductor element 5 as a circuit element, and the insulating substrate 2 and the semiconductor element 5 with solder. And a protruding member 8 as a restricting member provided at the joint 6.

絶縁基板２は、電気絶縁性を有する基板であり、例えば、セラミックス等からなる。絶縁基板２は、例えば、平面視で矩形状に形成されている。
表面側導電層３は、絶縁基板２の表面２ａに設けられている。ここで、絶縁基板２の表面２ａとは、絶縁基板２の外表面であって、半導体素子５に対向する側の面をいう。図１及び図２においては、絶縁基板２の上面に該当する。表面側導電層３は、例えば、銅やアルミニウム等の導電パターン（金属回路層）として構成されている。 The insulating substrate 2 is a substrate having electrical insulation, and is made of, for example, ceramics. For example, the insulating substrate 2 is formed in a rectangular shape in plan view.
The surface side conductive layer 3 is provided on the surface 2 a of the insulating substrate 2. Here, the surface 2 a of the insulating substrate 2 is an outer surface of the insulating substrate 2 and is a surface facing the semiconductor element 5. 1 and 2 correspond to the upper surface of the insulating substrate 2. The surface side conductive layer 3 is configured as a conductive pattern (metal circuit layer) such as copper or aluminum.

裏面側導電層４は、絶縁基板２の裏面２ｂに設けられている。ここで、絶縁基板２の裏面２ｂとは、絶縁基板２の外表面であって、表面２ａと逆側の面をいう。図１及び図２においては、絶縁基板２の下面に該当する。裏面側導電層４も、例えば、銅やアルミニウム等の導電パターンとして構成されている。   The back surface side conductive layer 4 is provided on the back surface 2 b of the insulating substrate 2. Here, the back surface 2b of the insulating substrate 2 is an outer surface of the insulating substrate 2 and is a surface opposite to the front surface 2a. 1 and 2 correspond to the lower surface of the insulating substrate 2. The back side conductive layer 4 is also configured as a conductive pattern such as copper or aluminum.

半導体素子５は、例えば、インバータ回路を構成する素子群、具体的には例えば、スイッチング素子であるＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ Ｇａｔｅ Ｂｉｐｏｌａｒ Ｔｒａｎｓｉｓｔｏｒ：絶縁ゲート型バイポーラ・トランジスタ）、及びＦＷＤ（Ｆｒｅｅ Ｗｈｅｅｌｉｎｇ Ｄｉｏｄｅ：転流ダイオード）を含む素子群である。   The semiconductor element 5 includes, for example, an element group constituting an inverter circuit, specifically, an IGBT (Insulated Gate Bipolar Transistor) that is a switching element, and an FWD (Free Wheeling Diode): a commutation diode. ).

この半導体素子５は、素子毎に物理的に分離される場合もあるが、本実施形態では説明の便宜上、平面視で矩形状に形成されている。半導体素子５の裏面５ａには、絶縁基板２の表面側導電層３とはんだにより接合可能な所定の導電パターン（図示せず）を有している。ここで、半導体素子５の裏面５ａとは、半導体素子５の外表面であって、絶縁基板２に対向する側の面をいう。図１及び図２においては、半導体素子５の裏面５ａは、半導体素子５の下面に該当する。半導体素子５の表面（上面）には、符号５ｂを付してある。   Although the semiconductor element 5 may be physically separated for each element, in the present embodiment, for convenience of explanation, the semiconductor element 5 is formed in a rectangular shape in plan view. The back surface 5a of the semiconductor element 5 has a predetermined conductive pattern (not shown) that can be bonded to the front surface side conductive layer 3 of the insulating substrate 2 by solder. Here, the back surface 5 a of the semiconductor element 5 refers to the outer surface of the semiconductor element 5 and the surface facing the insulating substrate 2. 1 and 2, the back surface 5 a of the semiconductor element 5 corresponds to the lower surface of the semiconductor element 5. The surface (upper surface) of the semiconductor element 5 is denoted by reference numeral 5b.

図１に示すように、接合部６は、絶縁基板２の表面側導電層３と半導体素子５の裏面５ａとをはんだにより接合している部分である。
接合部６には、２つの突起部材８が設けられている。突起部材８については、後述する。 As shown in FIG. 1, the joint portion 6 is a portion where the surface-side conductive layer 3 of the insulating substrate 2 and the back surface 5 a of the semiconductor element 5 are joined by solder.
Two protruding members 8 are provided in the joint portion 6. The protruding member 8 will be described later.

ここで、図２及び図３を参照して、接合部６の製造方法の概略について説明する。
接合部６は、後述する接合工程（図５におけるステップＳＴ３参照）において、図２に示すように、はんだシート７が溶融した後、固化することにより形成される。
図２及び図３に示すように、はんだシート７は、シート状に構成されたはんだである。はんだシート７は、例えば、鉛を含有しない鉛フリーはんだからなる。はんだシート７は、図３に示すように、平面視で矩形状に形成されており、平面視で半導体素子５とほぼ同じ大きさ（面積）となっている。 Here, with reference to FIG.2 and FIG.3, the outline of the manufacturing method of the junction part 6 is demonstrated.
In the joining process described later (see step ST3 in FIG. 5), the joining portion 6 is formed by solidifying after the solder sheet 7 is melted, as shown in FIG.
As shown in FIG.2 and FIG.3, the solder sheet 7 is the solder comprised in the sheet form. The solder sheet 7 is made of, for example, lead-free solder that does not contain lead. As shown in FIG. 3, the solder sheet 7 is formed in a rectangular shape in plan view, and has almost the same size (area) as the semiconductor element 5 in plan view.

図２及び図３に示すように、はんだシート７の表面７ａには、２つの突起部材８が配設されている。ここで、はんだシート７の表面７ａとは、はんだシート７の外表面であって、半導体素子５に対向する側の面をいう。図２においては、はんだシート７の表面７ａは、はんだシート７の上面に該当する。はんだシート７の裏面（下面）には、符号７ｂを付してある。   As shown in FIGS. 2 and 3, two protruding members 8 are disposed on the surface 7 a of the solder sheet 7. Here, the surface 7 a of the solder sheet 7 refers to the outer surface of the solder sheet 7 and the surface facing the semiconductor element 5. In FIG. 2, the surface 7 a of the solder sheet 7 corresponds to the upper surface of the solder sheet 7. Reference numeral 7 b is attached to the back surface (lower surface) of the solder sheet 7.

突起部材８は、後述する接合工程（図４におけるステップＳＴ３参照）において、はんだシート７が溶融した場合に、絶縁基板２の表面側導電層３と半導体素子５の裏面５ａとの間隔ｄ（図１参照）を規制するように、接合部６内に配設される。この間隔ｄ、つまり、突起部材８の高さは、はんだ接合の信頼性を確保できる最小の寸法として規定され、同時に、半導体素子５から絶縁基板２への放熱性を確保できる寸法として規定される。突起部材８は、例えば、断面形状がほぼ円形となっている。２つの突起部材８の高さ（直径）は、ほぼ同じである。   When the solder sheet 7 is melted in a joining step (see step ST3 in FIG. 4) described later, the protruding member 8 has an interval d (see FIG. 4) between the front surface side conductive layer 3 of the insulating substrate 2 and the back surface 5a of the semiconductor element 5. 1) is disposed in the joint portion 6 so as to regulate. This distance d, that is, the height of the protruding member 8 is defined as a minimum dimension that can ensure the reliability of solder joints, and at the same time, is defined as a dimension that can ensure heat dissipation from the semiconductor element 5 to the insulating substrate 2. . For example, the protruding member 8 has a substantially circular cross-sectional shape. The height (diameter) of the two protruding members 8 is substantially the same.

２つの突起部材８は、図２及び図３に示すように、矩形状のはんだシート７における対向する２つの辺（二辺）７ｃ，７ｄに沿ってほぼ平行に配設されている。つまり、２つの突起部材８は、半導体素子５の裏面５ａにおける両端部側に対応してそれぞれ配置される。   As shown in FIGS. 2 and 3, the two protruding members 8 are disposed substantially in parallel along two opposing sides (two sides) 7 c and 7 d of the rectangular solder sheet 7. That is, the two protruding members 8 are respectively arranged corresponding to both end portions on the back surface 5 a of the semiconductor element 5.

具体的には、突起部材８は、はんだシート７において、辺７ｃ又は辺７ｄから少なくとも１．５ｍｍ以上内方の位置に配設されることが好ましい。その理由は、図４に示すように、辺７ｃ又は辺７ｄ（図４の横軸において、０ｍｍの位置に相当）から少なくとも１．５ｍｍ以上内方の位置に突起部材８が配設されていれば、接合部６にはんだ歪みが生じにくくなり、この歪みに起因した亀裂（クラック）の発生を抑制できるからである。ここで、図４の縦軸に示すはんだ歪みは、その数値が１よりも大きい場合に、所定方向にはんだ歪みが生じており、その数値が１である場合に、はんだ歪みが生じていないことを意味する。   Specifically, the protruding member 8 is preferably disposed in the solder sheet 7 at a position that is at least 1.5 mm or more inward from the side 7c or the side 7d. The reason for this is that, as shown in FIG. 4, the protruding member 8 is disposed at an inner position of at least 1.5 mm or more from the side 7c or the side 7d (corresponding to a position of 0 mm on the horizontal axis in FIG. 4). This is because solder distortion is less likely to occur in the joint 6 and the occurrence of cracks due to this distortion can be suppressed. Here, when the numerical value of the solder strain shown on the vertical axis in FIG. 4 is larger than 1, solder strain is generated in a predetermined direction, and when the numerical value is 1, no solder strain is generated. Means.

突起部材８は、例えばアルミニウムを主成分とする金属素材からなる。ここで、アルミニウムを主成分とする金属素材とは、アルミニウムの成分比率（含有量）が大きい金属素材、すなわち、アルミニウム合金をいう。以下、このようなアルミニウム合金を単にアルミニウムという。アルミニウムは、はんだシート７の素材であるはんだよりも、融点が高く、かつ、はんだ濡れ性（溶けたはんだが、濡れ広がる程度）が低い金属素材である。   The protruding member 8 is made of, for example, a metal material whose main component is aluminum. Here, the metal material mainly composed of aluminum refers to a metal material having a large aluminum component ratio (content), that is, an aluminum alloy. Hereinafter, such an aluminum alloy is simply referred to as aluminum. Aluminum is a metal material having a higher melting point and lower solder wettability (the degree to which the melted solder spreads wet) than the solder that is the material of the solder sheet 7.

具体的には、突起部材８は、アルミニウム製のボンディングワイヤからなる。このアルミニウム製のボンディングワイヤは、一般的に、半導体素子５の表面側電極（図示せず）と、図示しない樹脂ケース等に設けられた外部端子とを電気的に接合（ワイヤボンディング）する際に配線として用いられるワイヤである。すなわち、本実施形態では、配線用のボンディングワイヤが突起部材８として流用されている。   Specifically, the protruding member 8 is made of an aluminum bonding wire. This aluminum bonding wire is generally used for electrically bonding (wire bonding) a surface side electrode (not shown) of the semiconductor element 5 and an external terminal provided on a resin case (not shown). It is a wire used as wiring. That is, in the present embodiment, a bonding wire for wiring is used as the protruding member 8.

なお、絶縁基板２の裏面側導電層４には、半導体素子５からの放熱性を向上するために、図示しない金属製放熱板（ヒートシンク）が、はんだ等を用いて固着される。この放熱板は、絶縁基板２よりも厚く、銅やアルミニウム等により構成されている。   In addition, in order to improve the heat dissipation from the semiconductor element 5, a metal heat sink (not shown) is fixed to the back surface side conductive layer 4 of the insulating substrate 2 using solder or the like. This heat sink is thicker than the insulating substrate 2 and is made of copper, aluminum, or the like.

次に、半導体基板１の製造方法について図５及び図６を参照しながら説明する。図５は、本発明の実施形態の半導体基板１の製造方法を示すフローチャートである。図６は、図５の製造方法における接合工程において絶縁基板と半導体素子との間に還元ガスが供給される様子を示す図である。
なお、以下、説明の便宜上、半導体基板１を製造する動作主体は、図示しない装置（ロボットを含む）であるとする。ただし、装置以外の動作主体、例えば作業者等の自然人が、以下のステップの少なくとも一部を実行してもよい。 Next, a method for manufacturing the semiconductor substrate 1 will be described with reference to FIGS. FIG. 5 is a flowchart showing a method for manufacturing the semiconductor substrate 1 according to the embodiment of the present invention. FIG. 6 is a diagram illustrating a state in which a reducing gas is supplied between the insulating substrate and the semiconductor element in the bonding step in the manufacturing method of FIG.
Hereinafter, for convenience of explanation, it is assumed that an operation subject for manufacturing the semiconductor substrate 1 is an apparatus (including a robot) (not shown). However, an operating entity other than the apparatus, for example, a natural person such as an operator, may execute at least a part of the following steps.

図５に示すように、ステップＳＴ１において、装置は、配設工程の動作を実施する。この配設工程は、装置が、はんだシート７（図２及び図３参照）の所定箇所に突起部材８を配設する工程である。例えば、装置は、突起部材８となるアルミニウム製のボンディングワイヤをワイヤボンディングすることにより、突起部材８をはんだシート７に配設する。これにより、図６に示すように、はんだシート７の表面７ａには、突起部材８が配設された部分と配設されていない部分において、突起部材８の高さ（間隔ｄ）に相当する高低差ができる。   As shown in FIG. 5, in step ST <b> 1, the apparatus performs an operation of an arrangement process. This arrangement | positioning process is a process in which the apparatus arrange | positions the protrusion member 8 in the predetermined location of the solder sheet 7 (refer FIG.2 and FIG.3). For example, the apparatus disposes the protruding member 8 on the solder sheet 7 by wire bonding an aluminum bonding wire to be the protruding member 8. As a result, as shown in FIG. 6, the surface 7 a of the solder sheet 7 corresponds to the height (interval d) of the protruding member 8 in the portion where the protruding member 8 is disposed and the portion where the protruding member 8 is not disposed. Height difference is possible.

次に、ステップＳＴ２において、装置は、積層工程の動作を実施する。この積層工程は、図６に示すように、装置が、絶縁基板２、突起部材８が配設されたはんだシート７、及び半導体素子５を、その順番で同図中上方向に積層する工程である。その際、積層される各部材間の密着力を得るために、装置は、所定の錘１０を半導体素子５の表面５ｂ（上面）に載置する。
はんだシート７の表面７ａには、突起部材８が配設されているので、はんだシート７の表面７ａと半導体素子５の裏面５ａとの間には、間隔ｄの隙間が形成される。 Next, in step ST2, the apparatus performs an operation of a stacking process. As shown in FIG. 6, this stacking process is a process in which the apparatus stacks the insulating substrate 2, the solder sheet 7 provided with the protruding members 8, and the semiconductor element 5 in the order in the upward direction in the figure. is there. At this time, the apparatus places a predetermined weight 10 on the surface 5 b (upper surface) of the semiconductor element 5 in order to obtain adhesion between the stacked members.
Since the protruding member 8 is disposed on the front surface 7 a of the solder sheet 7, a gap d is formed between the front surface 7 a of the solder sheet 7 and the back surface 5 a of the semiconductor element 5.

次に、ステップＳＴ３において、装置は、接合工程の動作を実施する。この接合工程は、図６に示すように、装置が、ステップＳＴ２において積層された絶縁基板２、はんだシート７、半導体素子５及び錘１０を、リフロー炉（図示せず）内に入れ、還元ガス１２を供給しながら、所定の温度で加熱してはんだシート７を溶融することによって、絶縁基板２と半導体素子５とをはんだ接合する工程である。   Next, in step ST3, the apparatus performs an operation of a bonding process. As shown in FIG. 6, in this joining process, the apparatus puts the insulating substrate 2, the solder sheet 7, the semiconductor element 5 and the weight 10 laminated in step ST2 into a reflow furnace (not shown), and a reducing gas. In this process, the insulating substrate 2 and the semiconductor element 5 are soldered together by melting the solder sheet 7 by heating at a predetermined temperature while supplying 12.

還元ガス１２としては、例えば、水素ガスが用いられる。水素ガスを用いた還元反応によれば、汚染物質を発生させず、水（水蒸気）のみが発生するため、環境にとって好ましい。   As the reducing gas 12, for example, hydrogen gas is used. According to the reduction reaction using hydrogen gas, pollutants are not generated and only water (water vapor) is generated, which is preferable for the environment.

はんだシート７の表面７ａに突起部材８を配設したことにより、はんだシート７の表面７ａと半導体素子５の裏面５ａとの間には、上記間隔ｄの隙間が形成されている。そのため、この隙間によって水素ガスの流路を確保することができ、この隙間に水素ガスを十分に供給することができる。   By disposing the protruding member 8 on the surface 7 a of the solder sheet 7, the gap d is formed between the surface 7 a of the solder sheet 7 and the back surface 5 a of the semiconductor element 5. Therefore, the flow path of hydrogen gas can be secured by this gap, and hydrogen gas can be sufficiently supplied to this gap.

この隙間に水素ガスが供給されると、水素ガスの還元作用により、溶融したはんだに含まれる酸化物が除去されると共に、絶縁基板２の表面側導電層３と半導体素子５の裏面５ａに形成されている酸化皮膜等も除去される。従って、はんだの濡れ性が向上し、はんだ接合の信頼性が向上する。   When hydrogen gas is supplied to the gap, the oxide contained in the molten solder is removed by the reducing action of the hydrogen gas, and is formed on the surface side conductive layer 3 of the insulating substrate 2 and the back surface 5a of the semiconductor element 5. The oxidized film and the like that have been removed are also removed. Therefore, the wettability of the solder is improved and the reliability of the solder joint is improved.

加熱時における上記所定の温度とは、はんだシート７は溶融するが、突起部材８は溶融しない温度である。この温度で加熱されることにより、はんだシート７のみが溶融する。すると、錘１０の作用によって半導体素子５及び突起部材８が、絶縁基板２の表面側導電層３側に向かって沈下し、突起部材８が表面側導電層３に当接する。そして、その後、溶融したはんだは、冷却され、固化する。つまり、はんだによって絶縁基板２の表面側導電層３と半導体素子５の裏面５ａとが接合され、接合部６（図１参照）が形成される。また、接合部６内に突起部材８が配設されることにより、接合部６の厚みが部分的に突起部材８の高さ以下になることがない。   The predetermined temperature at the time of heating is a temperature at which the solder sheet 7 melts but the protruding member 8 does not melt. By heating at this temperature, only the solder sheet 7 is melted. Then, due to the action of the weight 10, the semiconductor element 5 and the protruding member 8 sink toward the surface-side conductive layer 3 side of the insulating substrate 2, and the protruding member 8 contacts the surface-side conductive layer 3. Thereafter, the melted solder is cooled and solidified. That is, the front surface side conductive layer 3 of the insulating substrate 2 and the back surface 5a of the semiconductor element 5 are bonded to each other by solder, thereby forming the bonding portion 6 (see FIG. 1). In addition, since the protruding member 8 is disposed in the bonding portion 6, the thickness of the bonding portion 6 does not partially become lower than the height of the protruding member 8.

以上のように、本実施形態の半導体基板１の製造方法は、はんだで構成されるはんだシート７に、絶縁基板２の表面側導電層３と半導体素子５の裏面５ａとの間隔ｄを規制する突起部材８を配設する配設工程（ステップＳＴ１）と、絶縁基板２、突起部材８が配設されたはんだシート７、及び半導体素子５を、その順番で積層する積層工程（ステップＳＴ２）と、積層されている絶縁基板２、はんだシート７及び半導体素子５を、還元ガス１２下において加熱してはんだシート７を溶融することによって、絶縁基板２と半導体素子５とを接合する接合工程（ステップＳＴ３）と、を含む。
これにより、以下の（１）乃至（６）として示す各効果が奏される。 As described above, in the method for manufacturing the semiconductor substrate 1 according to the present embodiment, the distance d between the surface-side conductive layer 3 of the insulating substrate 2 and the back surface 5a of the semiconductor element 5 is regulated on the solder sheet 7 made of solder. A disposing step (step ST1) for disposing the protruding member 8, and a laminating step (step ST2) for laminating the insulating substrate 2, the solder sheet 7 on which the protruding member 8 is disposed, and the semiconductor element 5 in that order. A bonding step (step for bonding the insulating substrate 2 and the semiconductor element 5 by heating the laminated insulating substrate 2, the solder sheet 7 and the semiconductor element 5 under the reducing gas 12 to melt the solder sheet 7. ST3).
Thereby, each effect shown as the following (1) thru / or (6) is produced.

（１）はんだシート７に突起部材８が配設されることにより、はんだシート７の表面７ａと半導体素子５の裏面５ａとの間に、この突起部材８の高さに相当する間隔ｄの隙間が形成される。そのため、この隙間に還元ガス１２が十分に供給され、接合面におけるはんだの濡れ性を向上することができ、はんだ接合の信頼性を向上することができる。また、半導体素子５が、絶縁基板２に対して傾いてはんだ接合されることを抑制することができ、接合部６（はんだ）の厚みを均一にすることができる。つまり、接合部６が部分的に薄くなることを抑制することができるため、はんだ厚みの不均一に基づく亀裂の発生及び進展を抑制することができ、放熱性の悪化（熱特性の信頼性の低下）を抑制することができる。従って、回路基板１の耐久信頼性及び熱特性を一定以上に確保することができる。   (1) Since the protruding member 8 is disposed on the solder sheet 7, a gap having a distance d corresponding to the height of the protruding member 8 is provided between the front surface 7 a of the solder sheet 7 and the back surface 5 a of the semiconductor element 5. Is formed. Therefore, the reducing gas 12 is sufficiently supplied to this gap, so that the wettability of the solder on the joint surface can be improved, and the reliability of the solder joint can be improved. Moreover, it can suppress that the semiconductor element 5 inclines with respect to the insulated substrate 2 and is soldered, and can make the thickness of the junction part 6 (solder) uniform. That is, since it can suppress that the junction part 6 becomes thin partially, generation | occurrence | production and progress of the crack based on nonuniformity of solder thickness can be suppressed, and heat dissipation deteriorates (reliability of thermal characteristics). Reduction) can be suppressed. Therefore, the durability reliability and thermal characteristics of the circuit board 1 can be ensured to a certain level or more.

（２）また、突起部材８は、アルミニウム製のボンディングワイヤからなる。アルミニウムは、汎用性のある金属素材であり、これを用いることにより、製造コストを低減することができる。また、アルミニウムは、はんだシート７の素材であるはんだよりも、融点が高く、かつ、はんだ濡れ性が低い金属素材である。そのため、はんだシート７を所定の温度で加熱することによって、はんだシート７のみを溶融させ、突起部材８を溶融したはんだ内に固体の状態で残すことができる。また、突起部材８は、はんだよりも、はんだ濡れ性が低いので、溶融したはんだは、突起部材８の周囲に容易に流動する。
従って、絶縁基板２の表面側導電層３と半導体素子５の裏面５ａとの間に、突起部材８の高さ（直径）に相当する間隔ｄが確実に設定され、接合部６（はんだ）の厚みを均一にすることができる。 (2) The protruding member 8 is made of an aluminum bonding wire. Aluminum is a versatile metal material, and the production cost can be reduced by using aluminum. Aluminum is a metal material having a higher melting point and lower solder wettability than the solder that is the material of the solder sheet 7. Therefore, by heating the solder sheet 7 at a predetermined temperature, it is possible to melt only the solder sheet 7 and leave the protruding member 8 in a solid state in the melted solder. Further, since the protruding member 8 has lower solder wettability than the solder, the molten solder easily flows around the protruding member 8.
Accordingly, a distance d corresponding to the height (diameter) of the protruding member 8 is reliably set between the front surface side conductive layer 3 of the insulating substrate 2 and the back surface 5a of the semiconductor element 5, and the bonding portion 6 (solder) is fixed. The thickness can be made uniform.

（３）また、突起部材８を、アルミニウム製のボンディングワイヤとすることで、ワイヤボンディングするための新たな装置は不要であり、既存の装置を利用することできる。また、ワイヤボンディングすることにより、突起部材８をはんだシート７に容易かつ迅速に配設することができる。特に、突起部材８を、予めはんだシート７にワイヤボンディングすることで、量産工程への自動供給が可能となる。   (3) Since the protruding member 8 is made of an aluminum bonding wire, a new device for wire bonding is unnecessary, and an existing device can be used. Moreover, the protruding member 8 can be easily and quickly disposed on the solder sheet 7 by wire bonding. In particular, the protruding member 8 can be automatically supplied to the mass production process by wire bonding to the solder sheet 7 in advance.

（４）また、はんだシート７は、平面視で矩形状に形成され、突起部材８は、はんだシート７における対向する２つの辺７ｃ，７ｄに沿って配設される。そのため、前記積層工程時において、はんだシート７の２つの突起部材８の上に半導体素子５を安定して載置することができると共に、前記接合工程において、はんだシート７が溶融した場合にも突起部材８によって半導体素子５を支持することができる。これにより、絶縁基板２に対する半導体素子５の傾きの発生を抑制することができ、はんだ（接合部６）の厚みを均一化することができる。従って、接合部６に亀裂（クラック）が発生することを抑制することができ、半導体基板１の耐久信頼性を向上することができる。   (4) Further, the solder sheet 7 is formed in a rectangular shape in plan view, and the protruding member 8 is disposed along two opposing sides 7 c and 7 d in the solder sheet 7. Therefore, the semiconductor element 5 can be stably placed on the two protruding members 8 of the solder sheet 7 during the stacking step, and the protrusion is also generated when the solder sheet 7 is melted during the bonding step. The semiconductor element 5 can be supported by the member 8. Thereby, generation | occurrence | production of the inclination of the semiconductor element 5 with respect to the insulated substrate 2 can be suppressed, and the thickness of solder (joining part 6) can be equalize | homogenized. Therefore, it is possible to suppress the occurrence of cracks in the joint 6 and improve the durability reliability of the semiconductor substrate 1.

（５）また、はんだシート７は、鉛フリーはんだからなる。そのため、半導体基板１において、鉛を含まない接合部６を構成することができ、環境に優しい半導体基板１を提供することができる。この鉛フリーはんだは、鉛系はんだや錫−鉛系はんだよりも硬いことが知られている。そのため、半導体基板１の接合部６（はんだ）の厚みが均一に形成されない場合には、半導体素子５とはんだの線膨張係数差により、はんだ厚みの薄い箇所に歪みが発生し、亀裂の進展が早まる虞がある。しかし、本実施形態においては、前述したように、接合部６の厚みを均一に形成することができるため、亀裂の進展が早まる虞がなく、鉛フリーはんだを用いることができる。   (5) The solder sheet 7 is made of lead-free solder. Therefore, in the semiconductor substrate 1, the junction part 6 which does not contain lead can be comprised, and the environmentally friendly semiconductor substrate 1 can be provided. This lead-free solder is known to be harder than lead-based solder or tin-lead solder. Therefore, when the thickness of the joining portion 6 (solder) of the semiconductor substrate 1 is not formed uniformly, distortion occurs in a portion where the solder thickness is thin due to the difference in linear expansion coefficient between the semiconductor element 5 and the solder, and the crack progresses. There is a risk of getting early. However, in the present embodiment, as described above, since the thickness of the joint portion 6 can be formed uniformly, there is no possibility that the progress of cracks is accelerated, and lead-free solder can be used.

（６）また、接合面におけるはんだ濡れ性を確保するために、従来は、はんだ材料を、シートよりも厚みのある円柱状に加工することが行われていた。そのため、金型使用回数が激減し、加工コストが大幅に増加していた。しかし、本実施形態においては、前述した理由により、シート状の鉛フリーはんだを用いても、はんだ濡れ性を容易に確保できるため、はんだ材料を円柱状に加工する必要がない。従って、製造コストを低減することができる。   (6) Moreover, in order to ensure the solder wettability in a joining surface, conventionally, processing a solder material into a columnar shape with a thickness thicker than a sheet | seat was performed. For this reason, the number of molds used has been drastically reduced, and the processing cost has been greatly increased. However, in the present embodiment, for the reasons described above, even if a sheet-like lead-free solder is used, solder wettability can be easily ensured, so that it is not necessary to process the solder material into a cylindrical shape. Therefore, the manufacturing cost can be reduced.

また、前記製造方法によって製造される半導体基板１は、表面側導電層３及び裏面側導電層４を有する絶縁基板２と、半導体素子５と、絶縁基板２の表面側導電層３と半導体素子５の裏面５ａとをはんだにより接合している接合部６と、を備え、接合部６には、絶縁基板２の表面側導電層３と半導体素子５の裏面５ａとの間隔ｄを規制する突起部材８が設けられている。   Further, the semiconductor substrate 1 manufactured by the manufacturing method includes an insulating substrate 2 having a front surface side conductive layer 3 and a back surface side conductive layer 4, a semiconductor element 5, a front surface side conductive layer 3 of the insulating substrate 2, and the semiconductor element 5. A projecting member that regulates the distance d between the surface-side conductive layer 3 of the insulating substrate 2 and the back surface 5a of the semiconductor element 5. 8 is provided.

そのため、突起部材８を設けたことによって、半導体素子５が絶縁基板２に対して傾いてはんだ接合されることを抑制することができ、接合部６（はんだ）の厚みを均一にすることができる。従って、はんだ厚みの不均一に基づく亀裂の発生及び進展を抑制することができ、回路基板１の耐久信頼性及び熱特性を一定以上に確保することができる。   Therefore, by providing the protruding member 8, it is possible to suppress the semiconductor element 5 from being tilted and soldered to the insulating substrate 2, and to make the thickness of the joint 6 (solder) uniform. . Therefore, it is possible to suppress the occurrence and development of cracks based on the unevenness of the solder thickness, and to ensure the durability reliability and thermal characteristics of the circuit board 1 to a certain level or more.

以上、本発明の一実施形態について説明したが、本発明は、前述した実施形態に制限されるものではなく、適宜変更が可能である。
例えば、前記実施形態においては、突起部材８は、はんだシート７における対向する２つの辺７ｃ，７ｄに沿って配設されるものとして説明したが、これに制限されない。還元ガス１２の流路を確保することができ、かつ、半導体素子５を安定して載置することができれば、突起部材８は、１つ又は３つ以上配設されてもよく、その形状や配設位置も任意である。 As mentioned above, although one Embodiment of this invention was described, this invention is not restrict | limited to embodiment mentioned above, It can change suitably.
For example, in the above-described embodiment, the protruding member 8 has been described as being disposed along the two opposing sides 7c and 7d of the solder sheet 7, but is not limited thereto. If the flow path of the reducing gas 12 can be secured and the semiconductor element 5 can be stably placed, one or three or more projecting members 8 may be disposed, The arrangement position is also arbitrary.

また、前記実施形態においては、回路素子として、パワーモジュールに用いられる半導体素子５を例にして説明したが、これに制限されない。例えば、回路素子は、半導体素子でなく、その他の電気部品であってもよい。   Moreover, in the said embodiment, although the semiconductor element 5 used for a power module was demonstrated as an example as a circuit element, it is not restrict | limited to this. For example, the circuit element may be other electrical components instead of the semiconductor element.

また、前記実施形態においては、はんだシート７は、鉛を含有しない鉛フリーはんだからなるものとして説明したが、これに制限されない。例えば、はんだシート７は、鉛はんだ、錫−鉛共晶はんだ等からなるものでもよい。また、このようなはんだは、半導体素子５の接合用に用いられるもののほか、放熱性を高めるためのアルミニウムや銅等の金属製放熱板に、ニッケルメッキ等の表面処理を施したものとの接合に用いることも可能である。   Moreover, in the said embodiment, although the solder sheet 7 demonstrated as what consists of lead-free solder which does not contain lead, it is not restrict | limited to this. For example, the solder sheet 7 may be made of lead solder, tin-lead eutectic solder, or the like. In addition to the solder used for joining the semiconductor element 5, the solder is joined to a heat sink made of metal such as aluminum or copper and subjected to a surface treatment such as nickel plating. It can also be used.

また、前記実施形態においては、接合工程において、還元ガス１２として水素を用いるものとして説明したが、これに制限されない。例えば、還元ガス１２として、蟻酸を用いてもよい。   Moreover, in the said embodiment, although demonstrated as what uses hydrogen as the reducing gas 12 in a joining process, it is not restrict | limited to this. For example, formic acid may be used as the reducing gas 12.

また、前記実施形態においては、自動車等における電源装置のパワーモジュールに用いられる半導体基板１を例にして説明したが、これに制限されない。例えば、はんだ接合される回路基板であれば、どのような基板であってもよく、また回路基板以外の電気部品であってもよい。   In the above-described embodiment, the semiconductor substrate 1 used in the power module of the power supply device in an automobile or the like has been described as an example. However, the present invention is not limited to this. For example, any circuit board may be used as long as it is a solder-bonded circuit board, and electrical parts other than the circuit board may be used.

１ 半導体基板（回路基板）
２ 絶縁基板
３ 表面側導電層（導電層）
４ 裏面側導電層（導電層）
５ 半導体素子（回路素子）
６ 接合部
７ はんだシート
７ｃ，７ｄ 辺
８ 突起部材（規制部材）
１２ 還元ガス（還元雰囲気）
ｄ 間隔 1 Semiconductor substrate (circuit board)
2 Insulating substrate 3 Surface side conductive layer (conductive layer)
4 Back side conductive layer (conductive layer)
5 Semiconductor elements (circuit elements)
6 Joint 7 Solder sheet 7c, 7d Side 8 Projection member (regulation member)
12 Reducing gas (reducing atmosphere)
d interval

Claims (7)

導電層を有する絶縁基板と回路素子とを備え、前記絶縁基板の前記導電層と前記回路素子とがはんだにより接合される回路基板の製造方法であって、
前記はんだで構成されるはんだシートに、前記絶縁基板の前記導電層と前記回路素子との間隔を規制する規制部材を配設する配設工程と、
前記絶縁基板、前記規制部材が配設された前記はんだシート、及び前記回路素子を、その順番で積層する積層工程と、
積層されている前記絶縁基板、前記はんだシート及び前記回路素子を、還元雰囲気下において加熱して前記はんだシートを溶融することによって、前記絶縁基板と前記回路素子とを接合する接合工程と、
を含む回路基板の製造方法。 A method of manufacturing a circuit board comprising an insulating substrate having a conductive layer and a circuit element, wherein the conductive layer of the insulating substrate and the circuit element are joined by solder,
A disposing step of disposing a restricting member for restricting a distance between the conductive layer of the insulating substrate and the circuit element on the solder sheet composed of the solder;
A laminating step of laminating the insulating substrate, the solder sheet on which the regulating member is disposed, and the circuit element;
Bonding the insulating substrate and the circuit element by heating the laminated insulating substrate, the solder sheet and the circuit element in a reducing atmosphere to melt the solder sheet;
A method of manufacturing a circuit board including: 前記規制部材は、前記はんだよりも、融点が高く、かつ、はんだ濡れ性が低い金属素材からなる請求項１に記載の回路基板の製造方法。   The method of manufacturing a circuit board according to claim 1, wherein the regulating member is made of a metal material having a higher melting point and lower solder wettability than the solder. 前記規制部材は、アルミニウムを主成分とする金属素材からなる請求項２に記載の回路基板の製造方法。   The circuit board manufacturing method according to claim 2, wherein the regulating member is made of a metal material mainly composed of aluminum. 前記規制部材は、ボンディングワイヤからなる請求項３に記載の回路基板の製造方法。   The circuit board manufacturing method according to claim 3, wherein the regulating member is made of a bonding wire. 前記はんだシートは、平面視で矩形状に形成され、
前記規制部材は、前記はんだシートにおける対向する二辺に沿って配設される請求項１から４のいずれか一つに記載の回路基板の製造方法。 The solder sheet is formed in a rectangular shape in plan view,
The circuit board manufacturing method according to claim 1, wherein the regulating member is disposed along two opposing sides of the solder sheet. 前記はんだシートは、鉛フリーはんだからなる請求項１から５のいずれか一つに記載の回路基板の製造方法。   The circuit board manufacturing method according to claim 1, wherein the solder sheet is made of lead-free solder. 導電層を有する絶縁基板と、
回路素子と、
前記絶縁基板の前記導電層と前記回路素子とをはんだにより接合している接合部と、
を備え、
前記接合部には、前記絶縁基板の前記導電層と前記回路素子との間隔を規制する規制部材が設けられている回路基板。 An insulating substrate having a conductive layer;
Circuit elements;
A joint that joins the conductive layer of the insulating substrate and the circuit element with solder;
With
A circuit board provided with a restricting member for restricting a distance between the conductive layer of the insulating substrate and the circuit element at the joint.
JP2010099442A 2010-04-23 2010-04-23 Manufacturing method of circuit board and circuit board Pending JP2011228604A (en)

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DE102016219565A1 (en) * 2016-10-07 2018-04-12 Continental Automotive Gmbh Power electronics circuit
JP6885522B1 (en) * 2020-09-03 2021-06-16 三菱電機株式会社 Semiconductor device, power conversion device and manufacturing method of semiconductor device
US11677062B2 (en) 2018-12-25 2023-06-13 Nichia Corporation Method of manufacturing light source device having a bonding layer with bumps and a bonding member

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JPH11186331A (en) * 1997-12-19 1999-07-09 Mitsubishi Electric Corp Semiconductor device and its manufacture
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JPH03218030A (en) * 1990-01-23 1991-09-25 Hitachi Ltd Semiconductor integrated circuit device and preform bonding material used in the same
JPH05343446A (en) * 1992-06-11 1993-12-24 Toshiba Corp Manufacture of semiconductor device
JPH11186331A (en) * 1997-12-19 1999-07-09 Mitsubishi Electric Corp Semiconductor device and its manufacture
JP2001168252A (en) * 1999-12-07 2001-06-22 Shibafu Engineering Kk Semiconductor device and manufacturing method thereof
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JP2008227189A (en) * 2007-03-13 2008-09-25 Toyota Motor Corp Solder joining method and apparatus

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DE102016219565A1 (en) * 2016-10-07 2018-04-12 Continental Automotive Gmbh Power electronics circuit
US11677062B2 (en) 2018-12-25 2023-06-13 Nichia Corporation Method of manufacturing light source device having a bonding layer with bumps and a bonding member
JP6885522B1 (en) * 2020-09-03 2021-06-16 三菱電機株式会社 Semiconductor device, power conversion device and manufacturing method of semiconductor device
WO2022049697A1 (en) * 2020-09-03 2022-03-10 三菱電機株式会社 Semiconductor device, power conversion device, and method for manufacturing semiconductor device

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