WO2022049697A1 - Semiconductor device, power conversion device, and method for manufacturing semiconductor device - Google Patents

Semiconductor device, power conversion device, and method for manufacturing semiconductor device Download PDF

Info

Publication number
WO2022049697A1
WO2022049697A1 PCT/JP2020/033445 JP2020033445W WO2022049697A1 WO 2022049697 A1 WO2022049697 A1 WO 2022049697A1 JP 2020033445 W JP2020033445 W JP 2020033445W WO 2022049697 A1 WO2022049697 A1 WO 2022049697A1
Authority
WO
WIPO (PCT)
Prior art keywords
holding portion
semiconductor device
insulating substrate
semiconductor element
joint
Prior art date
Application number
PCT/JP2020/033445
Other languages
French (fr)
Japanese (ja)
Inventor
隆一郎 花田
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to PCT/JP2020/033445 priority Critical patent/WO2022049697A1/en
Priority to JP2020570068A priority patent/JP6885522B1/en
Publication of WO2022049697A1 publication Critical patent/WO2022049697A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/40—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/83138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8314—Guiding structures outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Definitions

  • the present disclosure relates to a semiconductor device joined by using a holding portion, a method for manufacturing the semiconductor device, and a power conversion device.
  • the semiconductor device includes a semiconductor element, an insulating substrate, and a base plate, and the semiconductor element and the insulating substrate, and the insulating substrate and the base plate are joined via a joining member.
  • the member arranged at the upper part of the joining member may be joined in an inclined state with respect to the member arranged at the lower part of the joining member.
  • the thickness of the joined members becomes uneven between the upper and lower members, which causes a poor joining. Therefore, it is required to reduce the inclination of the upper member of the joining member and the lower member of the joining member to be small, and to reduce the joining failure between the members arranged above and below the joining member.
  • Patent Document 1 a semiconductor device provided with an insulating resin spacer on the outer peripheral portion of the solder joining material is disclosed. Further, there is disclosed a semiconductor device in which a plurality of conductive solid spacers that regulate the distance between a base material and an electronic component and do not change in shape by heating are embedded in the coating agent layer (for example, Patent Document 2). Further, a semiconductor device in which a bonding wire is arranged on an outer peripheral portion of a semiconductor element is disclosed (for example, Patent Document 3).
  • the spacer is an insulating resin, the wettability with the solder is not so high, and it may be a starting point of cracks.
  • the semiconductor device described in Patent Document 2 depending on the method of arranging the solid spacers, when the solder is melted, the solder does not spread wet and spread, or bubbles are prevented from coming out, so that a bonding defect may occur. there were.
  • the bonding position accuracy of the semiconductor element can be improved by the bonding wire, but there is no function of adjusting the wetting spread of the solder (joint portion), and the solder bonding is defective. May occur. For this reason, the conventional semiconductor device has a problem that the improvement of the bonding defect is not sufficient and the reliability of the semiconductor device is deteriorated.
  • the present disclosure has been made to solve the above-mentioned problems, and improves reliability by improving the bonding failure between the members arranged above and below the bonding portion in the semiconductor device by using the holding portion.
  • the purpose is to obtain a semiconductor device that has been made.
  • the semiconductor device includes a semiconductor element having an electrode on the surface, an insulating substrate having metal layers on the upper surface and the lower surface, and the semiconductor element bonded to the metal layer on the upper surface side at the first junction.
  • the insulating substrate is embedded in at least one of the base plate bonded at the second junction on the upper surface and the first junction and the second junction, and embedded in the first junction, the corner of the semiconductor element.
  • Holding portions that are arranged diagonally inside and outside, and when embedded in the second joint, are arranged diagonally inside and outside the corners of the metal layer on the lower surface side of the insulating substrate. It is a semiconductor device equipped with.
  • the holding portions are provided inside and outside the corners of the joint portion, it is possible to improve the bondability between the members arranged above and below the joint portion, and improve the reliability of the semiconductor device. Can be made to.
  • FIG. It is sectional drawing which shows the joint part of the semiconductor device in Embodiment 1.
  • FIG. It is a planar structure schematic diagram which shows the other joint part of the semiconductor device in Embodiment 1.
  • FIG. It is sectional drawing which shows the other junction part of the semiconductor device in Embodiment 1.
  • FIG. It is sectional drawing which shows the other junction part of the semiconductor device in Embodiment 1.
  • FIG. It is a planar structure schematic diagram which shows the other joint part of the semiconductor device in Embodiment 1.
  • FIG. It is a planar structure schematic diagram which shows the other holding part of the semiconductor device in Embodiment 1.
  • FIG. It is sectional drawing which shows the other semiconductor device in Embodiment 1.
  • FIG. It is a planar structure schematic diagram which shows the semiconductor device in Embodiment 2.
  • FIG. 1 is a schematic plan view showing a semiconductor device according to the first embodiment.
  • FIG. 2 is a schematic cross-sectional structure diagram showing the semiconductor device according to the first embodiment.
  • FIG. 3 is another schematic cross-sectional structure showing the semiconductor device according to the first embodiment.
  • FIG. 4 is a schematic plan view showing a holding portion of the semiconductor device according to the first embodiment.
  • FIG. 2 is a schematic cross-sectional structure of the alternate long and short dash line AA of FIG.
  • FIG. 3 is a schematic cross-sectional structure of the alternate long and short dash line BB of FIG.
  • FIG. 4 is a schematic plan view of the arrangement of the first holding portion 6 as viewed from the upper surface side through the first joining portion 8.
  • the semiconductor device 100 includes a base plate 1, an insulating substrate 2, a first joining portion 8 which is a joining portion, a second joining portion 3 which is a joining portion, and a first holding portion 6 which is a holding portion. , A semiconductor element 7, a bonding wire 9 which is a wiring portion, a sealing portion 10, and an electrode terminal 12.
  • the upper surface of the base plate 1 and the lower surface of the insulating substrate 2 are joined by using the second joining portion 3.
  • the upper surface of the insulating substrate 2 and the back surface (lower surface) of the semiconductor element 7 are joined by using the first joining portion 8.
  • the first joining portion 8 that joins the back surface of the semiconductor element 7 and the upper surface of the insulating substrate 2, the first holding portions 6 arranged inside and outside facing the corners of the semiconductor element 7 in the diagonal direction are embedded.
  • the insulating substrate 2 and the semiconductor element 7 bonded to the upper surface of the insulating substrate 2 are sealed in the sealing portion 10.
  • the sealing portion 10 is indicated by a dotted line so that the positional relationship of the members sealed in the sealing portion 10 can be understood.
  • the outermost circumference of the semiconductor device 100 is the peripheral edge of the base plate 1.
  • the sealing portion 10 is arranged inside the peripheral portion of the base plate 1.
  • the insulating layer 22 of the insulating substrate 2 is arranged inside the outer edge of the sealing portion 10.
  • the metal layer 21 on the upper surface side of the insulating substrate 2 is arranged inside the outer edge of the insulating layer 22 of the insulating substrate 2.
  • a semiconductor element 7 having an electrode 13 formed on its surface is arranged inside the outer edge of the metal layer 21 on the upper surface side of the insulating substrate 2.
  • the first joint portion 8 is arranged so as to protrude from the corner portion.
  • the electrode terminal 12 is arranged so as to straddle the insulating substrate 2 and protrudes (exposed) from the sealing portion 10.
  • FIG. 2 is a schematic cross-sectional structure of the semiconductor element 7 in the facing direction.
  • the upper surface of the base plate 1 and the lower surface of the metal layer 23 on the lower surface side of the insulating substrate 2 are joined by using the second joining portion 3.
  • the upper surface of the metal layer 21 on the upper surface side of the insulating substrate 2 and the back surface of the semiconductor element 7 are bonded by using the first bonding portion 8.
  • the bonding wire 9 electrically connects the electrode 13 on the surface (upper surface) of the semiconductor element 7 and the electrode terminal 12 (right side). Further, the bonding wire 9 electrically connects a predetermined position of the metal layer 21 on the upper surface side of the insulating substrate 2 and the electrode terminal 12 (left side).
  • the sealing portion 10 is in contact with the upper surface of the base plate 1 which is not bonded (exposed) to the metal layer 23 on the lower surface side of the insulating substrate 2, and the semiconductor element 7 is bonded to the insulating substrate 2 and the upper surface of the insulating substrate 2. And is sealed.
  • the electrode terminal 12 is arranged on the upper part of the insulating substrate 2, one end side being arranged in the sealing portion 10, and the other end being exposed (protruding) from the side surface of the sealing portion 10.
  • FIG. 3 is a schematic cross-sectional structure diagram of the semiconductor element 7 in the diagonal direction.
  • a first holding portion 6 is arranged at a corner portion of the semiconductor element 7 in a diagonal direction (toward).
  • the holding portion 6 embedded in the first joining portion 8 is the first holding portion 6.
  • the first holding portion 6 has a first internal holding portion 61 arranged inside the outer peripheral portion of the semiconductor element 7, and a first external holding portion 62 arranged outside the outer peripheral portion of the semiconductor element 7. is doing.
  • the first holding portion 6 is arranged from the inside to the outside of the corner portion of the semiconductor element 7, and is embedded in the first joining portion 8.
  • FIG. 4 is a top view of the inside of the first joint portion 8 through the inside.
  • the first joint portion 8 is arranged on the upper surface of the metal layer 21 on the upper surface side of the insulating substrate 2.
  • the first joint portion 8 has a fillet portion 81 of the first joint portion 8 that is joined to the back surface of the semiconductor element 7 and protrudes (protrudes) from the outer shape of the semiconductor element 7.
  • the first holding portion 6 is embedded in the first junction 8 between the inside and the outside of the projection surface of the semiconductor element 7. Are arranged.
  • the first internal holding portion 61 is arranged inside the projection surface of the semiconductor element 7, and the first external holding portion 62 is arranged in the fillet portion 81 of the first joining portion 8. ing.
  • the corner portion of the first joint portion 8 is 0 of the length (a or b) of each side from the corner apex (intersection of the sides) of the first joint portion 8 as a region. It means up to a range of .25 times (1/4), and the first holding portion 6 may be arranged within this range.
  • One end of the first internal holding portion 61 is arranged inside the corner portion of the semiconductor element 7, and the other end of the first internal holding portion 61 is a corner portion of the semiconductor element 7 rather than one end of the first internal holding portion 61. Placed on the side.
  • the base plate 1 has a plate shape and is a bottom surface portion (bottom plate) of the semiconductor device 100.
  • the base plate 1 functions as a heat radiating member that dissipates heat generated inside the semiconductor device 100 to the outside of the semiconductor device 100.
  • the upper surface of the base plate 1 is bonded (using) to the lower surface of the metal layer 23 on the lower surface side of the insulating substrate 2 via the second joint portion 3.
  • a copper alloy, an aluminum alloy, or the like can be used as the material of the base plate 1, a copper alloy, an aluminum alloy, or the like can be used.
  • the lower surface of the sealing portion 10 is in contact with the outside of the joint region of the base plate 1 with the second joint portion 3.
  • the insulating substrate 2 has an upper surface layer, an intermediate layer, and a lower surface layer.
  • the metal layer 23 on the lower surface side of the insulating substrate 2 faces the upper surface of the base plate 1.
  • the insulating substrate 2 has an insulating layer 22 as an intermediate layer, a metal layer 21 on the upper surface side of the insulating layer 22 as an upper surface layer, and a metal layer 23 on the lower surface side of the insulating layer 22 as a lower surface layer.
  • the metal layer 23 on the lower surface side of the insulating layer 22 is joined to the upper surface of the base plate 1 by the second joint portion 3.
  • the insulating substrate 2 has a plate shape, and when the plate-shaped insulating substrate 2 is viewed from the plane (upper surface) direction, the size of the metal layer 21 on the upper surface side of the insulating layer 22 is smaller than the size of the insulating layer 22. It has become. The size of the metal layer 23 on the lower surface side of the insulating layer 22 is smaller than the size of the insulating layer 22. The end portion of the insulating layer 22 projects outward from the end portion of the metal layer 21 on the upper surface side of the insulating layer 22 and the metal layer 23 on the lower surface side of the insulating layer 22.
  • the metal layer 21 on the upper surface side of the insulating layer 22 suppresses creeping discharge between the metal layer 23 on the lower surface side of the insulating layer 22 and the base plate 1 with the insulating layer 22 interposed therebetween (securing the creeping distance). ).
  • the metal layer 21 on the upper surface side of the insulating layer 22 may be divided into a plurality of pieces according to the purpose to form a circuit pattern.
  • a semiconductor element 7 is bonded to the upper surface of the metal layer 21 on the upper surface side of the insulating substrate 2 by a first bonding portion 8.
  • the upper surface side of the insulating substrate 2 is synonymous with the upper surface side of the insulating layer 22, and the lower surface side of the insulating substrate 2 is synonymous with the lower surface side of the insulating layer 22.
  • the second joint portion 3 is a joining member for joining the upper surface of the base plate 1 and the lower surface of the metal layer 23 on the lower surface side of the insulating substrate 2. Solder is used as the material of the second joint portion 3, and sintered silver, sintered copper, or the like may be used if necessary.
  • the insulating substrate 2 is joined to the central region of the base plate 1.
  • the first bonding portion 8 is a bonding material for bonding the upper surface of the metal layer 21 on the upper surface side of the insulating substrate 2 and the back surface of the semiconductor element 7.
  • solder, sintered silver, sintered copper, or the like can be used as in the case of the second joint portion 3.
  • the wiring portion 9 electrically connects the predetermined position of the metal layer 21 on the upper surface side of the insulating substrate 2 and the electrode terminal 12. Further, the wiring portion 9 electrically joins the electrode 13 on the surface of the semiconductor element 7 and the electrode terminal 12. Further, when a plurality of semiconductor elements 7 are used, the plurality of semiconductor elements 7 are electrically connected to each other.
  • an aluminum alloy wire, a copper alloy wire, a gold wire, a copper alloy lead, an aluminum alloy ribbon, a copper alloy ribbon, or the like can be used. Wires, leads, ribbons, etc. plated with nickel, gold, silver, tin, etc. on the surface alone may be used.
  • the electrode 13 is arranged on the surface of the semiconductor element 7.
  • the semiconductor element 7 is bonded to the upper surface of the metal layer 21 on the upper surface side of the insulating substrate 2 via a first bonding portion 8 which is a bonding portion.
  • a power semiconductor element such as a MOSFET (Metal Oxide Semiconductor Field Transistor) or an IGBT (Insulated Gate Bipolar Transistor) can be used.
  • silicon Si: Silicon
  • SiC Silicon Cabide
  • the first holding portion 6 is embedded in the first joint portion 8 and installed inside and outside the corner portion of the first joint portion 8, in other words, is embedded in the first joint portion 8 and is a semiconductor device. It is installed on the lower surface side of the semiconductor element 7 inside and outside the corner portion of the semiconductor element 7.
  • the first holding portion 6 is installed on the lower surface side of the semiconductor element 7 inside and outside the corner portion of the semiconductor element 7, but may be integrally formed. Further, the first holding portion 6 is installed on the lower surface side of the semiconductor element 7 on the inner side and the outer side of the corner portion of the semiconductor element 7, but even if the inner side and the outer side of the semiconductor element 7 are formed separately. good.
  • the first holding portion 6 supports the semiconductor element 7 from the lower surface side of the semiconductor element 7.
  • the first holding portion 6 arranged in the first joint portion 8 reduces the deviation of the thickness of the first joint portion 8 from the design value. Since the first holding portion 6 reduces the variation in the thickness of the first joining portion 8, the inclination of the semiconductor element 7 is reduced. Since the first holding portion 6 reduces the variation in the thickness of the first joint portion 8, the heat dissipation from the semiconductor element 7 is improved.
  • the first holding portion 6 reduces the deviation of the bonding position of the semiconductor element 7.
  • the first holding portion 6 is for guiding the first joining portion 8 so that the first joining portion 8 is surely joined (wet and spreads) to the corner portion on the back surface of the semiconductor element 7.
  • the first holding portion 6 is arranged inside and outside the first joining portion 8 (arranged inside and outside the outer shape (outer edge) of the semiconductor element 7).
  • the upper surface of the first bonding portion 8 is in contact (bonding) with the back surface of the semiconductor element 7.
  • the lower surface of the first bonding portion 8 is in contact (bonding) with the metal layer 21 on the upper surface side of the insulating substrate 2.
  • the height of the first internal holding portion 61 which is a portion existing inside the outer shape of the semiconductor element 7, is higher than the height of the first external holding portion 62, which is a portion existing outside the outer shape of the semiconductor element 7. Low. As a result, it is possible to reduce the deviation of the bonding position of the semiconductor element 7 when the semiconductor element 7 and the insulating substrate 2 are bonded.
  • the shape of the first holding portion 6 a wire shape using a bonding wire and a block shape using a metal member can be considered. As will be described later, as shown in FIGS. 5 to 8, if the wire shape is used, the wiring portion 9 can be joined (formed) by the same device as the device for joining the semiconductor element 7.
  • a substance having good wettability with the first joint portion 8 for example, an aluminum alloy, a copper alloy, gold, or tin can be used.
  • the surface of the first holding portion 6 may be made of a material having good wettability with the first joining portion 8 or plated. With such a configuration, the first holding portion 6 forms an alloy layer at the contact interface with the first joining portion 8.
  • the installation location of the first holding portion 6 is the metal layer 21 on the upper surface side of the insulating substrate 2 and the semiconductor element. It is arranged so that the insulation distance from 7 is maintained.
  • the highest portion of the first holding portion 6 is set to be lower than the position of the surface of the semiconductor element 7.
  • FIG. 5 is a schematic cross-sectional structure showing a joint portion of the semiconductor device according to the first embodiment.
  • FIG. 6 is a schematic cross-sectional structure diagram showing a joint portion of the semiconductor device according to the first embodiment.
  • FIG. 7 is a schematic cross-sectional structure showing another joint portion of the semiconductor device according to the first embodiment.
  • FIG. 8 is a schematic cross-sectional structure showing another joint portion of the semiconductor device according to the first embodiment.
  • FIG. 9 is a schematic plan view showing another joint portion of the semiconductor device according to the first embodiment.
  • FIG. 10 is a schematic cross-sectional structure showing another joint portion of the semiconductor device according to the first embodiment.
  • FIG. 11 is a schematic cross-sectional structure showing another joint portion of the semiconductor device according to the first embodiment.
  • FIG. 12 is a schematic plan view showing another joint portion of the semiconductor device according to the first embodiment.
  • FIG. 7, and FIG. 9 are cross-sectional structural views of the first joint portion 8 before joining.
  • FIG. 8 and FIG. 10 are cross-sectional structural views of the first joint portion 8 after joining.
  • FIG. 6, FIG. 7, and FIG. 8 show the case where the bonding wire is used as the first holding portion 6.
  • the first internal holding portion 61 forms a flat portion so as to be in contact with the upper surface of the metal layer 21 on the upper surface side of the insulating substrate 2 up to the region corresponding to the outer periphery of the semiconductor element 7.
  • the first external holding portion 62 is formed and arranged by forming a loop portion in a region outside the outer periphery of the semiconductor element 7 and bonding it to the upper surface of the metal layer 21 (see FIG. 5).
  • the first joint portion 8 and the semiconductor element 7 are arranged on the flat portion of the first internal holding portion 61 so as to be overlapped with each other.
  • the upper surface of the metal layer 21 and the lower surface of the semiconductor element 7 are joined (see FIG. 6).
  • the height of the loop portion of the first external holding portion 62 is the height at which the semiconductor element 7 is in contact with the outer peripheral side surface of the semiconductor element 7 after being joined by the first joining portion 8.
  • the thickness of the first joint portion 8 can be adjusted and controlled by the diameter (height) of the first internal holding portion 61. Further, by arranging the first holding portion 6 at the corner portion of the semiconductor element 7 from the inside to the outside of the outer shape of the semiconductor element 7, the first joint portion 8 is formed when the first joint portion 8 is formed. Spreads wet and spreads from the inside to the outside of the outer shape of the semiconductor element 7 along the first holding portion 6, so that a fillet portion of the first joining portion 8 is formed around the first outer holding portion 62 (see FIG. 6). .. Since the fillet portion 81 is formed on the side surface of the corner portion of the semiconductor element 7, stress relaxation at the corner portion of the semiconductor element 7 can be performed, and the reliability of the semiconductor device 100 can be improved.
  • the first internal holding portion 61 forms a loop portion so as to be in contact with the upper surface of the metal layer 21 on the upper surface side of the insulating substrate 2 up to the region corresponding to the outer periphery of the semiconductor element 7.
  • the first external holding portion 62 is formed by forming a loop portion in a region on the upper surface of the metal layer 21 on the upper surface side outside the outer periphery of the semiconductor element 7 and bonding to the upper surface of the metal layer 21. ing.
  • the shape of the first internal holding portion 61 is different from that of the first holding portion 6 shown in FIGS. 5 and 6.
  • the thickness of the first joint portion 8 is desired to be thicker than the diameter of the first internal holding portion 61, or when the first internal holding portion 61 is formed by using a bonding wire having a small diameter. Even in such a configuration, the thickness of the first holding portion 6 can be specified, and the semiconductor element 7 can be supported and positioned as in the cases of FIGS. 5 and 6.
  • FIGS. 9 and 10 show a case where a block-shaped member is used as the first holding portion 6.
  • the first internal holding portion 61 is formed and arranged at the corner of the outer shape of the semiconductor element 7, and the first The thickness of the holding portion 6 can be specified, and the semiconductor element 7 can be supported and positioned.
  • the first holding portion 6 has the shape shown in FIGS. 6 and 8, but as shown in FIGS. 11 and 12, the first external holding portion 62 is used. Even in a shape in which a part of the loop portion is exposed, the thickness of the first holding portion 6 can be specified, and the semiconductor element 7 can be supported and positioned in the same manner.
  • the first internal holding portion 61 and the first external holding portion 62 are continuously formed from the inside to the outside of the corner portion of the semiconductor element 7. There is. It should be noted that the same effect can be obtained regardless of whether the first internal holding portion 61 and the first external holding portion 62 are not continuous and are arranged as separate bodies or continuously and integrally. Obtainable.
  • FIG. 13 is a schematic plan view showing another holding portion of the semiconductor device according to the first embodiment.
  • a plurality of numbers of the first holding portions 6 at the corner portions of the semiconductor element 7 are arranged.
  • the corner vertices of the semiconductor element 7 are sandwiched between the plurality of first holding portions 6, so that one first holding portion 6 is sandwiched between the corner portions.
  • the semiconductor element 7 can be stably supported.
  • the fillet portion 81 of the first joint portion 8 can secure a sufficient region for stress relaxation.
  • the corner portion of the first joint portion 8 is a region from the corner apex (intersection point of the sides) of the first joint portion 8 to each side. It means up to a range of 0.25 times (1/4) of the length (a or b) of, and the first holding portion 6 may be arranged within this range.
  • One end of the first internal holding portion 61 is arranged inside the corner portion of the semiconductor element 7, and the other end of the first internal holding portion 61 is a corner portion of the semiconductor element 7 rather than one end of the first internal holding portion 61. Placed on the side.
  • the base plate 1 to be the bottom surface of the semiconductor device 100 is prepared (base plate preparation process).
  • semiconductor element preparation step a semiconductor element 7 having an electrode 13 on the surface is prepared (semiconductor element preparation step).
  • an insulating substrate 2 having a metal layer 21 on the upper surface and a metal layer 23 on the lower surface is prepared (insulation substrate preparation step).
  • the insulating layer 22 is joined to the metal layer 21 on the upper surface side and the metal layer 23 on the lower surface side by brazing or the like. Since an electric circuit is formed on the metal layer 21 on the upper surface side, the pattern shape is often different. In such a case, by adjusting the size and thickness of the metal layer 21 on the upper surface side and the metal layer 23 on the lower surface side, it is possible to suppress the generation of thermal stress between the upper and lower (front and back) surfaces of the insulating layer 22. You may do it.
  • the insulating substrate 2 is bonded to the upper surface of the base plate 1 at the second bonding portion 3 (insulating substrate bonding process).
  • the first holding portion 6 is installed on the upper surface of the metal layer 21 on the upper surface side of the insulating substrate 2 (holding portion installation process).
  • the first holding portion 6 is a wire, a ribbon, or a lead, it is joined to the upper surface of the metal layer 21 by, for example, an ultrasonic joining method.
  • the semiconductor element 7 since the semiconductor element 7 has a positioning function as the role of the first holding portion 6, the semiconductor element 7 is arranged at a position where the semiconductor element 7 is planned to be arranged.
  • the semiconductor element 7 is arranged diagonally inside and outside, and when the first holding portion 6 is embedded in the second joint portion 3, the diagonal portion of the corner portion of the metal layer 23 on the lower surface of the insulating substrate 2 is diagonal. It is arranged inside and outside in the direction (holding part arrangement process).
  • the semiconductor element 7 and the metal layer 21 on the upper surface side of the insulating substrate 2 are electrically connected using the wiring portion 9 (wiring portion forming step).
  • the wiring portion 9 is a bonding wire, ribbon, or lead, it can be bonded by an ultrasonic bonding method.
  • the first holding portion 6 may also be bonded by the same device as the bonding device of the wiring portion 9.
  • the insulating substrate 2 and the semiconductor element 7 are sealed by the sealing portion 10 (sealing step).
  • the semiconductor device 100 shown in FIG. 1 can be manufactured by going through the above main manufacturing steps.
  • the holding portion 6 (second holding portion 6) is embedded in the second joint portion 3, the holding portion 6 (second holding portion 6) is installed on the upper surface of the base plate 1, and then the second joint portion 3 is installed.
  • the insulating substrate joining step of joining the base plate 1 and the insulating substrate 2 may be carried out using the above.
  • FIG. 14 is a schematic cross-sectional structure showing another semiconductor device according to the first embodiment.
  • the semiconductor device 101 is a base plate 1, an insulating substrate 2, a first joining portion 8 which is a joining portion, a second joining portion 3 which is a joining portion, a case portion 4, and a holding portion. It includes a first holding portion 6, a semiconductor element 7, a bonding wire 9 which is a wiring portion, a sealing portion 10, and an electrode terminal 12.
  • the semiconductor device 101 provided with the case portion 4 the same effect as that of the semiconductor device 100 can be obtained by providing the first holding portion 6.
  • the semiconductor device 101 can be manufactured by carrying out the case section arranging step of arranging the case section 4 on the upper surface of the base plate 1.
  • the first holding portion 6 is embedded in the first joining portion 8 and installed inside and outside the corner portion of the first joining portion 8. It is possible to reduce the deviation of the thickness of the first joint portion 8 from the design value, improve the joint defect, and improve the reliability of the semiconductor device.
  • first holding portion 6 is embedded in the first joining portion 8 and installed inside and outside the corner portion of the first joining portion 8, it is possible to reduce the deviation of the joining position of the semiconductor element 7. can.
  • the height of the portion where the thickness of the first joint portion 8 exists inside the first joint portion 8 of the first holding portion 6 is lower than the height of the portion existing outside the first joint portion 8. .. This makes it possible to reduce the deviation of the bonding position of the semiconductor element 7.
  • the first holding portion 6 is embedded in the first joining portion 8 and installed inside and outside the corner portion of the first joining portion 8, the first holding portion 6 is surely first up to the corner portion on the back surface of the semiconductor element 7. By joining (wetting and spreading) the joint portion 8, it is possible to improve the joint defect.
  • the first holding portion 6 is embedded in the first joining portion 8 and installed inside and outside the corner portion of the first joining portion 8, the first joining portion 8 gets wet with the first holding portion 6.
  • fillets are formed on the side surfaces of the corners of the semiconductor element 7, and the stress at the corners of the semiconductor element 7 can be reduced.
  • the first holding portion 6 is embedded in the first joint portion 8 and a material having good wettability with the first joint portion 8 is used, the joint state is improved and the heat dissipation from the semiconductor element 7 is improved. can.
  • the third holding portion 63 corresponds to the electrode 13 (the joint portion between the wiring portion 9 and the wiring portion 9) on the surface of the semiconductor element 7. It differs in that it is also arranged at the position on the back surface of the semiconductor element 7. In this way, since the third holding portion 63 is also arranged on the back surface of the semiconductor element 7 corresponding to the electrode 13 on the front surface of the semiconductor element 7, the heat generated by the semiconductor element 7 can be diffused through the third holding portion 63. can. As a result, the heat dissipation from the semiconductor element 7 can be improved, and the reliability of the semiconductor device 200 can be improved. Since other points are the same as those in the first embodiment, detailed description thereof will be omitted.
  • FIG. 15 is a schematic plan structure diagram showing the semiconductor device according to the second embodiment.
  • FIG. 16 is a schematic cross-sectional structure diagram showing the semiconductor device according to the second embodiment.
  • FIG. 17 is another schematic cross-sectional structure showing the semiconductor device according to the second embodiment.
  • FIG. 18 is a schematic plan view showing a holding portion of the semiconductor device according to the second embodiment.
  • FIG. 16 is a schematic cross-sectional structure of the alternate long and short dash line CC of FIG.
  • FIG. 17 is a schematic cross-sectional structure of the alternate long and short dash line DD of FIG.
  • FIG. 18 is a schematic plan view of the arrangement of the first holding portion 6 and the third holding portion 63 as viewed from above through the second joint portion 3.
  • the semiconductor device 200 includes a base plate 1, an insulating substrate 2, a first joining portion 8 which is a joining portion, a second joining portion 3 which is a joining portion, and a first holding portion 6 which is a holding portion.
  • a third holding portion 63 which is a holding portion, a semiconductor element 7, a bonding wire 9 which is a wiring portion, a sealing portion 10, and an electrode terminal 12 are provided.
  • the third holding portion 63 is shown by a dotted line.
  • the third holding portion 63 is arranged inside the outer shape of the electrode 13 on the surface of the semiconductor element 7.
  • the third holding portion 63 is arranged at a position on the back surface of the semiconductor element 7 corresponding to the arrangement position of the electrode 13 on the front surface of the semiconductor element 7. In particular, it is arranged at the corresponding position on the back surface of the semiconductor element 7 including the portion where the bonding wire 9 of the electrode 13 on the surface of the semiconductor element 7 is bonded.
  • the thickness (height) of the third holding portion 63 is the same as the thickness (height) of the first internal holding portion.
  • the semiconductor element 7 is supported (held) by the first internal holding portion 61 and the third holding portion 63.
  • one end of the first internal holding portion 61 is arranged inside the corner portion of the semiconductor element 7, and the other end of the first internal holding portion 61 is a semiconductor element rather than one end of the first internal holding portion 61. It is arranged on the corner side of 7.
  • the third holding portion 63 is arranged closer to the center of the semiconductor element 7 than one end of the first internal holding portion 61 arranged at the corners (four corners) of the semiconductor element 7.
  • the first holding portion 6 can be similarly applied to any of the embodiments used in the first embodiment.
  • the first holding portion 6 is embedded in the first joint portion 8 and installed inside and outside the corner portion of the first joint portion 8, so that the first It is possible to reduce the deviation of the thickness of the joint portion 8 from the design value, improve the joint defect, and improve the reliability of the semiconductor device.
  • first holding portion 6 is embedded in the first joining portion 8 and installed inside and outside the corner portion of the first joining portion 8, it is possible to reduce the deviation of the joining position of the semiconductor element 7. can.
  • the height of the portion where the thickness of the first joint portion 8 exists inside the first joint portion 8 of the first holding portion 6 is lower than the height of the portion existing outside the first joint portion 8. .. This makes it possible to reduce the deviation of the bonding position of the semiconductor element 7.
  • the first holding portion 6 is embedded in the first joining portion 8 and installed inside and outside the corner portion of the first joining portion 8, the first holding portion 6 is surely first up to the corner portion on the back surface of the semiconductor element 7. By joining (wetting and spreading) the joint portion 8, it is possible to improve the joint defect.
  • the first holding portion 6 is embedded in the first joining portion 8 and installed inside and outside the corner portion of the first joining portion 8, the first joining portion 8 gets wet and spreads in the holding portion 6. Therefore, fillets are formed on the side surfaces of the corners of the semiconductor element 7, and the stress at the corners of the semiconductor element 7 can be reduced.
  • the joint state can be improved and the heat dissipation from the semiconductor element 7 can be improved.
  • the third holding portion 63 is arranged on the back surface side of the semiconductor element 7 corresponding to the electrode 13 on the front surface of the semiconductor element 7, the heat generated by the semiconductor element 7 can be efficiently dissipated, and the reliability of the semiconductor device is improved. can do.
  • the first holding portion 6 used in the first embodiment is embedded in the second joint portion 3 as the second holding portion 6, and the corner portion of the metal layer 23 on the lower surface side of the insulating substrate 2 is embedded. It differs in that it is placed from the inside to the outside of.
  • the second holding portion 6 is embedded in the second joint portion 3 and arranged from the inside to the outside of the corner portion of the metal layer 23 on the lower surface side of the insulating substrate 2, so that the second holding portion 6 is placed on the base plate 1 of the insulating substrate 2. It is possible to reduce the joining failure at the time of joining. As a result, the heat dissipation from the insulating substrate 2 can be improved, and the reliability of the semiconductor device 300 can be improved. Since other points are the same as those in the first embodiment, detailed description thereof will be omitted.
  • FIG. 19 is a schematic plan structure diagram showing the semiconductor device according to the third embodiment.
  • FIG. 20 is a schematic cross-sectional structure diagram showing the semiconductor device according to the third embodiment.
  • FIG. 21 is another schematic cross-sectional structure showing the semiconductor device according to the third embodiment.
  • FIG. 22 is a schematic plan view showing a holding portion of the semiconductor device according to the third embodiment.
  • FIG. 20 is a schematic cross-sectional structure of the alternate long and short dash line EE of FIG.
  • FIG. 21 is a schematic cross-sectional structure of the alternate long and short dash line FF of FIG.
  • FIG. 22 is a schematic plan view of the arrangement of the second holding portion 6 as viewed from above through the second joint portion 3.
  • the semiconductor device 300 includes a base plate 1, an insulating substrate 2, a first joining portion 8 which is a joining portion, a second joining portion 3 which is a joining portion, and a second holding portion 6 which is a holding portion. , A semiconductor element 7, a bonding wire 9 which is a wiring portion, a sealing portion 10, and an electrode terminal 12.
  • the upper surface of the base plate 1 and the lower surface of the insulating substrate 2 are joined by using the second joining portion 3.
  • the upper surface of the insulating substrate 2 and the back surface of the semiconductor element 7 are bonded using the first bonding portion 8.
  • the second joint portion 3 that joins the metal layer 23 on the lower surface side of the insulating substrate 2 and the upper surface of the base plate 1 has an inner side facing diagonally from the corner portion of the metal layer 23 on the lower surface side of the insulating substrate 2.
  • the second holding portion 6 arranged on the outside is buried.
  • the insulating substrate 2 and the semiconductor element 7 bonded to the upper surface of the insulating substrate 2 are sealed in the sealing portion 10.
  • the sealing portion 10 is indicated by a dotted line so that the positional relationship of the members sealed in the sealing portion 10 can be understood.
  • the outermost circumference of the semiconductor device 300 is the peripheral edge of the base plate 1.
  • the sealing portion 10 is arranged inside the peripheral portion of the base plate 1.
  • the insulating layer 22 of the insulating substrate 2 is arranged inside the outer edge of the sealing portion 10.
  • the metal layer 21 on the upper surface side of the insulating substrate 2 is arranged inside the outer edge of the insulating layer 22 of the insulating substrate 2.
  • a semiconductor element 7 having an electrode 13 formed on the upper surface is arranged inside the outer edge of the metal layer 21 on the upper surface side of the insulating substrate 2.
  • the second joint 3 is arranged so as to protrude from the corners.
  • the electrode terminal 12 is arranged so as to straddle the insulating substrate 2 and protrudes (exposed) from the sealing portion 10.
  • FIG. 20 is a schematic cross-sectional structure of the insulating substrate 2 (semiconductor element 7) in the facing direction.
  • the upper surface of the base plate 1 and the lower surface of the metal layer 23 on the lower surface side of the insulating substrate 2 are joined by using the second joining portion 3.
  • the upper surface of the metal layer 21 on the upper surface side of the insulating substrate 2 and the back surface of the semiconductor element 7 are bonded by using the first bonding portion 8.
  • the bonding wire 9 electrically connects the electrode 13 on the surface of the semiconductor element 7 and the electrode terminal 12. Further, the bonding wire 9 electrically connects the predetermined position of the metal layer 21 on the upper surface side of the insulating substrate 2 and the electrode terminal 12.
  • the sealing portion 10 is in contact with the upper surface of the base plate 1 that is not bonded (exposed) to the metal layer 23 below the insulating substrate 2, and the semiconductor element 7 is bonded to the insulating substrate 2 and the upper surface of the insulating substrate 2. And is sealed.
  • the electrode terminal 12 is arranged on the upper part of the insulating substrate 2, one end side being arranged in the sealing portion 10, and the other end being exposed (protruding) from the side surface of the sealing portion 10.
  • FIG. 21 is a schematic cross-sectional structure diagram of the insulating substrate 2 (semiconductor element 7) in the diagonal direction.
  • a second holding portion 6 is arranged diagonally (toward) at a corner portion of the metal layer 23 on the lower surface side of the insulating substrate 2.
  • the holding portion 6 embedded in the second joint portion 3 is the second holding portion 6.
  • the second holding portion 6 is located inside the outer peripheral portion of the metal layer 23 on the lower surface side of the insulating substrate 2 and the outer peripheral portion of the metal layer 23 on the lower surface side of the insulating substrate 2. It has a second external holding portion 65 arranged on the outside.
  • the second holding portion 6 is arranged from the inside to the outside of the corner portion of the metal layer 23 on the lower surface side of the insulating substrate 2, and is embedded in the second joint portion 3.
  • the height of the loop portion of the second external holding portion 65 is the height at which the insulating substrate 2 is in contact with the outer peripheral side surface of the metal layer 23 on the lower surface side of the insulating substrate 2 after the insulating substrate 2 is bonded at the second bonding portion 3.
  • the loop portion of the second external holding portion 65 is arranged in contact with the outer peripheral side surface of the metal layer 23 on the lower surface side of the insulating substrate 2, so that the insulating substrate 2 at the time of joining the insulating substrate 2 at the second joining portion 3 is arranged. Can be positioned. In FIGS.
  • FIG. 22 is a top view of the inside of the second joint portion 3 through the inside.
  • the second joint portion 3 is arranged on the upper surface of the base plate 1.
  • the second joint portion 3 is joined to the lower surface of the metal layer 23 on the lower surface side of the insulating substrate 2, and protrudes (protrudes) from the outer shape (outer edge) of the metal layer 23 on the lower surface side of the insulating substrate 2. It has a fillet portion 31 of a joint portion 3.
  • a second portion is formed between the inside and the outside of the projection surface of the metal layer 23 on the lower surface side of the insulating substrate 2.
  • the holding portion 6 is embedded and arranged in the second joint portion 3.
  • the second internal holding portion 64 is arranged inside the projection surface of the metal layer 23 on the lower surface side of the insulating substrate 2, and the fillet portion 31 of the second joint portion 3 has a second holding portion 6.
  • the external holding portion 65 is arranged.
  • the corner of the second joint 3 is 0.25 times (1/4) the length (a or b) of each side from the corner apex (intersection of the sides) of the second joint 3 as a region. ), And it is sufficient that the second holding portion 6 is arranged within this range.
  • One end of the second internal holding portion 64 is arranged inside the corner portion of the metal layer 23 on the lower surface side of the insulating substrate 2, and the other end of the second internal holding portion 64 is from one end of the second internal holding portion 64. Is also arranged on the corner side of the metal layer 23 on the lower surface side of the insulating substrate 2. The same effect can be obtained by arranging a plurality of second holding portions 6 as shown in FIG.
  • the second holding portion 6 is for guiding the second joint portion 3 so that the second joint portion 3 is surely bonded (wet and spreads) to the corner portion of the lower surface of the metal layer 23 on the lower surface side of the insulating substrate 2. It is a thing.
  • the second holding portion 6 is arranged inside and outside the second joint portion 3 (arranged inside and outside the outer shape of the metal layer 23 on the lower surface side of the insulating substrate 2).
  • the upper surface of the second bonding portion 3 is in contact (bonding) with the lower surface of the metal layer 23 on the lower surface side of the insulating substrate 2.
  • the lower surface of the second joint portion 3 is in contact with (joins) the upper surface of the base plate 1.
  • the height of the second internal holding portion 64 which is a portion existing inside the outer shape of the metal layer 23 on the lower surface side of the insulating substrate 2, is a portion existing outside the outer shape of the metal layer 23 on the lower surface side of the insulating substrate 2. It is lower than the height of the second external holding portion 65. As a result, it is possible to reduce the deviation of the joining position of the insulating substrate 2 (the metal layer 23 on the lower surface side of the insulating substrate 2) at the time of joining the metal layer 23 on the lower surface side of the insulating substrate 2 and the base plate 1.
  • the second holding portion 6 is composed of the second joint portion 3 and a material having good wettability. Therefore, the second holding portion 6 forms an alloy layer at the contact interface with the second joining portion 3.
  • the configuration shown in FIGS. 5 to 12 of the first embodiment can be applied to the third embodiment, and the metal layer 21 on the upper surface side of the insulating substrate 2 and the back surface of the semiconductor element 7 are first joined.
  • the same effect can be obtained when the metal layer 23 on the lower surface side of the insulating substrate 2 and the upper surface of the base plate 1 are joined by the second joining portion 3.
  • the second holding portion 6 is installed inside and outside the corner portion of the metal layer 23 on the lower surface side of the insulating substrate 2, but may be integrally formed. Further, the second holding portion 6 is installed inside and outside the corner portion of the metal layer 23 on the lower surface side of the insulating substrate 2, but even if the inside and outside of the semiconductor element 7 are formed separately. good.
  • the second holding portion 6 is embedded in the second joint portion 3 and installed inside and outside the corner portion of the second joint portion 3, so that the second holding portion 6 is second. It is possible to reduce the deviation of the thickness of the joint portion 3 from the design value, improve the joint defect, and improve the reliability of the semiconductor device.
  • the second holding portion 6 is embedded in the second joint portion 3 and installed inside and outside the corner portion of the second joint portion 3, it is possible to reduce the deviation of the joint position of the insulating substrate 2. can.
  • the height of the portion where the thickness of the second joint portion 3 exists inside the second joint portion 3 of the second holding portion 6 is lower than the height of the portion existing outside the second joint portion 3. .. This makes it possible to reduce the deviation of the joining position of the insulating substrate 2.
  • the second holding portion 6 is embedded in the second joint portion 3 and installed inside and outside the corner portion of the second joint portion 3, the back surface of the metal layer 23 on the lower surface side of the insulating substrate 2 is used. By reliably joining (wetting and spreading) the second joint portion 3 to the corner portion, it is possible to improve the joint defect.
  • the second holding portion 6 is embedded in the second joint portion 3 and installed inside and outside the corner portion of the second joint portion 3, the second joint portion 3 gets wet with the second holding portion 6.
  • fillets are formed on the side surfaces of the corners of the metal layer 23 on the lower surface side of the insulating substrate 2, and the stress at the corners of the metal layer 23 on the lower surface side of the insulating substrate 2 can be reduced.
  • the joint state can be improved and the heat dissipation from the semiconductor element 7 can be improved.
  • the fourth holding portion 66 corresponds to the electrode 13 (the joint portion between the wiring portion 9 and the wiring portion 9) on the surface of the semiconductor element 7. It differs in that it is also arranged at the position of the lower surface of the metal layer 23 on the lower surface side of the insulating substrate 2. As described above, since the fourth holding portion 66 is also arranged on the lower surface of the metal layer 23 on the lower surface side of the insulating substrate 2 corresponding to the electrode 13 on the surface of the semiconductor element 7, the heat generated by the semiconductor element 7 is held fourth. It can be diffused through section 66. As a result, the heat dissipation from the semiconductor element 7 can be improved, and the reliability of the semiconductor device 400 can be improved. Since other points are the same as those in the second and third embodiments, detailed description thereof will be omitted.
  • FIG. 23 is a schematic plan structure diagram showing the semiconductor device according to the fourth embodiment.
  • FIG. 24 is a schematic cross-sectional structure showing the semiconductor device according to the third embodiment.
  • FIG. 25 is another schematic cross-sectional structure showing the semiconductor device according to the third embodiment.
  • FIG. 26 is a schematic plan view showing a holding portion of the semiconductor device according to the fourth embodiment.
  • FIG. 24 is a schematic cross-sectional structure of the alternate long and short dash line GG of FIG. 23.
  • FIG. 25 is a schematic cross-sectional structure of the alternate long and short dash line HH of FIG. 23.
  • FIG. 26 is a schematic plan view of the arrangement of the second holding portion 6 and the fourth holding portion 66 as viewed from above through the second joint portion 3.
  • the semiconductor device 400 includes a base plate 1, an insulating substrate 2, a first joining portion 8 which is a joining portion, a second joining portion 3 which is a joining portion, and a second holding portion 6 which is a holding portion.
  • a fourth holding portion 66 which is a holding portion, a semiconductor element 7, a bonding wire 9 which is a wiring portion, a sealing portion 10, and an electrode terminal 12 are provided.
  • the fourth holding portion 66 is shown by a dotted line.
  • the fourth holding portion 66 is arranged inside the outer shape of the electrode 13 on the surface of the semiconductor element 7.
  • the fourth holding portion 66 is arranged at the position of the lower surface of the metal layer 23 on the lower surface side of the insulating substrate 2 corresponding to the arrangement position of the electrode 13 on the surface of the semiconductor element 7. In particular, it is arranged at a corresponding position on the lower surface of the metal layer 23 on the lower surface side of the insulating substrate 2 including the portion where the bonding wire 9 of the electrode 13 on the surface of the semiconductor element 7 is bonded.
  • the thickness (height) of the fourth holding portion 66 is the same as the thickness (height) of the second internal holding portion 64.
  • the insulating substrate 2 is supported (held) by the second internal holding portion 64 and the fourth holding portion 66.
  • one end of the second internal holding portion 64 is arranged inside the corner portion of the metal layer 23 on the lower surface side of the insulating substrate 2, and the other end of the second internal holding portion 64 is the second internal holding portion. It is arranged on the corner side of the metal layer 23 on the lower surface side of the insulating substrate 2 with respect to one end of 64.
  • the fourth holding portion 66 is a central portion of the metal layer 23 on the lower surface side of the insulating substrate 2 than one end of the second internal holding portion 64 arranged at the corners (four corners) of the metal layer 23 on the lower surface side of the insulating substrate 2. It is located closer to you.
  • any form of the first holding unit 6 used in the first embodiment can be similarly applied.
  • the second holding portion 6 is embedded in the second joint portion 3 and installed inside and outside the corner portion of the second joint portion 3, so that the second holding portion 6 is second. It is possible to reduce the deviation of the thickness of the joint portion 3 from the design value, improve the joint defect, and improve the reliability of the semiconductor device.
  • the second holding portion 6 is embedded in the second joint portion 3 and installed inside and outside the corner portion of the second joint portion 3, the joint position of the metal layer 23 on the lower surface side of the insulating substrate 2 is formed. The deviation can be reduced.
  • the height of the portion where the thickness of the second joint portion 3 exists inside the second joint portion 3 of the second holding portion 6 is lower than the height of the portion existing outside the second joint portion 3. As a result, it is possible to reduce the deviation of the joining position of the metal layer 23 on the lower surface side of the insulating substrate 2.
  • the second holding portion 6 is embedded in the second joint portion 3 and installed inside and outside the corner portion of the second joint portion 3, the lower surface of the metal layer 23 on the lower surface side of the insulating substrate 2 By reliably joining (wetting and spreading) the second joint portion 3 to the corner portion, it is possible to improve the joint defect.
  • the second holding portion 6 is embedded in the second joint portion 3 and installed inside and outside the corner portion of the second joint portion 3, the second joint portion 3 gets wet and spreads in the holding portion 6. Therefore, fillets are formed on the side surfaces of the corners of the metal layer 23 on the lower surface side of the insulating substrate 2, and the stress at the corners of the metal layer 23 on the lower surface side of the insulating substrate 2 can be reduced.
  • the joint state can be improved and the heat dissipation from the semiconductor element 7 can be improved.
  • the fourth holding portion 66 is arranged on the lower surface side of the metal layer 23 on the lower surface side of the insulating substrate 2 corresponding to the electrode 13 on the surface of the semiconductor element 7, the heat generated by the semiconductor element 7 can be efficiently dissipated. The reliability of the semiconductor device can be improved.
  • Embodiment 5 the semiconductor device according to the first to fourth embodiments described above is applied to the power conversion device.
  • the present disclosure is not limited to a specific power conversion device, the case where the present disclosure is applied to a three-phase inverter will be described below as the fifth embodiment.
  • FIG. 27 is a block diagram showing a configuration of a power conversion system to which the power conversion device according to the fifth embodiment of the present disclosure is applied.
  • the power conversion system shown in FIG. 27 includes a power supply 1000, a power conversion device 2000, and a load 3000.
  • the power supply 1000 is a DC power supply, and supplies DC power to the power converter 2000.
  • the power supply 1000 can be composed of various things, for example, a DC system, a solar cell, a storage battery, a rectifier circuit connected to an AC system, an AC / DC converter, or the like. good. Further, the power supply 1000 may be configured by a DC / DC converter that converts the DC power output from the DC system into a predetermined power.
  • the power conversion device 2000 is a three-phase inverter connected between the power supply 1000 and the load 3000, converts the DC power supplied from the power supply 1000 into AC power, and supplies AC power to the load 3000. As shown in FIG. 27, the power conversion device 2000 converts the DC power input from the power supply 1000 into AC power and outputs the main conversion circuit 2001, and the main conversion circuit 2001 controls the control signal for controlling the main conversion circuit 2001. It is equipped with a control circuit 2003 that outputs to.
  • the load 3000 is a three-phase electric motor driven by AC power supplied from the power converter 2000.
  • the load 3000 is not limited to a specific application, and is an electric motor mounted on various electric devices, and is used as, for example, an electric motor for a hybrid vehicle, an electric vehicle, a railroad vehicle, an elevator, an air conditioner, and the like.
  • the main conversion circuit 2001 includes a switching element built in the semiconductor device 2002 and a freewheeling diode (not shown), and the DC power supplied from the power supply 1000 is converted into AC power by switching the switching element. And supply to the load 3000.
  • the main conversion circuit 2001 is a two-level three-phase full bridge circuit, and has six switching elements and each switching element. It can be composed of six freewheeling diodes connected in antiparallel.
  • the main conversion circuit 2001 is composed of a semiconductor device 2002 corresponding to any one of the above-described embodiments 1 to 5 in which each switching element, each freewheeling diode, and the like are built.
  • the six switching elements are connected in series for each of the two switching elements to form an upper and lower arm, and each upper and lower arm constitutes each phase (U phase, V phase, W phase) of the full bridge circuit.
  • the output terminals of each upper and lower arm that is, the three output terminals of the main conversion circuit 2001 are connected to the load 3000.
  • the main conversion circuit 2001 includes a drive circuit (not shown) for driving each switching element.
  • the drive circuit may be built in the semiconductor device 2002, or may be configured to include a drive circuit separately from the semiconductor device 2002.
  • the drive circuit generates a drive signal for driving the switching element of the main conversion circuit 2001 and supplies the drive signal to the control electrode of the switching element of the main conversion circuit 2001.
  • a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to the control electrode of each switching element.
  • the drive signal When the switching element is kept on, the drive signal is a voltage signal (on signal) equal to or higher than the threshold voltage of the switching element, and when the switching element is kept off, the drive signal is a voltage equal to or lower than the threshold voltage of the switching element. It becomes a signal (off signal).
  • the control circuit 2003 controls the switching element of the main conversion circuit 2001 so that the desired power is supplied to the load 3000. Specifically, the time (on time) for each switching element of the main conversion circuit 2001 to be in the on state is calculated based on the electric power to be supplied to the load 3000.
  • the main conversion circuit 2001 can be controlled by PWM control that modulates the on-time of the switching element according to the voltage to be output.
  • a control command is given to the drive circuit provided in the main conversion circuit 2001 so that an on signal is output to the switching element that should be turned on at each time point and an off signal is output to the switching element that should be turned off. Control signal) is output.
  • the drive circuit outputs an on signal or an off signal as a drive signal to the control electrode of each switching element according to this control signal.
  • the semiconductor device according to the first to fourth embodiments is applied as the semiconductor device 2002 of the main conversion circuit 2001, so that the reliability is improved. be able to.
  • the present disclosure is not limited to this, and can be applied to various power conversion devices.
  • the two-level power conversion device is used, but a three-level, multi-level power conversion device may be used, and when power is supplied to a single-phase load, the present disclosure is given to the single-phase inverter. It may be applied. Further, when power is supplied to a DC load or the like, the present disclosure can be applied to a DC / DC converter, an AC / DC converter, and the like.
  • the power conversion device to which the present disclosure is applied is not limited to the case where the above-mentioned load is an electric motor, and is, for example, a power supply device for a discharge machine, a laser machine, an induction heating cooker, or a non-contact power supply system. It can also be used as a power conditioner for a photovoltaic power generation system, a power storage system, or the like.
  • the power semiconductor element 7 when SiC is used as the semiconductor element 7, the power semiconductor element is operated at a higher temperature than that of Si in order to take advantage of its characteristics. Since a semiconductor device equipped with a SiC device is required to have higher reliability, the merit of the present disclosure of realizing a highly reliable semiconductor device becomes more effective.

Abstract

In the present invention, there is obtained a semiconductor device that ameliorates joining faults in portions where an insulation substrate and a semiconductor element are joined, or where a base plate and the insulation substrate are joined, so that reliability is improved. This semiconductor device comprises: a semiconductor element (7) that has an electrode (13) on the surface; an insulation substrate (2) that has metal layers (21, 23) on the top surface and the bottom surface, the semiconductor element (7) being joined by a first joining part (8) to the top surface of the top-surface-side metal layer (21); a base plate (1) to which the insulation substrate (2) is joined by a second joining part (3) on the top surface; and a holding part (6) that is embedded in the first joining part (8) and/or the second joining part (3), said holding part (6) being positioned on the inside and outside in the diagonal direction of the corner of the semiconductor element (7) when embedded in the first joining part (8), and positioned inside and outside in the diagonal direction of the corner of the metal layer (23) on the bottom-surface side of the insulation substrate (2) when embedded inside the second joining part (3).

Description

半導体装置、電力変換装置および半導体装置の製造方法Manufacturing method of semiconductor device, power conversion device and semiconductor device
　本開示は、保持部を用いて接合した半導体装置、半導体装置の製造方法および電力変換装置に関する。 The present disclosure relates to a semiconductor device joined by using a holding portion, a method for manufacturing the semiconductor device, and a power conversion device.
　半導体装置においては、半導体素子、絶縁基板およびベース板を備えており、半導体素子と絶縁基板と、絶縁基板とベース板とは接合部材を介して接合されている。 The semiconductor device includes a semiconductor element, an insulating substrate, and a base plate, and the semiconductor element and the insulating substrate, and the insulating substrate and the base plate are joined via a joining member.
　しかしながら、接合部材の上部に配置される部材が、接合部材の下部に配置される部材に対して傾いた状態で接合される場合がある。このような状態で部材同士を接合すると、上下の部材間において、接合部材の厚みに不均一が生じ、接合不良の原因となる。このため、接合部材の上部の部材と接合部材の下部の部材との傾きを少なく接合し、接合部材の上下に配置される部材間での接合不良を低減することが求められる。 However, the member arranged at the upper part of the joining member may be joined in an inclined state with respect to the member arranged at the lower part of the joining member. When the members are joined together in such a state, the thickness of the joined members becomes uneven between the upper and lower members, which causes a poor joining. Therefore, it is required to reduce the inclination of the upper member of the joining member and the lower member of the joining member to be small, and to reduce the joining failure between the members arranged above and below the joining member.
　そこで、部材間の接合時の傾きを低減する目的で、はんだ接合材の外周部に絶縁性樹脂スペーサを備えた半導体装置が開示されている（例えば、特許文献１）。また、塗布剤層内に基材と電子部品との間隔を規制し、加熱により形状変化しない複数の導電性の固体スペーサが埋設された半導体装置が開示されている（例えば、特許文献２）。さらに、半導体素子の外周部にボンディングワイヤ線を配置した半導体装置が開示されている（例えば、特許文献３）。 Therefore, for the purpose of reducing the inclination at the time of joining between the members, a semiconductor device provided with an insulating resin spacer on the outer peripheral portion of the solder joining material is disclosed (for example, Patent Document 1). Further, there is disclosed a semiconductor device in which a plurality of conductive solid spacers that regulate the distance between a base material and an electronic component and do not change in shape by heating are embedded in the coating agent layer (for example, Patent Document 2). Further, a semiconductor device in which a bonding wire is arranged on an outer peripheral portion of a semiconductor element is disclosed (for example, Patent Document 3).
特開２０１３－３８２２号公報Japanese Unexamined Patent Publication No. 2013-3822 特開２０１２－２８４３３号公報Japanese Unexamined Patent Publication No. 2012-28433 特開２００９－１７０５４３号公報Japanese Unexamined Patent Publication No. 2009-170543
　しかしながら、特許文献１に記載の半導体装置においては、スペーサが、絶縁性の樹脂であるため、はんだとの濡れ性はそれほど高くなく、き裂の起点となりうる場合があった。また、特許文献２に記載の半導体装置においては、固体スペーサの配置の仕方によっては、はんだの溶融時に、はんだの濡れ広がりを妨げる、または、気泡の抜けを妨げるため、接合不良が発生する場合があった。さらに、特許文献３に記載の半導体装置においては、ボンディングワイヤ線により、半導体素子の接合位置精度を向上することができるが、はんだ（接合部）の濡れ広がりを調整する機能はなく、はんだ接合不良が生じる場合があった。このため、従来の半導体装置では、接合不良の改善が十分ではなく、半導体装置の信頼性が劣化する問題点があった。 However, in the semiconductor device described in Patent Document 1, since the spacer is an insulating resin, the wettability with the solder is not so high, and it may be a starting point of cracks. Further, in the semiconductor device described in Patent Document 2, depending on the method of arranging the solid spacers, when the solder is melted, the solder does not spread wet and spread, or bubbles are prevented from coming out, so that a bonding defect may occur. there were. Further, in the semiconductor device described in Patent Document 3, the bonding position accuracy of the semiconductor element can be improved by the bonding wire, but there is no function of adjusting the wetting spread of the solder (joint portion), and the solder bonding is defective. May occur. For this reason, the conventional semiconductor device has a problem that the improvement of the bonding defect is not sufficient and the reliability of the semiconductor device is deteriorated.
　本開示は、上述のような問題を解決するためになされたもので、保持部を用いて半導体装置における接合部の上下に配置される部材間の接合不良を改善することで、信頼性を向上させた半導体装置を得ることを目的としている。 The present disclosure has been made to solve the above-mentioned problems, and improves reliability by improving the bonding failure between the members arranged above and below the bonding portion in the semiconductor device by using the holding portion. The purpose is to obtain a semiconductor device that has been made.
　本開示に係る半導体装置は、表面に電極を有する半導体素子と、上面と下面とに金属層を有し、半導体素子が上面側の金属層上に第一接合部で接合された絶縁基板と、絶縁基板が上面に第二接合部で接合されたベース板と、第一接合部と第二接合部との少なくともいずれか一方に埋設され、第一接合部内に埋設された場合は半導体素子の角部の対角方向で内側と外側とに配置され、第二接合部内に埋設された場合は絶縁基板の下面側の金属層の角部の対角方向で内側と外側とに配置される保持部と、を備えた半導体装置である。 The semiconductor device according to the present disclosure includes a semiconductor element having an electrode on the surface, an insulating substrate having metal layers on the upper surface and the lower surface, and the semiconductor element bonded to the metal layer on the upper surface side at the first junction. When the insulating substrate is embedded in at least one of the base plate bonded at the second junction on the upper surface and the first junction and the second junction, and embedded in the first junction, the corner of the semiconductor element. Holding portions that are arranged diagonally inside and outside, and when embedded in the second joint, are arranged diagonally inside and outside the corners of the metal layer on the lower surface side of the insulating substrate. It is a semiconductor device equipped with.
　本開示によれば、接合部の角部の内側と外側とに保持部を設けたので、接合部の上下に配置された部材間の接合性の向上が可能となり、半導体装置の信頼性を向上させることができる。 According to the present disclosure, since the holding portions are provided inside and outside the corners of the joint portion, it is possible to improve the bondability between the members arranged above and below the joint portion, and improve the reliability of the semiconductor device. Can be made to.
実施の形態１における半導体装置を示す平面構造模式図である。It is a planar structure schematic diagram which shows the semiconductor device in Embodiment 1. FIG. 実施の形態１における半導体装置を示す断面構造模式図である。It is sectional drawing which shows the semiconductor device in Embodiment 1. FIG. 実施の形態１における半導体装置を示す断面構造模式図である。It is sectional drawing which shows the semiconductor device in Embodiment 1. FIG. 実施の形態１における半導体装置の保持部を示す平面構造模式図である。It is a planar structure schematic diagram which shows the holding part of the semiconductor device in Embodiment 1. FIG. 実施の形態１における半導体装置の接合部を示す断面構造模式図である。It is sectional drawing which shows the joint part of the semiconductor device in Embodiment 1. FIG. 実施の形態１における半導体装置の接合部を示す断面構造模式図である。It is sectional drawing which shows the joint part of the semiconductor device in Embodiment 1. FIG. 実施の形態１における半導体装置の他の接合部を示す断面構造模式図である。It is sectional drawing which shows the other junction part of the semiconductor device in Embodiment 1. FIG. 実施の形態１における半導体装置の他の接合部を示す断面構造模式図である。It is sectional drawing which shows the other junction part of the semiconductor device in Embodiment 1. FIG. 実施の形態１における半導体装置の他の接合部を示す平面構造模式図である。It is a planar structure schematic diagram which shows the other joint part of the semiconductor device in Embodiment 1. FIG. 実施の形態１における半導体装置の他の接合部を示す断面構造模式図である。It is sectional drawing which shows the other junction part of the semiconductor device in Embodiment 1. FIG. 実施の形態１における半導体装置の他の接合部を示す断面構造模式図である。It is sectional drawing which shows the other junction part of the semiconductor device in Embodiment 1. FIG. 実施の形態１における半導体装置の他の接合部を示す平面構造模式図である。It is a planar structure schematic diagram which shows the other joint part of the semiconductor device in Embodiment 1. FIG. 実施の形態１における半導体装置の他の保持部を示す平面構造模式図である。It is a planar structure schematic diagram which shows the other holding part of the semiconductor device in Embodiment 1. FIG. 実施の形態１における他の半導体装置を示す断面構造模式図である。It is sectional drawing which shows the other semiconductor device in Embodiment 1. FIG. 実施の形態２における半導体装置を示す平面構造模式図である。It is a planar structure schematic diagram which shows the semiconductor device in Embodiment 2. 実施の形態２における半導体装置を示す断面構造模式図である。It is sectional drawing which shows the semiconductor device in Embodiment 2. 実施の形態２における半導体装置を示す断面構造模式図である。It is sectional drawing which shows the semiconductor device in Embodiment 2. 実施の形態２における半導体装置の保持部を示す平面構造模式図である。It is a plane structure schematic diagram which shows the holding part of the semiconductor device in Embodiment 2. 実施の形態３における半導体装置を示す平面構造模式図である。It is a planar structure schematic diagram which shows the semiconductor device in Embodiment 3. FIG. 実施の形態３における半導体装置を示す断面構造模式図である。It is sectional drawing which shows the semiconductor device in Embodiment 3. FIG. 実施の形態３における半導体装置を示す断面構造模式図である。It is sectional drawing which shows the semiconductor device in Embodiment 3. FIG. 実施の形態３における半導体装置の保持部を示す断面構造模式図である。It is sectional drawing which shows the holding part of the semiconductor device in Embodiment 3. FIG. 実施の形態４における半導体装置を示す平面構造模式図である。It is a planar structure schematic diagram which shows the semiconductor device in Embodiment 4. 実施の形態４における半導体装置を示す断面構造模式図である。It is sectional drawing which shows the semiconductor device in Embodiment 4. 実施の形態４における半導体装置を示す断面構造模式図である。It is sectional drawing which shows the semiconductor device in Embodiment 4. 実施の形態４における半導体装置の保持部を示す平面構造模式図である。It is a plane structure schematic diagram which shows the holding part of the semiconductor device in Embodiment 4. 実施の形態５における電力変換装置を適用した電力変換システムの構成を示すブロック図である。It is a block diagram which shows the structure of the power conversion system to which the power conversion apparatus in Embodiment 5 is applied.
　はじめに、本開示の半導体装置の全体構成について、図面を参照しながら説明する。なお、図は模式的なものであり、示された構成要素の正確な大きさなどを反映するものではない。また、同一の符号を付したものは、同一又はこれに相当するものであり、このことは明細書の全文において共通することである。 First, the overall configuration of the semiconductor device disclosed in the present disclosure will be described with reference to the drawings. It should be noted that the figure is a schematic one and does not reflect the exact size of the indicated components. Further, those having the same reference numerals are the same or equivalent thereof, and this is common to the whole text of the specification.
実施の形態１．
　図１は、実施の形態１における半導体装置を示す平面構造模式図である。図２は、実施の形態１における半導体装置を示す断面構造模式図である。図３は、実施の形態１における半導体装置を示す他の断面構造模式図である。図４は、実施の形態１における半導体装置の保持部を示す平面構造模式図である。図２は、図１の一点鎖線ＡＡにおける断面構造模式図である。図３は、図１の一点鎖線ＢＢにおける断面構造模式図である。図４は、第一接合部８を透過して、第一保持部６の配置を上面側から見た平面構造模式図である。 Embodiment 1.
FIG. 1 is a schematic plan view showing a semiconductor device according to the first embodiment. FIG. 2 is a schematic cross-sectional structure diagram showing the semiconductor device according to the first embodiment. FIG. 3 is another schematic cross-sectional structure showing the semiconductor device according to the first embodiment. FIG. 4 is a schematic plan view showing a holding portion of the semiconductor device according to the first embodiment. FIG. 2 is a schematic cross-sectional structure of the alternate long and short dash line AA of FIG. FIG. 3 is a schematic cross-sectional structure of the alternate long and short dash line BB of FIG. FIG. 4 is a schematic plan view of the arrangement of the first holding portion 6 as viewed from the upper surface side through the first joining portion 8.
　図において、半導体装置１００は、ベース板１と、絶縁基板２と、接合部である第一接合部８と、接合部である第二接合部３と、保持部である第一保持部６と、半導体素子７と、配線部であるボンディングワイヤ９と、封止部１０と、電極端子１２と、を備えている。 In the figure, the semiconductor device 100 includes a base plate 1, an insulating substrate 2, a first joining portion 8 which is a joining portion, a second joining portion 3 which is a joining portion, and a first holding portion 6 which is a holding portion. , A semiconductor element 7, a bonding wire 9 which is a wiring portion, a sealing portion 10, and an electrode terminal 12.
　図において、半導体装置１００は、ベース板１の上面と絶縁基板２の下面とを第二接合部３を用いて接合している。絶縁基板２の上面と半導体素子７の裏面（下面）とを第一接合部８を用いて接合している。半導体素子７の裏面と絶縁基板２の上面とを接合する第一接合部８には、半導体素子７の角部の対角方向へ向いて内側と外側に配置された第一保持部６が埋設されている。絶縁基板２と絶縁基板２の上面に接合された半導体素子７とは、封止部１０内に封止されている。 In the figure, in the semiconductor device 100, the upper surface of the base plate 1 and the lower surface of the insulating substrate 2 are joined by using the second joining portion 3. The upper surface of the insulating substrate 2 and the back surface (lower surface) of the semiconductor element 7 are joined by using the first joining portion 8. In the first joining portion 8 that joins the back surface of the semiconductor element 7 and the upper surface of the insulating substrate 2, the first holding portions 6 arranged inside and outside facing the corners of the semiconductor element 7 in the diagonal direction are embedded. Has been done. The insulating substrate 2 and the semiconductor element 7 bonded to the upper surface of the insulating substrate 2 are sealed in the sealing portion 10.
　図１において、封止部１０は、点線にて表示し、封止部１０に封止されている部材の位置関係がわかるようにしている。半導体装置１００の最外周は、ベース板１の周縁部である。ベース板１の周縁部よりも内側には、封止部１０が配置されている。封止部１０の外縁よりも内側には、絶縁基板２の絶縁層２２が配置されている。絶縁基板２の絶縁層２２の外縁よりも内側には、絶縁基板２の上面側の金属層２１が配置されている。絶縁基板２の上面側の金属層２１の外縁よりも内側には、電極１３が表面に形成された半導体素子７が配置されている。半導体素子７の裏面側の角部（四隅）には、第一接合部８が角部からはみ出して配置されている。電極端子１２は、絶縁基板２を跨いで配置され、封止部１０から突出（露出）している。 In FIG. 1, the sealing portion 10 is indicated by a dotted line so that the positional relationship of the members sealed in the sealing portion 10 can be understood. The outermost circumference of the semiconductor device 100 is the peripheral edge of the base plate 1. The sealing portion 10 is arranged inside the peripheral portion of the base plate 1. The insulating layer 22 of the insulating substrate 2 is arranged inside the outer edge of the sealing portion 10. The metal layer 21 on the upper surface side of the insulating substrate 2 is arranged inside the outer edge of the insulating layer 22 of the insulating substrate 2. A semiconductor element 7 having an electrode 13 formed on its surface is arranged inside the outer edge of the metal layer 21 on the upper surface side of the insulating substrate 2. At the corners (four corners) on the back surface side of the semiconductor element 7, the first joint portion 8 is arranged so as to protrude from the corner portion. The electrode terminal 12 is arranged so as to straddle the insulating substrate 2 and protrudes (exposed) from the sealing portion 10.
　図２は、半導体素子７の対面方向の断面構造模式図である。図２において、ベース板１の上面と絶縁基板２の下面側の金属層２３の下面とを第二接合部３を用いて接合している。絶縁基板２の上面側の金属層２１の上面と半導体素子７の裏面とを第一接合部８を用いて接合している。ボンディングワイヤ９は、半導体素子７の表面（上面）の電極１３と電極端子１２（右側）とを電気的に接続している。また、ボンディングワイヤ９は、絶縁基板２の上面側の金属層２１の所定の位置と電極端子１２（左側）とを電気的に接続している。封止部１０は、絶縁基板２の下面側の金属層２３と接合していない（露出した）ベース板１の上面と接して、絶縁基板２と絶縁基板２の上面に接合された半導体素子７とを封止している。電極端子１２は、絶縁基板２の上部で、一端側が封止部１０内に配置され、他端が封止部１０の側面から露出（突出）して配置される。 FIG. 2 is a schematic cross-sectional structure of the semiconductor element 7 in the facing direction. In FIG. 2, the upper surface of the base plate 1 and the lower surface of the metal layer 23 on the lower surface side of the insulating substrate 2 are joined by using the second joining portion 3. The upper surface of the metal layer 21 on the upper surface side of the insulating substrate 2 and the back surface of the semiconductor element 7 are bonded by using the first bonding portion 8. The bonding wire 9 electrically connects the electrode 13 on the surface (upper surface) of the semiconductor element 7 and the electrode terminal 12 (right side). Further, the bonding wire 9 electrically connects a predetermined position of the metal layer 21 on the upper surface side of the insulating substrate 2 and the electrode terminal 12 (left side). The sealing portion 10 is in contact with the upper surface of the base plate 1 which is not bonded (exposed) to the metal layer 23 on the lower surface side of the insulating substrate 2, and the semiconductor element 7 is bonded to the insulating substrate 2 and the upper surface of the insulating substrate 2. And is sealed. The electrode terminal 12 is arranged on the upper part of the insulating substrate 2, one end side being arranged in the sealing portion 10, and the other end being exposed (protruding) from the side surface of the sealing portion 10.
　図３は、半導体素子７の対角方向の断面構造模式図である。図３において、半導体素子７の角部には、対角方向に対して（向かって）第一保持部６が配置されている。第一接合部８内に埋設される保持部６が、第一保持部６である。第一保持部６は、半導体素子７の外周部よりも内側に配置される第一内部保持部６１と、半導体素子７の外周部よりも外側に配置される第一外部保持部６２とを有している。第一保持部６は、半導体素子７の角部の内側から外側に配置され、第一接合部８の中に埋設されている。 FIG. 3 is a schematic cross-sectional structure diagram of the semiconductor element 7 in the diagonal direction. In FIG. 3, a first holding portion 6 is arranged at a corner portion of the semiconductor element 7 in a diagonal direction (toward). The holding portion 6 embedded in the first joining portion 8 is the first holding portion 6. The first holding portion 6 has a first internal holding portion 61 arranged inside the outer peripheral portion of the semiconductor element 7, and a first external holding portion 62 arranged outside the outer peripheral portion of the semiconductor element 7. is doing. The first holding portion 6 is arranged from the inside to the outside of the corner portion of the semiconductor element 7, and is embedded in the first joining portion 8.
　図４は、第一接合部８の内部を透過して上面視した図である。図４において、絶縁基板２の上面側の金属層２１の上面には、第一接合部８が配置されている。第一接合部８は、半導体素子７の裏面と接合し、半導体素子７の外形よりも外側にはみ出した（突出した）第一接合部８のフィレット部８１を有している。第一接合部８の角部（半導体素子７の角部と同等）には、半導体素子７の投影面の内側から外側の間に第一保持部６が第一接合部８の中に埋設されて配置されている。第一保持部６は、半導体素子７の投影面よりも内側には、第一内部保持部６１が配置され、第一接合部８のフィレット部８１には、第一外部保持部６２が配置されている。なお、図４に示すように、第一接合部８の角部とは、領域として、第一接合部８の角部頂点（辺の交点）から各辺の長さ（ａまたはｂ）の０.２５倍（１/４）の範囲までをいい、第一保持部６は、この範囲内に配置されていればよい。第一内部保持部６１の一端は、半導体素子７の角部よりも内側に配置され、第一内部保持部６１の他端は、第一内部保持部６１の一端よりも半導体素子７の角部側に配置される。 FIG. 4 is a top view of the inside of the first joint portion 8 through the inside. In FIG. 4, the first joint portion 8 is arranged on the upper surface of the metal layer 21 on the upper surface side of the insulating substrate 2. The first joint portion 8 has a fillet portion 81 of the first joint portion 8 that is joined to the back surface of the semiconductor element 7 and protrudes (protrudes) from the outer shape of the semiconductor element 7. At the corner of the first junction 8 (equivalent to the corner of the semiconductor element 7), the first holding portion 6 is embedded in the first junction 8 between the inside and the outside of the projection surface of the semiconductor element 7. Are arranged. In the first holding portion 6, the first internal holding portion 61 is arranged inside the projection surface of the semiconductor element 7, and the first external holding portion 62 is arranged in the fillet portion 81 of the first joining portion 8. ing. As shown in FIG. 4, the corner portion of the first joint portion 8 is 0 of the length (a or b) of each side from the corner apex (intersection of the sides) of the first joint portion 8 as a region. It means up to a range of .25 times (1/4), and the first holding portion 6 may be arranged within this range. One end of the first internal holding portion 61 is arranged inside the corner portion of the semiconductor element 7, and the other end of the first internal holding portion 61 is a corner portion of the semiconductor element 7 rather than one end of the first internal holding portion 61. Placed on the side.
　ベース板１は、板状であり、半導体装置１００の底面部（底板）である。ベース板１は、半導体装置１００内部で発生した熱を半導体装置１００の外部へ放熱する放熱部材として機能する。ベース板１は、ベース板１の上面が絶縁基板２の下面側の金属層２３の下面と、第二接合部３を介して（用いて）接合されている。ベース板１の材料としては、銅合金またはアルミニウム合金などを用いることができる。ベース板１の第二接合部３との接合領域の外側には、封止部１０の下面が接している。 The base plate 1 has a plate shape and is a bottom surface portion (bottom plate) of the semiconductor device 100. The base plate 1 functions as a heat radiating member that dissipates heat generated inside the semiconductor device 100 to the outside of the semiconductor device 100. In the base plate 1, the upper surface of the base plate 1 is bonded (using) to the lower surface of the metal layer 23 on the lower surface side of the insulating substrate 2 via the second joint portion 3. As the material of the base plate 1, a copper alloy, an aluminum alloy, or the like can be used. The lower surface of the sealing portion 10 is in contact with the outside of the joint region of the base plate 1 with the second joint portion 3.
　絶縁基板２は、上面層と中間層と下面層とを有している。絶縁基板２の下面側の金属層２３は、ベース板１の上面に対向している。絶縁基板２は、中間層として絶縁層２２、上面層として絶縁層２２の上面側に金属層２１と、下面層として絶縁層２２の下面側に金属層２３と、を有している。絶縁層２２の下面側の金属層２３は、第二接合部３によりベース板１の上面と接合されている。絶縁基板２は板状であり、板状の絶縁基板２を平面（上面）方向から見た場合において、絶縁層２２の上面側の金属層２１の大きさは、絶縁層２２の大きさよりも小さくなっている。絶縁層２２の下面側の金属層２３の大きさは、絶縁層２２の大きさよりも小さくなっている。絶縁層２２の端部は、絶縁層２２の上面側の金属層２１および絶縁層２２の下面側の金属層２３の端部よりも外側へ突出している。この構成は、絶縁層２２を挟んで、絶縁層２２の上面側の金属層２１が、絶縁層２２の下面側の金属層２３およびベース板１との間で沿面放電を抑制（沿面距離を確保）するためである。 The insulating substrate 2 has an upper surface layer, an intermediate layer, and a lower surface layer. The metal layer 23 on the lower surface side of the insulating substrate 2 faces the upper surface of the base plate 1. The insulating substrate 2 has an insulating layer 22 as an intermediate layer, a metal layer 21 on the upper surface side of the insulating layer 22 as an upper surface layer, and a metal layer 23 on the lower surface side of the insulating layer 22 as a lower surface layer. The metal layer 23 on the lower surface side of the insulating layer 22 is joined to the upper surface of the base plate 1 by the second joint portion 3. The insulating substrate 2 has a plate shape, and when the plate-shaped insulating substrate 2 is viewed from the plane (upper surface) direction, the size of the metal layer 21 on the upper surface side of the insulating layer 22 is smaller than the size of the insulating layer 22. It has become. The size of the metal layer 23 on the lower surface side of the insulating layer 22 is smaller than the size of the insulating layer 22. The end portion of the insulating layer 22 projects outward from the end portion of the metal layer 21 on the upper surface side of the insulating layer 22 and the metal layer 23 on the lower surface side of the insulating layer 22. In this configuration, the metal layer 21 on the upper surface side of the insulating layer 22 suppresses creeping discharge between the metal layer 23 on the lower surface side of the insulating layer 22 and the base plate 1 with the insulating layer 22 interposed therebetween (securing the creeping distance). ).
　また、絶縁層２２の上面側の金属層２１は、目的に応じて複数に分割され、回路パターンを形成してもよい。絶縁基板２の絶縁層２２の材料としては、酸化アルミニウム（Ａｌ２Ｏ３）や窒化アルミニウム（ＡｌＮ）や窒化珪素（Ｓｉ３Ｎ４）などを用いることができる。絶縁基板２の上面側の金属層２１および下面側の金属層２３の材料としては、銅合金やアルミニウム合金などを用いることができる。絶縁基板２の上面側の金属層２１の上面には、半導体素子７が第一接合部８で接合されている。なお、絶縁基板２の上面側は、絶縁層２２の上面側、絶縁基板２の下面側は、絶縁層２２の下面側と同義である。 Further, the metal layer 21 on the upper surface side of the insulating layer 22 may be divided into a plurality of pieces according to the purpose to form a circuit pattern. As the material of the insulating layer 22 of the insulating substrate 2, aluminum oxide (Al 2 O 3 ), aluminum nitride (Al N), silicon nitride (Si 3 N 4 ), or the like can be used. As the material of the metal layer 21 on the upper surface side and the metal layer 23 on the lower surface side of the insulating substrate 2, a copper alloy, an aluminum alloy, or the like can be used. A semiconductor element 7 is bonded to the upper surface of the metal layer 21 on the upper surface side of the insulating substrate 2 by a first bonding portion 8. The upper surface side of the insulating substrate 2 is synonymous with the upper surface side of the insulating layer 22, and the lower surface side of the insulating substrate 2 is synonymous with the lower surface side of the insulating layer 22.
　第二接合部３は、ベース板１の上面と絶縁基板２の下面側の金属層２３の下面とを接合するための接合部材である。第二接合部３の材料としては、はんだが用いられ、必要に応じて焼結銀、焼結銅などを用いてもよい。ベース板１の中央領域には、絶縁基板２が接合される。 The second joint portion 3 is a joining member for joining the upper surface of the base plate 1 and the lower surface of the metal layer 23 on the lower surface side of the insulating substrate 2. Solder is used as the material of the second joint portion 3, and sintered silver, sintered copper, or the like may be used if necessary. The insulating substrate 2 is joined to the central region of the base plate 1.
　第一接合部８は、絶縁基板２の上面側の金属層２１の上面と半導体素子７の裏面とを接合するための接合材である。第一接合部８の材料としては、第二接合部３と同様に、はんだ、焼結銀または焼結銅などを用いることができる。 The first bonding portion 8 is a bonding material for bonding the upper surface of the metal layer 21 on the upper surface side of the insulating substrate 2 and the back surface of the semiconductor element 7. As the material of the first joint portion 8, solder, sintered silver, sintered copper, or the like can be used as in the case of the second joint portion 3.
　配線部９は、絶縁基板２の上面側の金属層２１の所定の位置と電極端子１２とを電気的に接続している。また、配線部９は、半導体素子７の表面の電極１３と電極端子１２とを電気的に接合している。さらに、複数の半導体素子７を用いている場合では、複数の半導体素子７間を電気的に接続する。配線部９としては、アルミニウム合金製ワイヤ、銅合金製ワイヤ、金製ワイヤ、銅合金製リード、アルミニウム合金製リボンまたは銅合金製リボンなどを用いることができる。表面のみニッケル、金、銀、すずなどのめっき処理がされたワイヤ、リード、リボンなどを用いてもよい。 The wiring portion 9 electrically connects the predetermined position of the metal layer 21 on the upper surface side of the insulating substrate 2 and the electrode terminal 12. Further, the wiring portion 9 electrically joins the electrode 13 on the surface of the semiconductor element 7 and the electrode terminal 12. Further, when a plurality of semiconductor elements 7 are used, the plurality of semiconductor elements 7 are electrically connected to each other. As the wiring portion 9, an aluminum alloy wire, a copper alloy wire, a gold wire, a copper alloy lead, an aluminum alloy ribbon, a copper alloy ribbon, or the like can be used. Wires, leads, ribbons, etc. plated with nickel, gold, silver, tin, etc. on the surface alone may be used.
　半導体素子７は、半導体素子７の表面に電極１３が配置されている。半導体素子７は、絶縁基板２の上面側の金属層２１の上面に接合部である第一接合部８を介して接合されている。半導体素子７は、ＭＯＳＦＥＴ（Ｍｅｔａｌ　Ｏｘｉｄｅ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　Ｆｉｅｌｄ　Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ）やＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ　Ｇａｔｅ　Ｂｉｐｏｌａｒ　Ｔｒａｎｓｉｓｔｏｒ）などの電力用半導体素子などを用いることができる。また、半導体素子７の材料としては、珪素（Ｓｉ：Ｓｉｌｉｃｏｎ）や炭化珪素（ＳｉＣ：Ｓｉｌｉｃｏｎ　Ｃａｂｉｄｅ）などを用いることができる。 In the semiconductor element 7, the electrode 13 is arranged on the surface of the semiconductor element 7. The semiconductor element 7 is bonded to the upper surface of the metal layer 21 on the upper surface side of the insulating substrate 2 via a first bonding portion 8 which is a bonding portion. As the semiconductor element 7, a power semiconductor element such as a MOSFET (Metal Oxide Semiconductor Field Transistor) or an IGBT (Insulated Gate Bipolar Transistor) can be used. Further, as the material of the semiconductor element 7, silicon (Si: Silicon), silicon carbide (SiC: Silicon Cabide), or the like can be used.
　第一保持部６は、第一接合部８内に埋設され、第一接合部８の角部の内側と外側とに設置される、言い換えると、第一接合部８内に埋設され、半導体素子７の下面側で半導体素子７の角部の内側と外側とに設置される。 The first holding portion 6 is embedded in the first joint portion 8 and installed inside and outside the corner portion of the first joint portion 8, in other words, is embedded in the first joint portion 8 and is a semiconductor device. It is installed on the lower surface side of the semiconductor element 7 inside and outside the corner portion of the semiconductor element 7.
　第一保持部６は、半導体素子７の下面側で半導体素子７の角部の内側と外側とに設置されるが、一体で形成されていてもよい。また、第一保持部６は、半導体素子７の下面側で半導体素子７の角部の内側と外側とに設置されるが、半導体素子７の内側と外側とを別体で形成されていてもよい。 The first holding portion 6 is installed on the lower surface side of the semiconductor element 7 inside and outside the corner portion of the semiconductor element 7, but may be integrally formed. Further, the first holding portion 6 is installed on the lower surface side of the semiconductor element 7 on the inner side and the outer side of the corner portion of the semiconductor element 7, but even if the inner side and the outer side of the semiconductor element 7 are formed separately. good.
　第一保持部６は、半導体素子７を半導体素子７の下面側から支持する。第一接合部８内に配置される第一保持部６は、第一接合部８の厚みの設計値からのずれを低減する。第一保持部６は、第一接合部８の厚みのばらつきを低減するので、半導体素子７の傾きを低減する。第一保持部６は、第一接合部８の厚みのばらつきを低減するので、半導体素子７からの放熱性が改善される。第一保持部６は、半導体素子７の接合位置のずれを低減する。 The first holding portion 6 supports the semiconductor element 7 from the lower surface side of the semiconductor element 7. The first holding portion 6 arranged in the first joint portion 8 reduces the deviation of the thickness of the first joint portion 8 from the design value. Since the first holding portion 6 reduces the variation in the thickness of the first joining portion 8, the inclination of the semiconductor element 7 is reduced. Since the first holding portion 6 reduces the variation in the thickness of the first joint portion 8, the heat dissipation from the semiconductor element 7 is improved. The first holding portion 6 reduces the deviation of the bonding position of the semiconductor element 7.
　第一保持部６は、半導体素子７の裏面の角部まで確実に第一接合部８が接合される（濡れ広がる）ように第一接合部８を誘導するためのものである。第一保持部６は、第一接合部８の内側と外側に配置（半導体素子７の外形（外縁）の内側と外側に配置）されていている。第一接合部８の上面は、半導体素子７の裏面に接触(接合)している。第一接合部８の下面は、絶縁基板２の上面側の金属層２１に接触（接合）している。半導体素子７の外形より内側に存在する部分である第一内部保持部６１の高さは、半導体素子７の外形よりも外側に存在する部分である第一外部保持部６２の高さに比べて低い。これにより、半導体素子７と絶縁基板２との接合時の半導体素子７の接合位置のずれを低減することができる。 The first holding portion 6 is for guiding the first joining portion 8 so that the first joining portion 8 is surely joined (wet and spreads) to the corner portion on the back surface of the semiconductor element 7. The first holding portion 6 is arranged inside and outside the first joining portion 8 (arranged inside and outside the outer shape (outer edge) of the semiconductor element 7). The upper surface of the first bonding portion 8 is in contact (bonding) with the back surface of the semiconductor element 7. The lower surface of the first bonding portion 8 is in contact (bonding) with the metal layer 21 on the upper surface side of the insulating substrate 2. The height of the first internal holding portion 61, which is a portion existing inside the outer shape of the semiconductor element 7, is higher than the height of the first external holding portion 62, which is a portion existing outside the outer shape of the semiconductor element 7. Low. As a result, it is possible to reduce the deviation of the bonding position of the semiconductor element 7 when the semiconductor element 7 and the insulating substrate 2 are bonded.
　また、第一保持部６の形状としては、ボンディングワイヤを用いたワイヤ形状、金属部材を用いたブロック形状が考えられる。後述するように、図５から図８に示すとおり、ワイヤ形状であれば配線部９を半導体素子７へ接合する装置と同じ装置で接合（形成）することができる。第一保持部６の材質としては、第一接合部８と濡れ性のよい物質、例えば、アルミニウム合金、銅合金、金、すずを用いることができる。また、第一保持部６の表面を第一接合部８と濡れ性のよい材質やめっき処理されたものを用いてもよい。このような構成とすることで、第一保持部６は、第一接合部８との接触界面で合金層を形成する。 Further, as the shape of the first holding portion 6, a wire shape using a bonding wire and a block shape using a metal member can be considered. As will be described later, as shown in FIGS. 5 to 8, if the wire shape is used, the wiring portion 9 can be joined (formed) by the same device as the device for joining the semiconductor element 7. As the material of the first holding portion 6, a substance having good wettability with the first joint portion 8, for example, an aluminum alloy, a copper alloy, gold, or tin can be used. Further, the surface of the first holding portion 6 may be made of a material having good wettability with the first joining portion 8 or plated. With such a configuration, the first holding portion 6 forms an alloy layer at the contact interface with the first joining portion 8.
　絶縁基板２の上面側の金属層２１と半導体素子７とは電流が流れる部位（部材）であるため、第一保持部６の設置個所は、絶縁基板２の上面側の金属層２１と半導体素子７との間の絶縁距離が保たれるように配置される。例えば、第一保持部６の最も高い部分が半導体素子７の表面の位置よりも低くなるように設定される。 Since the metal layer 21 on the upper surface side of the insulating substrate 2 and the semiconductor element 7 are portions (members) through which current flows, the installation location of the first holding portion 6 is the metal layer 21 on the upper surface side of the insulating substrate 2 and the semiconductor element. It is arranged so that the insulation distance from 7 is maintained. For example, the highest portion of the first holding portion 6 is set to be lower than the position of the surface of the semiconductor element 7.
　図５は、実施の形態１における半導体装置の接合部を示す断面構造模式図である。図６は、実施の形態１における半導体装置の接合部を示す断面構造模式図である。図７は、実施の形態１における半導体装置の他の接合部を示す断面構造模式図である。図８は、実施の形態１における半導体装置の他の接合部を示す断面構造模式図である。図９は、実施の形態１における半導体装置の他の接合部を示す平面構造模式図である。図１０は、実施の形態１における半導体装置の他の接合部を示す断面構造模式図である。図１１は、実施の形態１における半導体装置の他の接合部を示す断面構造模式図である。図１２は、実施の形態１における半導体装置の他の接合部を示す平面構造模式図である。図５、図７、図９は第一接合部８の接合前の断面構造図である。図６、図８、図１０は、第一接合部８の接合後の断面構造図である。 FIG. 5 is a schematic cross-sectional structure showing a joint portion of the semiconductor device according to the first embodiment. FIG. 6 is a schematic cross-sectional structure diagram showing a joint portion of the semiconductor device according to the first embodiment. FIG. 7 is a schematic cross-sectional structure showing another joint portion of the semiconductor device according to the first embodiment. FIG. 8 is a schematic cross-sectional structure showing another joint portion of the semiconductor device according to the first embodiment. FIG. 9 is a schematic plan view showing another joint portion of the semiconductor device according to the first embodiment. FIG. 10 is a schematic cross-sectional structure showing another joint portion of the semiconductor device according to the first embodiment. FIG. 11 is a schematic cross-sectional structure showing another joint portion of the semiconductor device according to the first embodiment. FIG. 12 is a schematic plan view showing another joint portion of the semiconductor device according to the first embodiment. 5, FIG. 7, and FIG. 9 are cross-sectional structural views of the first joint portion 8 before joining. 6, FIG. 8 and FIG. 10 are cross-sectional structural views of the first joint portion 8 after joining.
　図５、図６、図７、図８は、第一保持部６としてボンディングワイヤを用いた場合である。図５、図６においては、第一内部保持部６１は、半導体素子７の外周に対応する領域までは絶縁基板２の上面側の金属層２１の上面上に接するように平坦部を形成して配置する。第一外部保持部６２は、半導体素子７の外周よりも外側の領域でループ部を形成して金属層２１の上面にボンディングすることで形成して配置している（図５参照）。第一内部保持部６１の平坦部上に第一接合部８と半導体素子７とを重ねて配置する。第一接合部８と半導体素子７とを第一保持部６の第一内部保持部６１上に配置後、熱処理を行うことで第一接合部８を溶融して、絶縁基板２の上面側の金属層２１の上面と半導体素子７の下面とを接合する（図６参照）。第一外部保持部６２のループ部の高さは、第一接合部８で半導体素子７を接合後に、半導体素子７の外周側面と接する高さである。第一外部保持部６２のループ部が、半導体素子７の外周側面と接して配置されることで、第一接合部８での半導体素子７の接合時の半導体素子７の位置決めを行うことができる。 5, FIG. 6, FIG. 7, and FIG. 8 show the case where the bonding wire is used as the first holding portion 6. In FIGS. 5 and 6, the first internal holding portion 61 forms a flat portion so as to be in contact with the upper surface of the metal layer 21 on the upper surface side of the insulating substrate 2 up to the region corresponding to the outer periphery of the semiconductor element 7. Deploy. The first external holding portion 62 is formed and arranged by forming a loop portion in a region outside the outer periphery of the semiconductor element 7 and bonding it to the upper surface of the metal layer 21 (see FIG. 5). The first joint portion 8 and the semiconductor element 7 are arranged on the flat portion of the first internal holding portion 61 so as to be overlapped with each other. After arranging the first joint portion 8 and the semiconductor element 7 on the first internal holding portion 61 of the first holding portion 6, heat treatment is performed to melt the first joint portion 8 and to melt the first joint portion 8 on the upper surface side of the insulating substrate 2. The upper surface of the metal layer 21 and the lower surface of the semiconductor element 7 are joined (see FIG. 6). The height of the loop portion of the first external holding portion 62 is the height at which the semiconductor element 7 is in contact with the outer peripheral side surface of the semiconductor element 7 after being joined by the first joining portion 8. By arranging the loop portion of the first external holding portion 62 in contact with the outer peripheral side surface of the semiconductor element 7, the semiconductor element 7 can be positioned at the time of joining the semiconductor element 7 at the first joining portion 8. ..
　また、第一内部保持部６１の直径（高さ）によって、第一接合部８の厚さを調整、制御することができる。さらに、第一保持部６を半導体素子７の角部で、半導体素子７の外形よりも内側から外側に亘って配置することで、第一接合部８での接合形成時に、第一接合部８が第一保持部６に沿って半導体素子７の外形の内側から外側へ濡れ広がることで、第一外部保持部６２の周囲に第一接合部８のフィレット部が形成される（図６参照）。半導体素子７の角部の側面にフィレット部８１が形成されたことで、半導体素子７の角部での応力緩和ができ、半導体装置１００の信頼性を向上することができる。 Further, the thickness of the first joint portion 8 can be adjusted and controlled by the diameter (height) of the first internal holding portion 61. Further, by arranging the first holding portion 6 at the corner portion of the semiconductor element 7 from the inside to the outside of the outer shape of the semiconductor element 7, the first joint portion 8 is formed when the first joint portion 8 is formed. Spreads wet and spreads from the inside to the outside of the outer shape of the semiconductor element 7 along the first holding portion 6, so that a fillet portion of the first joining portion 8 is formed around the first outer holding portion 62 (see FIG. 6). .. Since the fillet portion 81 is formed on the side surface of the corner portion of the semiconductor element 7, stress relaxation at the corner portion of the semiconductor element 7 can be performed, and the reliability of the semiconductor device 100 can be improved.
　図７、図８においては、第一内部保持部６１は、半導体素子７の外周に対応する領域までは絶縁基板２の上面側の金属層２１の上面上に接するようにループ部を形成して配置し、第一外部保持部６２は、半導体素子７の外周よりも外側の上面側の金属層２１の上面上の領域でループ部を形成して金属層２１の上面にボンディングすることで形成している。図５、図６に示した第一保持部６とは、第一内部保持部６１の形状が異なる。例えば、第一接合部８の厚みを第一内部保持部６１の直径よりも厚くしたい場合、あるいは、第一内部保持部６１として、直径の小さいボンディングワイヤを用いて形成する場合に適用できる。このような構成においても、図５、図６の場合と同様に第一保持部６の厚み規定、半導体素子７の支持および位置決めを行うことができる。 In FIGS. 7 and 8, the first internal holding portion 61 forms a loop portion so as to be in contact with the upper surface of the metal layer 21 on the upper surface side of the insulating substrate 2 up to the region corresponding to the outer periphery of the semiconductor element 7. The first external holding portion 62 is formed by forming a loop portion in a region on the upper surface of the metal layer 21 on the upper surface side outside the outer periphery of the semiconductor element 7 and bonding to the upper surface of the metal layer 21. ing. The shape of the first internal holding portion 61 is different from that of the first holding portion 6 shown in FIGS. 5 and 6. For example, it can be applied when the thickness of the first joint portion 8 is desired to be thicker than the diameter of the first internal holding portion 61, or when the first internal holding portion 61 is formed by using a bonding wire having a small diameter. Even in such a configuration, the thickness of the first holding portion 6 can be specified, and the semiconductor element 7 can be supported and positioned as in the cases of FIGS. 5 and 6.
　図９、図１０においては、第一保持部６として、ブロック形状の部材を用いた場合である。ブロック形状の第一保持部６を用いて、例えば、第一保持部６を切り欠きくことで、第一内部保持部６１形成して半導体素子７の外形の角部へ配置して、第一保持部６の厚み規定、半導体素子７の支持および位置決めを行うことができる。 9 and 10 show a case where a block-shaped member is used as the first holding portion 6. Using the block-shaped first holding portion 6, for example, by cutting out the first holding portion 6, the first internal holding portion 61 is formed and arranged at the corner of the outer shape of the semiconductor element 7, and the first The thickness of the holding portion 6 can be specified, and the semiconductor element 7 can be supported and positioned.
　図１１、図１２においては、第一保持部６としては、図６、図８に示した形状のものを用いているが、図１１、図１２に示すように、第一外部保持部６２のループ部の一部が露出した形状においても同様の第一保持部６の厚みの規定、半導体素子７の支持および位置決めを行うことができる。図５から図１２においては、第一保持部６は、第一内部保持部６１と第一外部保持部６２とが半導体素子７の角部の内側から外側までの間で連続して形成されている。なお、第一内部保持部６１と第一外部保持部６２とが連続しておらず、別体として配置された場合においても、連続して一体的に配置された場合においても、同様の効果を得ることができる。 In FIGS. 11 and 12, the first holding portion 6 has the shape shown in FIGS. 6 and 8, but as shown in FIGS. 11 and 12, the first external holding portion 62 is used. Even in a shape in which a part of the loop portion is exposed, the thickness of the first holding portion 6 can be specified, and the semiconductor element 7 can be supported and positioned in the same manner. In FIGS. 5 to 12, in the first holding portion 6, the first internal holding portion 61 and the first external holding portion 62 are continuously formed from the inside to the outside of the corner portion of the semiconductor element 7. There is. It should be noted that the same effect can be obtained regardless of whether the first internal holding portion 61 and the first external holding portion 62 are not continuous and are arranged as separate bodies or continuously and integrally. Obtainable.
　図１３は、実施の形態１における半導体装置の他の保持部を示す平面構造模式図である。図において、半導体素子７の角部における第一保持部６の数が複数配置されている。このように、第一保持部６を半導体素子７の角部に複数配置することで、半導体素子７の角部頂点を複数の第一保持部６で挟むので、角部に１本の第一保持部６を配置した場合に比べて、半導体素子７の位置決めをより正確に行うこと（接合位置精度の向上）が可能となる。また、半導体素子７を安定して支持することができる。さらに、第一接合部８のフィレット部８１は、応力緩和のために十分な領域を確保することができる。なお、図１３に示すように、図４に示した場合等同様に、第一接合部８の角部とは、領域として、第一接合部８の角部頂点（辺の交点）から各辺の長さ（ａまたはｂ）の０.２５倍（１/４）の範囲までをいい、第一保持部６は、この範囲内に配置されていればよい。第一内部保持部６１の一端は、半導体素子７の角部よりも内側に配置され、第一内部保持部６１の他端は、第一内部保持部６１の一端よりも半導体素子７の角部側に配置される。 FIG. 13 is a schematic plan view showing another holding portion of the semiconductor device according to the first embodiment. In the figure, a plurality of numbers of the first holding portions 6 at the corner portions of the semiconductor element 7 are arranged. By arranging a plurality of the first holding portions 6 at the corner portions of the semiconductor element 7 in this way, the corner vertices of the semiconductor element 7 are sandwiched between the plurality of first holding portions 6, so that one first holding portion 6 is sandwiched between the corner portions. Compared with the case where the holding portion 6 is arranged, it is possible to more accurately position the semiconductor element 7 (improve the joining position accuracy). Further, the semiconductor element 7 can be stably supported. Further, the fillet portion 81 of the first joint portion 8 can secure a sufficient region for stress relaxation. As shown in FIG. 13, as in the case shown in FIG. 4, the corner portion of the first joint portion 8 is a region from the corner apex (intersection point of the sides) of the first joint portion 8 to each side. It means up to a range of 0.25 times (1/4) of the length (a or b) of, and the first holding portion 6 may be arranged within this range. One end of the first internal holding portion 61 is arranged inside the corner portion of the semiconductor element 7, and the other end of the first internal holding portion 61 is a corner portion of the semiconductor element 7 rather than one end of the first internal holding portion 61. Placed on the side.
　次に、上述のように構成された本実施の形態１の半導体装置１００の製造方法について説明する。 Next, a method of manufacturing the semiconductor device 100 of the first embodiment configured as described above will be described.
　はじめに、半導体装置１００の底面部となるベース板１を準備する（ベース板準備工程）。 First, the base plate 1 to be the bottom surface of the semiconductor device 100 is prepared (base plate preparation process).
　次に、表面に電極１３を有する半導体素子７を準備する（半導体素子準備工程）。 Next, a semiconductor element 7 having an electrode 13 on the surface is prepared (semiconductor element preparation step).
　次に、上面に金属層２１と下面とに金属層２３とを有する絶縁基板２を準備する（絶縁基板準備工程）。絶縁層２２と上面側の金属層２１、下面側の金属層２３との接合は、ロウ付けなどにより行う。上面側の金属層２１には、電気回路が形成されるため、パターン形状が異なることがよくある。このような場合、上面側の金属層２１、下面側の金属層２３の大きさ、厚みを調整することで、絶縁層２２の上下（おもて裏）面間で熱応力の発生を抑えるようにしてもよい。 Next, an insulating substrate 2 having a metal layer 21 on the upper surface and a metal layer 23 on the lower surface is prepared (insulation substrate preparation step). The insulating layer 22 is joined to the metal layer 21 on the upper surface side and the metal layer 23 on the lower surface side by brazing or the like. Since an electric circuit is formed on the metal layer 21 on the upper surface side, the pattern shape is often different. In such a case, by adjusting the size and thickness of the metal layer 21 on the upper surface side and the metal layer 23 on the lower surface side, it is possible to suppress the generation of thermal stress between the upper and lower (front and back) surfaces of the insulating layer 22. You may do it.
　次にベース板１の上面に絶縁基板２を第二接合部３で接合する（絶縁基板接合工程）。 Next, the insulating substrate 2 is bonded to the upper surface of the base plate 1 at the second bonding portion 3 (insulating substrate bonding process).
　次に、絶縁基板２の上面側の金属層２１の上面に第一保持部６に設置する（保持部設置工程）。第一保持部６がワイヤ、リボン、リードの場合、例えば超音波接合法で金属層２１の上面に接合する。第一保持部６の配置位置としては、第一保持部６の役割として、半導体素子７の位置決め機能を有していることから、半導体素子７が配置される予定の位置に配置される。 Next, the first holding portion 6 is installed on the upper surface of the metal layer 21 on the upper surface side of the insulating substrate 2 (holding portion installation process). When the first holding portion 6 is a wire, a ribbon, or a lead, it is joined to the upper surface of the metal layer 21 by, for example, an ultrasonic joining method. As for the arrangement position of the first holding portion 6, since the semiconductor element 7 has a positioning function as the role of the first holding portion 6, the semiconductor element 7 is arranged at a position where the semiconductor element 7 is planned to be arranged.
　次に、第一保持部６を第一接合部８と第二接合部３との少なくともいずれか一方に埋設し、第一保持部６が第一接合部８内に埋設される場合は半導体素子７の角部の対角方向で内側と外側とに配置し、第一保持部６が第二接合部３内に埋設される場合は絶縁基板２の下面の金属層２３の角部の対角方向で内側と外側とに配置する（保持部配置工程）。 Next, when the first holding portion 6 is embedded in at least one of the first joining portion 8 and the second joining portion 3, and the first holding portion 6 is embedded in the first joining portion 8, the semiconductor element 7 is arranged diagonally inside and outside, and when the first holding portion 6 is embedded in the second joint portion 3, the diagonal portion of the corner portion of the metal layer 23 on the lower surface of the insulating substrate 2 is diagonal. It is arranged inside and outside in the direction (holding part arrangement process).
　次に、半導体素子７と絶縁基板２の上面側の金属層２１とを配線部９を用いて電気的に接続する（配線部形成工程）。配線部９がボンディングワイヤ、リボン、リードの場合、超音波接合法で接合できる。なお、第一保持部６もボンディングワイヤ、リボン、リードの場合、配線部９の接合装置と同じ装置で接合できる場合がある。 Next, the semiconductor element 7 and the metal layer 21 on the upper surface side of the insulating substrate 2 are electrically connected using the wiring portion 9 (wiring portion forming step). When the wiring portion 9 is a bonding wire, ribbon, or lead, it can be bonded by an ultrasonic bonding method. In the case of a bonding wire, ribbon, or lead, the first holding portion 6 may also be bonded by the same device as the bonding device of the wiring portion 9.
　次に、絶縁基板２と半導体素子７とを封止部１０で封止する（封止工程）。 Next, the insulating substrate 2 and the semiconductor element 7 are sealed by the sealing portion 10 (sealing step).
　以上の主要な製造工程を経ることで、図１に示す半導体装置１００が製造できる。 The semiconductor device 100 shown in FIG. 1 can be manufactured by going through the above main manufacturing steps.
　なお、保持部６（第二保持部６）を第二接合部３内に埋設する場合は、ベース板１の上面に保持部６（第二保持部６）を設置後、第二接合部３を用いてベース板１と絶縁基板２とを接合する絶縁基板接合工程を実施すればよい。 When the holding portion 6 (second holding portion 6) is embedded in the second joint portion 3, the holding portion 6 (second holding portion 6) is installed on the upper surface of the base plate 1, and then the second joint portion 3 is installed. The insulating substrate joining step of joining the base plate 1 and the insulating substrate 2 may be carried out using the above.
　図１４は、実施の形態１における他の半導体装置を示す断面構造模式図である。図１４において、半導体装置１０１は、ベース板１と、絶縁基板２と、接合部である第一接合部８と、接合部である第二接合部３と、ケース部４と、保持部である第一保持部６と、半導体素子７と、配線部であるボンディングワイヤ９と、封止部１０と、電極端子１２と、を備えている。このように、ケース部４を備えた半導体装置１０１においても、第一保持部６を備えたことにより、半導体装置１００と同様の効果を得ることができる。 FIG. 14 is a schematic cross-sectional structure showing another semiconductor device according to the first embodiment. In FIG. 14, the semiconductor device 101 is a base plate 1, an insulating substrate 2, a first joining portion 8 which is a joining portion, a second joining portion 3 which is a joining portion, a case portion 4, and a holding portion. It includes a first holding portion 6, a semiconductor element 7, a bonding wire 9 which is a wiring portion, a sealing portion 10, and an electrode terminal 12. As described above, even in the semiconductor device 101 provided with the case portion 4, the same effect as that of the semiconductor device 100 can be obtained by providing the first holding portion 6.
　また、半導体装置１００の製造方法において、ケース部４をベース板１の上面に配置するケース部配置工程を実施することで、半導体装置１０１を製造することができる。 Further, in the manufacturing method of the semiconductor device 100, the semiconductor device 101 can be manufactured by carrying out the case section arranging step of arranging the case section 4 on the upper surface of the base plate 1.
　以上のように構成された半導体装置１００，１０１においては、第一保持部６を、第一接合部８内に埋設し、第一接合部８の角部の内側と外側とに設置したので、第一接合部８の厚みの設計値からのずれを低減し、接合不良を改善し、半導体装置の信頼性を向上させることができる。 In the semiconductor devices 100 and 101 configured as described above, the first holding portion 6 is embedded in the first joining portion 8 and installed inside and outside the corner portion of the first joining portion 8. It is possible to reduce the deviation of the thickness of the first joint portion 8 from the design value, improve the joint defect, and improve the reliability of the semiconductor device.
　また、第一保持部６を、第一接合部８内に埋設し、第一接合部８の角部の内側と外側とに設置したので、半導体素子７の接合位置のずれを低減することができる。 Further, since the first holding portion 6 is embedded in the first joining portion 8 and installed inside and outside the corner portion of the first joining portion 8, it is possible to reduce the deviation of the joining position of the semiconductor element 7. can.
　さらに、第一接合部８の厚みを第一保持部６の第一接合部８の内側に存在する部分の高さは、第一接合部８の外側に存在する部分の高さに比べて低い。これによって、半導体素子７の接合位置のずれを低減することができる。 Further, the height of the portion where the thickness of the first joint portion 8 exists inside the first joint portion 8 of the first holding portion 6 is lower than the height of the portion existing outside the first joint portion 8. .. This makes it possible to reduce the deviation of the bonding position of the semiconductor element 7.
　また、第一保持部６を、第一接合部８内に埋設し、第一接合部８の角部の内側と外側とに設置したので、半導体素子７の裏面の角部まで確実に第一接合部８が接合される（濡れ広がる）ことで、接合不良を改善することができる。 Further, since the first holding portion 6 is embedded in the first joining portion 8 and installed inside and outside the corner portion of the first joining portion 8, the first holding portion 6 is surely first up to the corner portion on the back surface of the semiconductor element 7. By joining (wetting and spreading) the joint portion 8, it is possible to improve the joint defect.
　さらに、第一保持部６を、第一接合部８内に埋設し、第一接合部８の角部の内側と外側とに設置したので、第一接合部８が第一保持部６で濡れ広がることで、半導体素子７の角部の側面にフィレットが形成され、半導体素子７の角部での応力を低減することができる。 Further, since the first holding portion 6 is embedded in the first joining portion 8 and installed inside and outside the corner portion of the first joining portion 8, the first joining portion 8 gets wet with the first holding portion 6. By expanding, fillets are formed on the side surfaces of the corners of the semiconductor element 7, and the stress at the corners of the semiconductor element 7 can be reduced.
　また、第一保持部６として、第一接合部８内に埋設し、第一接合部８と濡れ性のよい材料を用いたので、接合状態が改善され、半導体素子７からの放熱性が改善できる。 Further, since the first holding portion 6 is embedded in the first joint portion 8 and a material having good wettability with the first joint portion 8 is used, the joint state is improved and the heat dissipation from the semiconductor element 7 is improved. can.
実施の形態２．
　本実施の形態２においては、実施の形態１で用いた第一保持部６に加えて第三保持部６３を半導体素子７の表面の電極１３（と配線部９との接合部）に対応する半導体素子７の裏面の位置にも配置した点で異なる。このように、半導体素子７の表面の電極１３に対応する半導体素子７の裏面にも第三保持部６３を配置したので、半導体素子７で発生した熱を第三保持部６３を通じて拡散することができる。その結果、半導体素子７からの放熱性の向上が可能となり、半導体装置２００の信頼性を向上することができる。なお、その他の点については、実施の形態１と同様であるので、詳しい説明は省略する。 Embodiment 2.
In the second embodiment, in addition to the first holding portion 6 used in the first embodiment, the third holding portion 63 corresponds to the electrode 13 (the joint portion between the wiring portion 9 and the wiring portion 9) on the surface of the semiconductor element 7. It differs in that it is also arranged at the position on the back surface of the semiconductor element 7. In this way, since the third holding portion 63 is also arranged on the back surface of the semiconductor element 7 corresponding to the electrode 13 on the front surface of the semiconductor element 7, the heat generated by the semiconductor element 7 can be diffused through the third holding portion 63. can. As a result, the heat dissipation from the semiconductor element 7 can be improved, and the reliability of the semiconductor device 200 can be improved. Since other points are the same as those in the first embodiment, detailed description thereof will be omitted.
　図１５は、実施の形態２における半導体装置を示す平面構造模式図である。図１６は、実施の形態２における半導体装置を示す断面構造模式図である。図１７は、実施の形態２における半導体装置を示す他の断面構造模式図である。図１８は、実施の形態２における半導体装置の保持部を示す平面構造模式図である。図１６は、図１の一点鎖線ＣＣにおける断面構造模式図である。図１７は、図１の一点鎖線ＤＤにおける断面構造模式図である。図１８は、第二接合部３を透過して、第一保持部６および第三保持部６３の配置を上面から見た平面構造模式図である。 FIG. 15 is a schematic plan structure diagram showing the semiconductor device according to the second embodiment. FIG. 16 is a schematic cross-sectional structure diagram showing the semiconductor device according to the second embodiment. FIG. 17 is another schematic cross-sectional structure showing the semiconductor device according to the second embodiment. FIG. 18 is a schematic plan view showing a holding portion of the semiconductor device according to the second embodiment. FIG. 16 is a schematic cross-sectional structure of the alternate long and short dash line CC of FIG. FIG. 17 is a schematic cross-sectional structure of the alternate long and short dash line DD of FIG. FIG. 18 is a schematic plan view of the arrangement of the first holding portion 6 and the third holding portion 63 as viewed from above through the second joint portion 3.
　図において、半導体装置２００は、ベース板１と、絶縁基板２と、接合部である第一接合部８と、接合部である第二接合部３と、保持部である第一保持部６と、保持部である第三保持部６３と、半導体素子７と、配線部であるボンディングワイヤ９と、封止部１０と、電極端子１２と、を備えている。 In the figure, the semiconductor device 200 includes a base plate 1, an insulating substrate 2, a first joining portion 8 which is a joining portion, a second joining portion 3 which is a joining portion, and a first holding portion 6 which is a holding portion. A third holding portion 63, which is a holding portion, a semiconductor element 7, a bonding wire 9 which is a wiring portion, a sealing portion 10, and an electrode terminal 12 are provided.
　図１５において、第三保持部６３は、点線にて示している。半導体素子７の表面の電極１３の外形よりも内側に第三保持部６３が配置されている。第三保持部６３は、半導体素子７の表面の電極１３の配置位置に対応する半導体素子７の裏面の位置に配置される。特に、半導体素子７の表面の電極１３のボンディングワイヤ９が接合された箇所を含んだ半導体素子７の裏面の対応する位置に配置される。このように配置することで、半導体装置１００（半導体素子７）の動作時に発生する熱を発熱箇所から効率的に放熱することができる。 In FIG. 15, the third holding portion 63 is shown by a dotted line. The third holding portion 63 is arranged inside the outer shape of the electrode 13 on the surface of the semiconductor element 7. The third holding portion 63 is arranged at a position on the back surface of the semiconductor element 7 corresponding to the arrangement position of the electrode 13 on the front surface of the semiconductor element 7. In particular, it is arranged at the corresponding position on the back surface of the semiconductor element 7 including the portion where the bonding wire 9 of the electrode 13 on the surface of the semiconductor element 7 is bonded. By arranging in this way, the heat generated during the operation of the semiconductor device 100 (semiconductor element 7) can be efficiently dissipated from the heat generating portion.
　図１６、図１７において、第三保持部６３の厚さ（高さ）は、第一内部保持部の厚さ（高さ）と同等の厚さである。半導体素子７は、第一内部保持部６１と第三保持部６３とで支持（保持）される。 In FIGS. 16 and 17, the thickness (height) of the third holding portion 63 is the same as the thickness (height) of the first internal holding portion. The semiconductor element 7 is supported (held) by the first internal holding portion 61 and the third holding portion 63.
　図１８において、第一内部保持部６１の一端は、半導体素子７の角部よりも内側に配置され、第一内部保持部６１の他端は、第一内部保持部６１の一端よりも半導体素子７の角部側に配置される。第三保持部６３は、半導体素子７の角部（四隅）に配置された第一内部保持部６１の一端よりも半導体素子７の中央部寄りに配置されている。 In FIG. 18, one end of the first internal holding portion 61 is arranged inside the corner portion of the semiconductor element 7, and the other end of the first internal holding portion 61 is a semiconductor element rather than one end of the first internal holding portion 61. It is arranged on the corner side of 7. The third holding portion 63 is arranged closer to the center of the semiconductor element 7 than one end of the first internal holding portion 61 arranged at the corners (four corners) of the semiconductor element 7.
　なお、第一保持部６としては、実施の形態１で用いたいずれの形態でも同様に適用できる。 The first holding portion 6 can be similarly applied to any of the embodiments used in the first embodiment.
　以上のように構成された半導体装置２００においては、第一保持部６を、第一接合部８内に埋設し、第一接合部８の角部の内側と外側とに設置したので、第一接合部８の厚みの設計値からのずれを低減し、接合不良を改善し、半導体装置の信頼性を向上させることができる。 In the semiconductor device 200 configured as described above, the first holding portion 6 is embedded in the first joint portion 8 and installed inside and outside the corner portion of the first joint portion 8, so that the first It is possible to reduce the deviation of the thickness of the joint portion 8 from the design value, improve the joint defect, and improve the reliability of the semiconductor device.
　また、第一保持部６を、第一接合部８内に埋設し、第一接合部８の角部の内側と外側とに設置したので、半導体素子７の接合位置のずれを低減することができる。 Further, since the first holding portion 6 is embedded in the first joining portion 8 and installed inside and outside the corner portion of the first joining portion 8, it is possible to reduce the deviation of the joining position of the semiconductor element 7. can.
　さらに、第一接合部８の厚みを第一保持部６の第一接合部８の内側に存在する部分の高さは、第一接合部８の外側に存在する部分の高さに比べて低い。これによって、半導体素子７の接合位置のずれを低減することができる。 Further, the height of the portion where the thickness of the first joint portion 8 exists inside the first joint portion 8 of the first holding portion 6 is lower than the height of the portion existing outside the first joint portion 8. .. This makes it possible to reduce the deviation of the bonding position of the semiconductor element 7.
　また、第一保持部６を、第一接合部８内に埋設し、第一接合部８の角部の内側と外側とに設置したので、半導体素子７の裏面の角部まで確実に第一接合部８が接合される（濡れ広がる）ことで、接合不良を改善することができる。 Further, since the first holding portion 6 is embedded in the first joining portion 8 and installed inside and outside the corner portion of the first joining portion 8, the first holding portion 6 is surely first up to the corner portion on the back surface of the semiconductor element 7. By joining (wetting and spreading) the joint portion 8, it is possible to improve the joint defect.
　さらに、第一保持部６を、第一接合部８内に埋設し、第一接合部８の角部の内側と外側とに設置したので、第一接合部８が保持部６で濡れ広がることで、半導体素子７の角部の側面にフィレットが形成され、半導体素子７の角部での応力を低減することができる。 Further, since the first holding portion 6 is embedded in the first joining portion 8 and installed inside and outside the corner portion of the first joining portion 8, the first joining portion 8 gets wet and spreads in the holding portion 6. Therefore, fillets are formed on the side surfaces of the corners of the semiconductor element 7, and the stress at the corners of the semiconductor element 7 can be reduced.
　また、第一保持部６として、第一接合部８と濡れ性のよい材料を用いたので、接合状態が改善され、半導体素子７からの放熱性が改善できる。 Further, since the material having good wettability with the first joint portion 8 is used as the first holding portion 6, the joint state can be improved and the heat dissipation from the semiconductor element 7 can be improved.
　さらに、第三保持部６３を、半導体素子７の表面の電極１３に対応する半導体素子７の裏面側に配置したので、半導体素子７での発熱を効率よく放熱でき、半導体装置の信頼性を向上することができる。 Further, since the third holding portion 63 is arranged on the back surface side of the semiconductor element 7 corresponding to the electrode 13 on the front surface of the semiconductor element 7, the heat generated by the semiconductor element 7 can be efficiently dissipated, and the reliability of the semiconductor device is improved. can do.
実施の形態３．
　本実施の形態３においては、実施の形態１で用いた第一保持部６を第二保持部６として第二接合部３内に埋設し、絶縁基板２の下面側の金属層２３の角部の内側から外側に配置した点で異なる。このように、第二保持部６を第二接合部３内に埋設し、絶縁基板２の下面側の金属層２３の角部の内側から外側に配置したので、絶縁基板２のベース板１への接合時の接合不良を低減することができる。その結果、絶縁基板２からの放熱性の向上が可能となり、半導体装置３００の信頼性を向上することができる。なお、その他の点については、実施の形態１と同様であるので、詳しい説明は省略する。 Embodiment 3.
In the third embodiment, the first holding portion 6 used in the first embodiment is embedded in the second joint portion 3 as the second holding portion 6, and the corner portion of the metal layer 23 on the lower surface side of the insulating substrate 2 is embedded. It differs in that it is placed from the inside to the outside of. In this way, the second holding portion 6 is embedded in the second joint portion 3 and arranged from the inside to the outside of the corner portion of the metal layer 23 on the lower surface side of the insulating substrate 2, so that the second holding portion 6 is placed on the base plate 1 of the insulating substrate 2. It is possible to reduce the joining failure at the time of joining. As a result, the heat dissipation from the insulating substrate 2 can be improved, and the reliability of the semiconductor device 300 can be improved. Since other points are the same as those in the first embodiment, detailed description thereof will be omitted.
　図１９は、実施の形態３における半導体装置を示す平面構造模式図である。図２０は、実施の形態３における半導体装置を示す断面構造模式図である。図２１は、実施の形態３における半導体装置を示す他の断面構造模式図である。図２２は、実施の形態３における半導体装置の保持部を示す平面構造模式図である。図２０は、図１の一点鎖線ＥＥにおける断面構造模式図である。図２１は、図１の一点鎖線ＦＦにおける断面構造模式図である。図２２は、第二接合部３を透過して、第二保持部６の配置を上面から見た平面構造模式図である。 FIG. 19 is a schematic plan structure diagram showing the semiconductor device according to the third embodiment. FIG. 20 is a schematic cross-sectional structure diagram showing the semiconductor device according to the third embodiment. FIG. 21 is another schematic cross-sectional structure showing the semiconductor device according to the third embodiment. FIG. 22 is a schematic plan view showing a holding portion of the semiconductor device according to the third embodiment. FIG. 20 is a schematic cross-sectional structure of the alternate long and short dash line EE of FIG. FIG. 21 is a schematic cross-sectional structure of the alternate long and short dash line FF of FIG. FIG. 22 is a schematic plan view of the arrangement of the second holding portion 6 as viewed from above through the second joint portion 3.
　図において、半導体装置３００は、ベース板１と、絶縁基板２と、接合部である第一接合部８と、接合部である第二接合部３と、保持部である第二保持部６と、半導体素子７と、配線部であるボンディングワイヤ９と、封止部１０と、電極端子１２と、を備えている。 In the figure, the semiconductor device 300 includes a base plate 1, an insulating substrate 2, a first joining portion 8 which is a joining portion, a second joining portion 3 which is a joining portion, and a second holding portion 6 which is a holding portion. , A semiconductor element 7, a bonding wire 9 which is a wiring portion, a sealing portion 10, and an electrode terminal 12.
　図において、半導体装置３００は、ベース板１の上面と絶縁基板２の下面とを第二接合部３を用いて接合している。絶縁基板２の上面と半導体素子７の裏面とを第一接合部８を用いて接合している。絶縁基板２の下面側の金属層２３とベース板１の上面とを接合する第二接合部３には、絶縁基板２の下面側の金属層２３の角部の対角方向へ向いて内側と外側に配置された第二保持部６が埋設されている。絶縁基板２と絶縁基板２の上面に接合された半導体素子７とは、封止部１０内に封止されている。 In the figure, in the semiconductor device 300, the upper surface of the base plate 1 and the lower surface of the insulating substrate 2 are joined by using the second joining portion 3. The upper surface of the insulating substrate 2 and the back surface of the semiconductor element 7 are bonded using the first bonding portion 8. The second joint portion 3 that joins the metal layer 23 on the lower surface side of the insulating substrate 2 and the upper surface of the base plate 1 has an inner side facing diagonally from the corner portion of the metal layer 23 on the lower surface side of the insulating substrate 2. The second holding portion 6 arranged on the outside is buried. The insulating substrate 2 and the semiconductor element 7 bonded to the upper surface of the insulating substrate 2 are sealed in the sealing portion 10.
　図１９において、封止部１０は、点線にて表示し、封止部１０に封止されている部材の位置関係がわかるようにしている。半導体装置３００の最外周は、ベース板１の周縁部である。ベース板１の周縁部よりも内側には、封止部１０が配置されている。封止部１０の外縁よりも内側には、絶縁基板２の絶縁層２２が配置されている。絶縁基板２の絶縁層２２の外縁よりも内側には、絶縁基板２の上面側の金属層２１が配置されている。絶縁基板２の上面側の金属層２１の外縁よりも内側には、電極１３が上面に形成された半導体素子７が配置されている。絶縁基板２の下面側の金属層２３の角部（四隅）には、第二接合部３が角部からはみ出して配置されている。電極端子１２は、絶縁基板２を跨いで配置され、封止部１０から突出（露出）している。 In FIG. 19, the sealing portion 10 is indicated by a dotted line so that the positional relationship of the members sealed in the sealing portion 10 can be understood. The outermost circumference of the semiconductor device 300 is the peripheral edge of the base plate 1. The sealing portion 10 is arranged inside the peripheral portion of the base plate 1. The insulating layer 22 of the insulating substrate 2 is arranged inside the outer edge of the sealing portion 10. The metal layer 21 on the upper surface side of the insulating substrate 2 is arranged inside the outer edge of the insulating layer 22 of the insulating substrate 2. A semiconductor element 7 having an electrode 13 formed on the upper surface is arranged inside the outer edge of the metal layer 21 on the upper surface side of the insulating substrate 2. At the corners (four corners) of the metal layer 23 on the lower surface side of the insulating substrate 2, the second joint 3 is arranged so as to protrude from the corners. The electrode terminal 12 is arranged so as to straddle the insulating substrate 2 and protrudes (exposed) from the sealing portion 10.
　図２０は、絶縁基板２（半導体素子７）の対面方向の断面構造模式図である。図２０において、ベース板１の上面と絶縁基板２の下面側の金属層２３の下面とを第二接合部３を用いて接合している。絶縁基板２の上面側の金属層２１の上面と半導体素子７の裏面とを第一接合部８を用いて接合している。ボンディングワイヤ９は、半導体素子７の表面の電極１３と電極端子１２とを電気的に接続している。また、ボンディングワイヤ９は、絶縁基板２の上面側の金属層２１の所定の位置と電極端子１２とを電気的に接続している。封止部１０は、絶縁基板２の下側の金属層２３と接合していない（露出した）ベース板１の上面と接して、絶縁基板２と絶縁基板２の上面に接合された半導体素子７とを封止している。電極端子１２は、絶縁基板２の上部で、一端側が封止部１０内に配置され、他端が封止部１０の側面から露出（突出）して配置される。 FIG. 20 is a schematic cross-sectional structure of the insulating substrate 2 (semiconductor element 7) in the facing direction. In FIG. 20, the upper surface of the base plate 1 and the lower surface of the metal layer 23 on the lower surface side of the insulating substrate 2 are joined by using the second joining portion 3. The upper surface of the metal layer 21 on the upper surface side of the insulating substrate 2 and the back surface of the semiconductor element 7 are bonded by using the first bonding portion 8. The bonding wire 9 electrically connects the electrode 13 on the surface of the semiconductor element 7 and the electrode terminal 12. Further, the bonding wire 9 electrically connects the predetermined position of the metal layer 21 on the upper surface side of the insulating substrate 2 and the electrode terminal 12. The sealing portion 10 is in contact with the upper surface of the base plate 1 that is not bonded (exposed) to the metal layer 23 below the insulating substrate 2, and the semiconductor element 7 is bonded to the insulating substrate 2 and the upper surface of the insulating substrate 2. And is sealed. The electrode terminal 12 is arranged on the upper part of the insulating substrate 2, one end side being arranged in the sealing portion 10, and the other end being exposed (protruding) from the side surface of the sealing portion 10.
　図２１は、絶縁基板２（半導体素子７）の対角方向の断面構造模式図である。図２１において、絶縁基板２の下面側の金属層２３の角部には、対角方向に対して（向かって）第二保持部６が配置されている。第二接合部３内に埋設される保持部６が、第二保持部６である。第二保持部６は、絶縁基板２の下面側の金属層２３の外周部よりも内側に配置される第二内部保持部６４と、絶縁基板２の下面側の金属層２３の外周部よりも外側に配置される第二外部保持部６５とを有している。第二保持部６は、絶縁基板２の下面側の金属層２３の角部の内側から外側に配置され、第二接合部３の中に埋設されている。第二外部保持部６５のループ部の高さは、第二接合部３で絶縁基板２を接合後に、絶縁基板２の下面側の金属層２３の外周側面と接する高さである。第二外部保持部６５のループ部が、絶縁基板２の下面側の金属層２３の外周側面と接して配置されることで、第二接合部３での絶縁基板２の接合時の絶縁基板２の位置決めを行うことができる。図２１、図２２においては、第二保持部６は、第二内部保持部６４と第二外部保持部６５とが絶縁基板２の下側の金属層２３の角部の内側から外側までの間で連続して一体的に形成されている。なお、第二内部保持部６４と第二外部保持部６５とが連続しておらず、別体として配置された場合においても、連続して一体的に配置された場合においても、同様の効果を得ることができる。 FIG. 21 is a schematic cross-sectional structure diagram of the insulating substrate 2 (semiconductor element 7) in the diagonal direction. In FIG. 21, a second holding portion 6 is arranged diagonally (toward) at a corner portion of the metal layer 23 on the lower surface side of the insulating substrate 2. The holding portion 6 embedded in the second joint portion 3 is the second holding portion 6. The second holding portion 6 is located inside the outer peripheral portion of the metal layer 23 on the lower surface side of the insulating substrate 2 and the outer peripheral portion of the metal layer 23 on the lower surface side of the insulating substrate 2. It has a second external holding portion 65 arranged on the outside. The second holding portion 6 is arranged from the inside to the outside of the corner portion of the metal layer 23 on the lower surface side of the insulating substrate 2, and is embedded in the second joint portion 3. The height of the loop portion of the second external holding portion 65 is the height at which the insulating substrate 2 is in contact with the outer peripheral side surface of the metal layer 23 on the lower surface side of the insulating substrate 2 after the insulating substrate 2 is bonded at the second bonding portion 3. The loop portion of the second external holding portion 65 is arranged in contact with the outer peripheral side surface of the metal layer 23 on the lower surface side of the insulating substrate 2, so that the insulating substrate 2 at the time of joining the insulating substrate 2 at the second joining portion 3 is arranged. Can be positioned. In FIGS. 21 and 22, in the second holding portion 6, between the second internal holding portion 64 and the second external holding portion 65 from the inside to the outside of the corner portion of the lower metal layer 23 of the insulating substrate 2. It is continuously and integrally formed. It should be noted that the same effect can be obtained regardless of whether the second internal holding portion 64 and the second external holding portion 65 are not continuous and are arranged as separate bodies or continuously and integrally. Obtainable.
　図２２は、第二接合部３の内部を透過して上面視した図である。図２２において、ベース板１の上面には、第二接合部３が配置されている。第二接合部３は、絶縁基板２の下面側の金属層２３の下面と接合し、絶縁基板２の下面側の金属層２３の外形(外縁)よりも外側にはみ出した（突出した）第二接合部３のフィレット部３１を有している。第二接合部３の角部（絶縁基板２の下面側の金属層２３の角部と同等）には、絶縁基板２の下面側の金属層２３の投影面の内側から外側の間に第二保持部６が第二接合部３の中に埋設されて配置されている。第二保持部６は、絶縁基板２の下面側の金属層２３の投影面よりも内側には、第二内部保持部６４が配置され、第二接合部３のフィレット部３１には、第二外部保持部６５が配置されている。なお、第二接合部３の角部とは、領域として、第二接合部３の角部頂点（辺の交点）から各辺の長さ（ａまたはｂ）の０.２５倍（１/４）の範囲までをいい、この範囲内に第二保持部６が配置されていればよい。第二内部保持部６４の一端は、絶縁基板２の下面側の金属層２３の角部よりも内側に配置され、第二内部保持部６４の他端は、第二内部保持部６４の一端よりも絶縁基板２の下面側の金属層２３の角部側に配置される。なお、図１３のように第二保持部６を複数配置しても同様の効果が得られる。 FIG. 22 is a top view of the inside of the second joint portion 3 through the inside. In FIG. 22, the second joint portion 3 is arranged on the upper surface of the base plate 1. The second joint portion 3 is joined to the lower surface of the metal layer 23 on the lower surface side of the insulating substrate 2, and protrudes (protrudes) from the outer shape (outer edge) of the metal layer 23 on the lower surface side of the insulating substrate 2. It has a fillet portion 31 of a joint portion 3. At the corners of the second joint 3 (equivalent to the corners of the metal layer 23 on the lower surface side of the insulating substrate 2), a second portion is formed between the inside and the outside of the projection surface of the metal layer 23 on the lower surface side of the insulating substrate 2. The holding portion 6 is embedded and arranged in the second joint portion 3. In the second holding portion 6, the second internal holding portion 64 is arranged inside the projection surface of the metal layer 23 on the lower surface side of the insulating substrate 2, and the fillet portion 31 of the second joint portion 3 has a second holding portion 6. The external holding portion 65 is arranged. The corner of the second joint 3 is 0.25 times (1/4) the length (a or b) of each side from the corner apex (intersection of the sides) of the second joint 3 as a region. ), And it is sufficient that the second holding portion 6 is arranged within this range. One end of the second internal holding portion 64 is arranged inside the corner portion of the metal layer 23 on the lower surface side of the insulating substrate 2, and the other end of the second internal holding portion 64 is from one end of the second internal holding portion 64. Is also arranged on the corner side of the metal layer 23 on the lower surface side of the insulating substrate 2. The same effect can be obtained by arranging a plurality of second holding portions 6 as shown in FIG.
　第二保持部６は、絶縁基板２の下面側の金属層２３の下面の角部まで確実に第二接合部３が接合される（濡れ広がる）ように第二接合部３を誘導するためのものである。第二保持部６は、第二接合部３の内側と外側に配置（絶縁基板２の下面側の金属層２３の外形の内側と外側に配置）されていている。第二接合部３の上面は、絶縁基板２の下面側の金属層２３の下面に接触(接合)している。第二接合部３の下面は、ベース板１の上面に接触（接合）している。絶縁基板２の下面側の金属層２３の外形より内側に存在する部分である第二内部保持部６４の高さは、絶縁基板２の下面側の金属層２３の外形よりも外側に存在する部分である第二外部保持部６５の高さに比べて低い。これにより、絶縁基板２の下面側の金属層２３とベース板１との接合時の絶縁基板２（絶縁基板２の下面側の金属層２３）の接合位置のずれを低減することができる。 The second holding portion 6 is for guiding the second joint portion 3 so that the second joint portion 3 is surely bonded (wet and spreads) to the corner portion of the lower surface of the metal layer 23 on the lower surface side of the insulating substrate 2. It is a thing. The second holding portion 6 is arranged inside and outside the second joint portion 3 (arranged inside and outside the outer shape of the metal layer 23 on the lower surface side of the insulating substrate 2). The upper surface of the second bonding portion 3 is in contact (bonding) with the lower surface of the metal layer 23 on the lower surface side of the insulating substrate 2. The lower surface of the second joint portion 3 is in contact with (joins) the upper surface of the base plate 1. The height of the second internal holding portion 64, which is a portion existing inside the outer shape of the metal layer 23 on the lower surface side of the insulating substrate 2, is a portion existing outside the outer shape of the metal layer 23 on the lower surface side of the insulating substrate 2. It is lower than the height of the second external holding portion 65. As a result, it is possible to reduce the deviation of the joining position of the insulating substrate 2 (the metal layer 23 on the lower surface side of the insulating substrate 2) at the time of joining the metal layer 23 on the lower surface side of the insulating substrate 2 and the base plate 1.
　第二保持部６は、第二接合部３と濡れ性のよい材料で構成されている。このため、第二保持部６は、第二接合部３との接触界面で合金層を形成する。 The second holding portion 6 is composed of the second joint portion 3 and a material having good wettability. Therefore, the second holding portion 6 forms an alloy layer at the contact interface with the second joining portion 3.
　実施の形態１の図５から図１２に示した構成を、本実施の形態３においても適用することができ、絶縁基板２の上面側の金属層２１と半導体素子７の裏面とを第一接合部８で接合した場合の効果は、絶縁基板２の下面側の金属層２３とベース板１の上面とを第二接合部３で接合した場合においても同様の効果を得ることができる。 The configuration shown in FIGS. 5 to 12 of the first embodiment can be applied to the third embodiment, and the metal layer 21 on the upper surface side of the insulating substrate 2 and the back surface of the semiconductor element 7 are first joined. The same effect can be obtained when the metal layer 23 on the lower surface side of the insulating substrate 2 and the upper surface of the base plate 1 are joined by the second joining portion 3.
　第二保持部６は、絶縁基板２の下面側の金属層２３の角部の内側と外側とに設置されるが、一体で形成されていてもよい。また、第二保持部６は、絶縁基板２の下面側の金属層２３の角部の内側と外側とに設置されるが、半導体素子７の内側と外側とを別体で形成されていてもよい。 The second holding portion 6 is installed inside and outside the corner portion of the metal layer 23 on the lower surface side of the insulating substrate 2, but may be integrally formed. Further, the second holding portion 6 is installed inside and outside the corner portion of the metal layer 23 on the lower surface side of the insulating substrate 2, but even if the inside and outside of the semiconductor element 7 are formed separately. good.
　以上のように構成された半導体装置３００においては、第二保持部６を、第二接合部３内に埋設し、第二接合部３の角部の内側と外側とに設置したので、第二接合部３の厚みの設計値からのずれを低減し、接合不良を改善し、半導体装置の信頼性を向上させることができる。 In the semiconductor device 300 configured as described above, the second holding portion 6 is embedded in the second joint portion 3 and installed inside and outside the corner portion of the second joint portion 3, so that the second holding portion 6 is second. It is possible to reduce the deviation of the thickness of the joint portion 3 from the design value, improve the joint defect, and improve the reliability of the semiconductor device.
　また、第二保持部６を、第二接合部３内に埋設し、第二接合部３の角部の内側と外側とに設置したので、絶縁基板２の接合位置のずれを低減することができる。 Further, since the second holding portion 6 is embedded in the second joint portion 3 and installed inside and outside the corner portion of the second joint portion 3, it is possible to reduce the deviation of the joint position of the insulating substrate 2. can.
　さらに、第二接合部３の厚みを第二保持部６の第二接合部３の内側に存在する部分の高さは、第二接合部３の外側に存在する部分の高さに比べて低い。これによって、絶縁基板２の接合位置のずれを低減することができる。 Further, the height of the portion where the thickness of the second joint portion 3 exists inside the second joint portion 3 of the second holding portion 6 is lower than the height of the portion existing outside the second joint portion 3. .. This makes it possible to reduce the deviation of the joining position of the insulating substrate 2.
　また、第二保持部６を、第二接合部３内に埋設し、第二接合部３の角部の内側と外側とに設置したので、絶縁基板２の下面側の金属層２３の裏面の角部まで確実に第二接合部３が接合される（濡れ広がる）ことで、接合不良を改善することができる。 Further, since the second holding portion 6 is embedded in the second joint portion 3 and installed inside and outside the corner portion of the second joint portion 3, the back surface of the metal layer 23 on the lower surface side of the insulating substrate 2 is used. By reliably joining (wetting and spreading) the second joint portion 3 to the corner portion, it is possible to improve the joint defect.
　さらに、第二保持部６を、第二接合部３内に埋設し、第二接合部３の角部の内側と外側とに設置したので、第二接合部３が第二保持部６で濡れ広がることで、絶縁基板２の下面側の金属層２３の角部の側面にフィレットが形成され、絶縁基板２の下面側の金属層２３の角部での応力を低減することができる。 Further, since the second holding portion 6 is embedded in the second joint portion 3 and installed inside and outside the corner portion of the second joint portion 3, the second joint portion 3 gets wet with the second holding portion 6. By expanding, fillets are formed on the side surfaces of the corners of the metal layer 23 on the lower surface side of the insulating substrate 2, and the stress at the corners of the metal layer 23 on the lower surface side of the insulating substrate 2 can be reduced.
　また、第二保持部６として、第二接合部３と濡れ性のよい材料を用いたので、接合状態が改善され、半導体素子７からの放熱性が改善できる。 Further, since the material having good wettability with the second joint portion 3 is used as the second holding portion 6, the joint state can be improved and the heat dissipation from the semiconductor element 7 can be improved.
実施の形態４．
　本実施の形態４においては、実施の形態３で用いた第二保持部６に加えて第四保持部６６を半導体素子７の表面の電極１３（と配線部９との接合部）に対応する絶縁基板２の下面側の金属層２３の下面の位置にも配置した点で異なる。このように、半導体素子７の表面の電極１３に対応する絶縁基板２の下面側の金属層２３の下面にも第四保持部６６を配置したので、半導体素子７で発生した熱を第四保持部６６を通じて拡散することができる。その結果、半導体素子７からの放熱性の向上が可能となり、半導体装置４００の信頼性を向上することができる。なお、その他の点については、実施の形態２、実施の形態３と同様であるので、詳しい説明は省略する。 Embodiment 4.
In the fourth embodiment, in addition to the second holding portion 6 used in the third embodiment, the fourth holding portion 66 corresponds to the electrode 13 (the joint portion between the wiring portion 9 and the wiring portion 9) on the surface of the semiconductor element 7. It differs in that it is also arranged at the position of the lower surface of the metal layer 23 on the lower surface side of the insulating substrate 2. As described above, since the fourth holding portion 66 is also arranged on the lower surface of the metal layer 23 on the lower surface side of the insulating substrate 2 corresponding to the electrode 13 on the surface of the semiconductor element 7, the heat generated by the semiconductor element 7 is held fourth. It can be diffused through section 66. As a result, the heat dissipation from the semiconductor element 7 can be improved, and the reliability of the semiconductor device 400 can be improved. Since other points are the same as those in the second and third embodiments, detailed description thereof will be omitted.
　図２３は、実施の形態４における半導体装置を示す平面構造模式図である。図２４は、実施の形態３における半導体装置を示す断面構造模式図である。図２５は、実施の形態３における半導体装置を示す他の断面構造模式図である。図２６は、実施の形態４における半導体装置の保持部を示す平面構造模式図である。図２４は、図２３の一点鎖線ＧＧにおける断面構造模式図である。図２５は、図２３の一点鎖線ＨＨにおける断面構造模式図である。図２６は、第二接合部３を透過して、第二保持部６および第四保持部６６の配置を上面から見た平面構造模式図である。 FIG. 23 is a schematic plan structure diagram showing the semiconductor device according to the fourth embodiment. FIG. 24 is a schematic cross-sectional structure showing the semiconductor device according to the third embodiment. FIG. 25 is another schematic cross-sectional structure showing the semiconductor device according to the third embodiment. FIG. 26 is a schematic plan view showing a holding portion of the semiconductor device according to the fourth embodiment. FIG. 24 is a schematic cross-sectional structure of the alternate long and short dash line GG of FIG. 23. FIG. 25 is a schematic cross-sectional structure of the alternate long and short dash line HH of FIG. 23. FIG. 26 is a schematic plan view of the arrangement of the second holding portion 6 and the fourth holding portion 66 as viewed from above through the second joint portion 3.
　図において、半導体装置４００は、ベース板１と、絶縁基板２と、接合部である第一接合部８と、接合部である第二接合部３と、保持部である第二保持部６と、保持部である第四保持部６６と、半導体素子７と、配線部であるボンディングワイヤ９と、封止部１０と、電極端子１２と、を備えている。 In the figure, the semiconductor device 400 includes a base plate 1, an insulating substrate 2, a first joining portion 8 which is a joining portion, a second joining portion 3 which is a joining portion, and a second holding portion 6 which is a holding portion. A fourth holding portion 66, which is a holding portion, a semiconductor element 7, a bonding wire 9 which is a wiring portion, a sealing portion 10, and an electrode terminal 12 are provided.
　図２３において、第四保持部６６は、点線にて示している。半導体素子７の表面の電極１３の外形よりも内側に第四保持部６６が配置されている。第四保持部６６は、半導体素子７の表面の電極１３の配置位置に対応する絶縁基板２の下面側の金属層２３の下面の位置に配置される。特に、半導体素子７の表面の電極１３のボンディングワイヤ９が接合された箇所を含んだ絶縁基板２の下面側の金属層２３の下面の対応する位置に配置される。このように配置することで、半導体装置１００（半導体素子７）の動作時に発生する熱を発熱箇所から効率的に放熱することができる In FIG. 23, the fourth holding portion 66 is shown by a dotted line. The fourth holding portion 66 is arranged inside the outer shape of the electrode 13 on the surface of the semiconductor element 7. The fourth holding portion 66 is arranged at the position of the lower surface of the metal layer 23 on the lower surface side of the insulating substrate 2 corresponding to the arrangement position of the electrode 13 on the surface of the semiconductor element 7. In particular, it is arranged at a corresponding position on the lower surface of the metal layer 23 on the lower surface side of the insulating substrate 2 including the portion where the bonding wire 9 of the electrode 13 on the surface of the semiconductor element 7 is bonded. By arranging in this way, the heat generated during the operation of the semiconductor device 100 (semiconductor element 7) can be efficiently dissipated from the heat generating portion.
　図２４、図２５において、第四保持部６６の厚さ（高さ）は、第二内部保持部６４の厚さ（高さ）と同等の厚さである。絶縁基板２は、第二内部保持部６４と第四保持部６６とで支持（保持）される。 In FIGS. 24 and 25, the thickness (height) of the fourth holding portion 66 is the same as the thickness (height) of the second internal holding portion 64. The insulating substrate 2 is supported (held) by the second internal holding portion 64 and the fourth holding portion 66.
　図２６において、第二内部保持部６４の一端は、絶縁基板２の下面側の金属層２３の角部よりも内側に配置され、第二内部保持部６４の他端は、第二内部保持部６４の一端よりも絶縁基板２の下面側の金属層２３の角部側に配置される。第四保持部６６は、絶縁基板２の下面側の金属層２３の角部（四隅）に配置された第二内部保持部６４の一端よりも絶縁基板２の下面側の金属層２３の中央部寄りに配置されている。 In FIG. 26, one end of the second internal holding portion 64 is arranged inside the corner portion of the metal layer 23 on the lower surface side of the insulating substrate 2, and the other end of the second internal holding portion 64 is the second internal holding portion. It is arranged on the corner side of the metal layer 23 on the lower surface side of the insulating substrate 2 with respect to one end of 64. The fourth holding portion 66 is a central portion of the metal layer 23 on the lower surface side of the insulating substrate 2 than one end of the second internal holding portion 64 arranged at the corners (four corners) of the metal layer 23 on the lower surface side of the insulating substrate 2. It is located closer to you.
　第二保持部６としては、実施の形態１で用いた第一保持部６のいずれの形態でも同様に適用できる。 As the second holding unit 6, any form of the first holding unit 6 used in the first embodiment can be similarly applied.
　以上のように構成された半導体装置４００においては、第二保持部６を、第二接合部３内に埋設し、第二接合部３の角部の内側と外側とに設置したので、第二接合部３の厚みの設計値からのずれを低減し、接合不良を改善し、半導体装置の信頼性を向上させることができる。 In the semiconductor device 400 configured as described above, the second holding portion 6 is embedded in the second joint portion 3 and installed inside and outside the corner portion of the second joint portion 3, so that the second holding portion 6 is second. It is possible to reduce the deviation of the thickness of the joint portion 3 from the design value, improve the joint defect, and improve the reliability of the semiconductor device.
　また、第二保持部６を、第二接合部３内に埋設し、第二接合部３の角部の内側と外側とに設置したので、絶縁基板２の下面側の金属層２３の接合位置のずれを低減することができる。 Further, since the second holding portion 6 is embedded in the second joint portion 3 and installed inside and outside the corner portion of the second joint portion 3, the joint position of the metal layer 23 on the lower surface side of the insulating substrate 2 is formed. The deviation can be reduced.
　さらに、第二接合部３の厚みを第二保持部６の第二接合部３内側に存在する部分の高さは、第二接合部３の外側に存在する部分の高さに比べて低い。これによって、絶縁基板２の下面側の金属層２３の接合位置のずれを低減することができる。 Further, the height of the portion where the thickness of the second joint portion 3 exists inside the second joint portion 3 of the second holding portion 6 is lower than the height of the portion existing outside the second joint portion 3. As a result, it is possible to reduce the deviation of the joining position of the metal layer 23 on the lower surface side of the insulating substrate 2.
　また、第二保持部６を、第二接合部３内に埋設し、第二接合部３の角部の内側と外側とに設置したので、絶縁基板２の下面側の金属層２３の下面の角部まで確実に第二接合部３が接合される（濡れ広がる）ことで、接合不良を改善することができる。 Further, since the second holding portion 6 is embedded in the second joint portion 3 and installed inside and outside the corner portion of the second joint portion 3, the lower surface of the metal layer 23 on the lower surface side of the insulating substrate 2 By reliably joining (wetting and spreading) the second joint portion 3 to the corner portion, it is possible to improve the joint defect.
　さらに、第二保持部６を、第二接合部３内に埋設し、第二接合部３の角部の内側と外側とに設置したので、第二接合部３が保持部６で濡れ広がることで、絶縁基板２の下面側の金属層２３の角部の側面にフィレットが形成され、絶縁基板２の下面側の金属層２３の角部での応力を低減することができる。 Further, since the second holding portion 6 is embedded in the second joint portion 3 and installed inside and outside the corner portion of the second joint portion 3, the second joint portion 3 gets wet and spreads in the holding portion 6. Therefore, fillets are formed on the side surfaces of the corners of the metal layer 23 on the lower surface side of the insulating substrate 2, and the stress at the corners of the metal layer 23 on the lower surface side of the insulating substrate 2 can be reduced.
　また、第二保持部６として、第二接合部３と濡れ性のよい材料を用いたので、接合状態が改善され、半導体素子７からの放熱性が改善できる。 Further, since the material having good wettability with the second joint portion 3 is used as the second holding portion 6, the joint state can be improved and the heat dissipation from the semiconductor element 7 can be improved.
　さらに、第四保持部６６を、半導体素子７の表面の電極１３に対応する絶縁基板２の下面側の金属層２３の下面側に配置したので、半導体素子７での発熱を効率よく放熱でき、半導体装置の信頼性を向上することができる。 Further, since the fourth holding portion 66 is arranged on the lower surface side of the metal layer 23 on the lower surface side of the insulating substrate 2 corresponding to the electrode 13 on the surface of the semiconductor element 7, the heat generated by the semiconductor element 7 can be efficiently dissipated. The reliability of the semiconductor device can be improved.
実施の形態５．
　本実施の形態５は、上述した実施の形態１から４にかかる半導体装置を電力変換装置に適用したものである。本開示は特定の電力変換装置に限定されるものではないが、以下、実施の形態５として、三相のインバータに本開示を適用した場合について説明する。 Embodiment 5.
In the fifth embodiment, the semiconductor device according to the first to fourth embodiments described above is applied to the power conversion device. Although the present disclosure is not limited to a specific power conversion device, the case where the present disclosure is applied to a three-phase inverter will be described below as the fifth embodiment.
　図２７は、本開示の実施の形態５における電力変換装置を適用した電力変換システムの構成を示すブロック図である。 FIG. 27 is a block diagram showing a configuration of a power conversion system to which the power conversion device according to the fifth embodiment of the present disclosure is applied.
　図２７に示す電力変換システムは、電源１０００、電力変換装置２０００、負荷３０００を備えている。電源１０００は、直流電源であり、電力変換装置２０００に直流電力を供給する。電源１０００は種々のもので構成することができ、例えば、直流系統、太陽電池、蓄電池で構成することができるし、交流系統に接続された整流回路、ＡＣ／ＤＣコンバータなどで構成することとしてもよい。また、電源１０００を、直流系統から出力される直流電力を所定の電力に変換するＤＣ／ＤＣコンバータによって構成することとしてもよい。 The power conversion system shown in FIG. 27 includes a power supply 1000, a power conversion device 2000, and a load 3000. The power supply 1000 is a DC power supply, and supplies DC power to the power converter 2000. The power supply 1000 can be composed of various things, for example, a DC system, a solar cell, a storage battery, a rectifier circuit connected to an AC system, an AC / DC converter, or the like. good. Further, the power supply 1000 may be configured by a DC / DC converter that converts the DC power output from the DC system into a predetermined power.
　電力変換装置２０００は、電源１０００と負荷３０００との間に接続された三相のインバータであり、電源１０００から供給された直流電力を交流電力に変換し、負荷３０００に交流電力を供給する。電力変換装置２０００は、図２７に示すように、電源１０００から入力される直流電力を交流電力に変換して出力する主変換回路２００１と、主変換回路２００１を制御する制御信号を主変換回路２００１に出力する制御回路２００３とを備えている。 The power conversion device 2000 is a three-phase inverter connected between the power supply 1000 and the load 3000, converts the DC power supplied from the power supply 1000 into AC power, and supplies AC power to the load 3000. As shown in FIG. 27, the power conversion device 2000 converts the DC power input from the power supply 1000 into AC power and outputs the main conversion circuit 2001, and the main conversion circuit 2001 controls the control signal for controlling the main conversion circuit 2001. It is equipped with a control circuit 2003 that outputs to.
　負荷３０００は、電力変換装置２０００から供給された交流電力によって駆動される三相の電動機である。なお、負荷３０００は特定の用途に限られるものではなく、各種電気機器に搭載された電動機であり、例えば、ハイブリッド自動車、電気自動車、鉄道車両、エレベーター、空調機器向けの電動機等として用いられる。 The load 3000 is a three-phase electric motor driven by AC power supplied from the power converter 2000. The load 3000 is not limited to a specific application, and is an electric motor mounted on various electric devices, and is used as, for example, an electric motor for a hybrid vehicle, an electric vehicle, a railroad vehicle, an elevator, an air conditioner, and the like.
　以下、電力変換装置２０００の詳細を説明する。主変換回路２００１は、半導体装置２００２に内蔵されたスイッチング素子と還流ダイオードとを備えており（図示せず）、スイッチング素子がスイッチングすることによって、電源１０００から供給される直流電力を交流電力に変換し、負荷３０００に供給する。主変換回路２００１の具体的な回路構成は種々のものがあるが、本実施の形態にかかる主変換回路２００１は２レベルの三相フルブリッジ回路であり、６つのスイッチング素子とそれぞれのスイッチング素子に逆並列に接続された６つの還流ダイオードとから構成することができる。主変換回路２００１は、各スイッチング素子、各還流ダイオードなどを内蔵する上述した実施の形態１から５のいずれかに相当する半導体装置２００２によって構成される。６つのスイッチング素子は２つのスイッチング素子ごとに直列接続され上下アームを構成し、各上下アームはフルブリッジ回路の各相（Ｕ相、Ｖ相、Ｗ相）を構成する。各上下アームの出力端子、すなわち主変換回路２００１の３つの出力端子は、負荷３０００に接続される。 The details of the power converter 2000 will be described below. The main conversion circuit 2001 includes a switching element built in the semiconductor device 2002 and a freewheeling diode (not shown), and the DC power supplied from the power supply 1000 is converted into AC power by switching the switching element. And supply to the load 3000. There are various specific circuit configurations of the main conversion circuit 2001, but the main conversion circuit 2001 according to the present embodiment is a two-level three-phase full bridge circuit, and has six switching elements and each switching element. It can be composed of six freewheeling diodes connected in antiparallel. The main conversion circuit 2001 is composed of a semiconductor device 2002 corresponding to any one of the above-described embodiments 1 to 5 in which each switching element, each freewheeling diode, and the like are built. The six switching elements are connected in series for each of the two switching elements to form an upper and lower arm, and each upper and lower arm constitutes each phase (U phase, V phase, W phase) of the full bridge circuit. The output terminals of each upper and lower arm, that is, the three output terminals of the main conversion circuit 2001 are connected to the load 3000.
　また、主変換回路２００１は、各スイッチング素子を駆動する駆動回路（図示なし）を備えている。駆動回路は半導体装置２００２に内蔵されていてもよいし、半導体装置２００２とは別に駆動回路を備える構成であってもよい。駆動回路は、主変換回路２００１のスイッチング素子を駆動する駆動信号を生成し、主変換回路２００１のスイッチング素子の制御電極に供給する。具体的には、後述する制御回路２００３からの制御信号に従い、スイッチング素子をオン状態にする駆動信号とスイッチング素子をオフ状態にする駆動信号とを各スイッチング素子の制御電極に出力する。スイッチング素子をオン状態に維持する場合、駆動信号はスイッチング素子の閾値電圧以上の電圧信号（オン信号）であり、スイッチング素子をオフ状態に維持する場合、駆動信号はスイッチング素子の閾値電圧以下の電圧信号（オフ信号）となる。 Further, the main conversion circuit 2001 includes a drive circuit (not shown) for driving each switching element. The drive circuit may be built in the semiconductor device 2002, or may be configured to include a drive circuit separately from the semiconductor device 2002. The drive circuit generates a drive signal for driving the switching element of the main conversion circuit 2001 and supplies the drive signal to the control electrode of the switching element of the main conversion circuit 2001. Specifically, according to the control signal from the control circuit 2003 described later, a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to the control electrode of each switching element. When the switching element is kept on, the drive signal is a voltage signal (on signal) equal to or higher than the threshold voltage of the switching element, and when the switching element is kept off, the drive signal is a voltage equal to or lower than the threshold voltage of the switching element. It becomes a signal (off signal).
　制御回路２００３は、負荷３０００に所望の電力が供給されるよう主変換回路２００１のスイッチング素子を制御する。具体的には、負荷３０００に供給すべき電力に基づいて主変換回路２００１の各スイッチング素子がオン状態となるべき時間（オン時間）を算出する。例えば、出力すべき電圧に応じてスイッチング素子のオン時間を変調するＰＷＭ制御によって主変換回路２００１を制御することができる。また、各時点においてオン状態となるべきスイッチング素子にはオン信号を出力し、オフ状態となるべきスイッチング素子にはオフ信号を出力されるように、主変換回路２００１が備える駆動回路に制御指令（制御信号）を出力する。駆動回路は、この制御信号に従い、各スイッチング素子の制御電極にオン信号又はオフ信号を駆動信号として出力する。 The control circuit 2003 controls the switching element of the main conversion circuit 2001 so that the desired power is supplied to the load 3000. Specifically, the time (on time) for each switching element of the main conversion circuit 2001 to be in the on state is calculated based on the electric power to be supplied to the load 3000. For example, the main conversion circuit 2001 can be controlled by PWM control that modulates the on-time of the switching element according to the voltage to be output. Further, a control command is given to the drive circuit provided in the main conversion circuit 2001 so that an on signal is output to the switching element that should be turned on at each time point and an off signal is output to the switching element that should be turned off. Control signal) is output. The drive circuit outputs an on signal or an off signal as a drive signal to the control electrode of each switching element according to this control signal.
　以上のように構成された本実施の形態５に係る電力変換装置においては、主変換回路２００１の半導体装置２００２として実施の形態１から４にかかる半導体装置を適用するため、信頼性向上を実現することができる。 In the power conversion device according to the fifth embodiment configured as described above, the semiconductor device according to the first to fourth embodiments is applied as the semiconductor device 2002 of the main conversion circuit 2001, so that the reliability is improved. be able to.
　本実施の形態では、２レベルの三相インバータに本開示を適用する例を説明したが、本開示は、これに限られるものではなく、種々の電力変換装置に適用することができる。本実施の形態では、２レベルの電力変換装置としたが３レベル、マルチレベルの電力変換装置であってもよいし、単相負荷に電力を供給する場合には単相のインバータに本開示を適用してもよい。また、直流負荷等に電力を供給する場合にはＤＣ／ＤＣコンバータ、ＡＣ／ＤＣコンバータなどに本開示を適用することもできる。 In the present embodiment, an example of applying the present disclosure to a two-level three-phase inverter has been described, but the present disclosure is not limited to this, and can be applied to various power conversion devices. In the present embodiment, the two-level power conversion device is used, but a three-level, multi-level power conversion device may be used, and when power is supplied to a single-phase load, the present disclosure is given to the single-phase inverter. It may be applied. Further, when power is supplied to a DC load or the like, the present disclosure can be applied to a DC / DC converter, an AC / DC converter, and the like.
　また、本開示を適用した電力変換装置は、上述した負荷が電動機の場合に限定されるものではなく、例えば、放電加工機、レーザー加工機、誘導加熱調理器、非接触器給電システムの電源装置等として用いることもでき、さらには、太陽光発電システム、蓄電システム等のパワーコンディショナーとして用いることもできる。 Further, the power conversion device to which the present disclosure is applied is not limited to the case where the above-mentioned load is an electric motor, and is, for example, a power supply device for a discharge machine, a laser machine, an induction heating cooker, or a non-contact power supply system. It can also be used as a power conditioner for a photovoltaic power generation system, a power storage system, or the like.
　特に、半導体素子７として、ＳｉＣを用いた場合、電力用半導体素子はその特徴を生かすために、Ｓｉの時と比較してより高温で動作させることになる。ＳｉＣデバイスを搭載する半導体装置においては、より高い信頼性が求められるため、高信頼の半導体装置を実現するという本開示のメリットはより効果的なものとなる。 In particular, when SiC is used as the semiconductor element 7, the power semiconductor element is operated at a higher temperature than that of Si in order to take advantage of its characteristics. Since a semiconductor device equipped with a SiC device is required to have higher reliability, the merit of the present disclosure of realizing a highly reliable semiconductor device becomes more effective.
　上述した実施の形態は、すべての点で例示であって制限的なものではないと解されるべきである。本開示の範囲は、上述した実施形態の範囲ではなく、特許請求の範囲によって示され、特許請求の範囲と均等の意味及び範囲内でのすべての変更を含むものである。また、上記の実施形態に開示されている複数の構成要素を適宜組み合わせることにより発明を形成してもよい。 It should be understood that the embodiments described above are exemplary in all respects and not restrictive. The scope of the present disclosure is not the scope of the embodiments described above, but is indicated by the scope of claims and includes all modifications within the meaning and scope equivalent to the scope of claims. Further, the invention may be formed by appropriately combining a plurality of components disclosed in the above-described embodiment.
１　ベース板、２　絶縁基板、３　第二接合部、４　ケース部、６　第一保持部，第二保持部、７　半導体素子、８　第一接合部、９　配線部、１０　封止部、１２　電極端子、６１　第一内部保持部、６２　第一外部保持部、６３　第三保持部、６４　第二内部保持部、６５　第二外部保持部、６６　第四保持部、１００, １０１，２００，３００, ４００,２００２　半導体装置、１０００　電源、２０００　電力変換装置、２００１　主変換回路、２００３　制御回路、３０００　負荷。 1 base plate, 2 insulating substrate, 3 second joint, 4 case, 6 first holding, second holding, 7 semiconductor element, 8 first joining, 9 wiring, 10 sealing, 12 electrodes Terminal, 61 1st internal holding part, 62 1st external holding part, 63 3rd holding part, 64 2nd internal holding part, 65 2nd external holding part, 66 4th holding part, 100, 101, 200, 300, 400,2002 semiconductor device, 1000 power supply, 2000 power conversion device, 2001 main conversion circuit, 2003 control circuit, 3000 load.

Claims (14)

  1. 表面に電極を有する半導体素子と、
    上面と下面とに金属層を有し、前記半導体素子が上面側の前記金属層の上面に第一接合部で接合された絶縁基板と、
    前記絶縁基板が上面に第二接合部で接合されたベース板と、
    前記第一接合部と前記第二接合部との少なくともいずれか一方に埋設され、前記第一接合部内に埋設された場合は前記半導体素子の角部の対角方向で内側と外側とに配置され、前記第二接合部内に埋設された場合は前記絶縁基板の下面側の前記金属層の角部の対角方向で内側と外側とに配置される保持部と、
    を備えた半導体装置。     Semiconductor devices with electrodes on the surface and
    An insulating substrate having a metal layer on an upper surface and a lower surface, and the semiconductor element bonded to the upper surface of the metal layer on the upper surface side at a first joining portion.
    The base plate to which the insulating substrate is bonded to the upper surface at the second joint,
    It is embedded in at least one of the first joint and the second joint, and when it is embedded in the first joint, it is arranged inside and outside in the diagonal direction of the corner of the semiconductor element. When embedded in the second joint, a holding portion arranged on the inner side and the outer side in the diagonal direction of the corner portion of the metal layer on the lower surface side of the insulating substrate.
    A semiconductor device equipped with.
  2. 前記保持部は、別体で形成されている、請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the holding portion is formed as a separate body.
  3. 前記保持部は、一体で形成されている、請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the holding portion is integrally formed.
  4. 前記保持部は、前記第一接合部との接触界面で合金層を形成する、請求項１から請求項３のいずれか一項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 3, wherein the holding portion forms an alloy layer at a contact interface with the first joint portion.
  5. 前記保持部は、前記第二接合部との接触界面で合金層を形成する、請求項１から請求項４のいずれか一項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 4, wherein the holding portion forms an alloy layer at a contact interface with the second joint portion.
  6. 前記保持部は、前記第一接合部内に埋設される第一保持部と前記第二接合部内に埋設される第二保持部とを有し、前記第一保持部は、第一内部保持部と第一外部保持部とで構成され、前記第二保持部は、第二内部保持部と第二外部保持部とで構成され、
    前記第一内部保持部は、前記半導体素子の外縁より内側に配置され、前記第一外部保持部は、前記半導体素子の外縁よりも外側に配置され、前記第一外部保持部は、前記半導体素子の外周側面と接し、
    前記第二内部保持部は、前記絶縁基板の下面側の前記金属層の外縁より内側に配置され、前記第二外部保持部は、前記絶縁基板の下面側の前記金属層の外縁よりも外側に配置され、前記第二外部保持部は、前記絶縁基板の下面側の前記金属層の外周側面と接している、請求項１から請求項５のいずれか一項に記載の半導体装置。     The holding portion has a first holding portion embedded in the first joint portion and a second holding portion embedded in the second joint portion, and the first holding portion includes a first internal holding portion. It is composed of a first external holding portion, and the second holding portion is composed of a second internal holding portion and a second external holding portion.
    The first internal holding portion is arranged inside the outer edge of the semiconductor element, the first external holding portion is arranged outside the outer edge of the semiconductor element, and the first external holding portion is the semiconductor element. In contact with the outer peripheral side of the
    The second internal holding portion is arranged inside the outer edge of the metal layer on the lower surface side of the insulating substrate, and the second outer holding portion is outside the outer edge of the metal layer on the lower surface side of the insulating substrate. The semiconductor device according to any one of claims 1 to 5, wherein the second external holding portion is arranged and is in contact with the outer peripheral side surface of the metal layer on the lower surface side of the insulating substrate.
  7. 前記第一内部保持部の高さは、前記第一外部保持部の高さよりも低い、請求項６に記載の半導体装置。 The semiconductor device according to claim 6, wherein the height of the first internal holding portion is lower than the height of the first external holding portion.
  8. 前記第二内部保持部の高さは、前記第二外部保持部の高さよりも低い、請求項６または請求項７に記載の半導体装置。 The semiconductor device according to claim 6 or 7, wherein the height of the second internal holding portion is lower than the height of the second external holding portion.
  9. 第三保持部は、前記第一接合部内の前記半導体素子の表面の電極に対応する前記半導体素子の裏面の位置に配置される、請求項１から請求項８のいずれか一項に記載の半導体装置。 The semiconductor according to any one of claims 1 to 8, wherein the third holding portion is arranged at a position on the back surface of the semiconductor device corresponding to an electrode on the front surface of the semiconductor element in the first junction portion. Device.
  10. 第四保持部は、前記第二接合部内の前記半導体素子の表面の電極に対応する前記絶縁基板の下面側の前記金属層の位置に配置される、請求項１から請求項９のいずれか一項に記載の半導体装置。 Any one of claims 1 to 9, wherein the fourth holding portion is arranged at the position of the metal layer on the lower surface side of the insulating substrate corresponding to the electrode on the surface of the semiconductor element in the second joint portion. The semiconductor device described in the section.
  11. 前記保持部は、一部が前記第一接合部から露出している、請求項１から請求項１０のいずれか一項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 10, wherein the holding portion is partially exposed from the first joint portion.
  12. 前記保持部は、一部が前記第二接合部から露出している、請求項１から請求項１１のいずれか一項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 11, wherein the holding portion is partially exposed from the second joint portion.
  13. 請求項１から請求項１２のいずれか一項に記載の半導体装置を有し、入力される電力を変換して出力する主変換回路と、
    前記主変換回路を制御する制御信号を前記主変換回路に出力する制御回路と、
    を備えた電力変換装置。     A main conversion circuit having the semiconductor device according to any one of claims 1 to 12 and converting and outputting input power.
    A control circuit that outputs a control signal that controls the main conversion circuit to the main conversion circuit, and a control circuit that outputs the control signal to the main conversion circuit.
    Power conversion device equipped with.
  14. 表面に電極を有する半導体素子を準備する半導体素子準備工程と、
    上面と下面とに金属層を有する絶縁基板を準備し、前記絶縁基板の上面側の前記金属層の上面に第一接合部で前記半導体素子を接合する半導体素子接合工程と、
    ベース板の上面に前記絶縁基板を第二接合部で接合する絶縁基板接合工程と
    保持部を前記第一接合部と前記第二接合部との少なくともいずれか一方に埋設し、前記保持部が前記第一接合部内に埋設される場合は前記半導体素子の角部の対角方向で内側と外側とに配置し、前記保持部が前記第二接合部内に埋設される場合は前記絶縁基板の下面側の前記金属層の角部の対角方向で内側と外側とに配置する保持部配置工程と、
    を備えた半導体装置の製造方法。     A semiconductor device preparation process that prepares a semiconductor device having electrodes on its surface,
    A semiconductor device joining step of preparing an insulating substrate having a metal layer on an upper surface and a lower surface and joining the semiconductor element to the upper surface of the metal layer on the upper surface side of the insulating substrate at a first joining portion.
    An insulating substrate joining step of joining the insulating substrate at the second joining portion and a holding portion are embedded in at least one of the first joining portion and the second joining portion on the upper surface of the base plate, and the holding portion is the said. When it is embedded in the first joint, it is arranged inside and outside in the diagonal direction of the corner of the semiconductor element, and when the holding portion is embedded in the second joint, it is on the lower surface side of the insulating substrate. In the holding portion arranging step of arranging the inside and the outside in the diagonal direction of the corner portion of the metal layer of the above.
    A method for manufacturing a semiconductor device.
PCT/JP2020/033445 2020-09-03 2020-09-03 Semiconductor device, power conversion device, and method for manufacturing semiconductor device WO2022049697A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/JP2020/033445 WO2022049697A1 (en) 2020-09-03 2020-09-03 Semiconductor device, power conversion device, and method for manufacturing semiconductor device
JP2020570068A JP6885522B1 (en) 2020-09-03 2020-09-03 Semiconductor device, power conversion device and manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2020/033445 WO2022049697A1 (en) 2020-09-03 2020-09-03 Semiconductor device, power conversion device, and method for manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
WO2022049697A1 true WO2022049697A1 (en) 2022-03-10

Family

ID=76310137

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2020/033445 WO2022049697A1 (en) 2020-09-03 2020-09-03 Semiconductor device, power conversion device, and method for manufacturing semiconductor device

Country Status (2)

Country Link
JP (1) JP6885522B1 (en)
WO (1) WO2022049697A1 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11186331A (en) * 1997-12-19 1999-07-09 Mitsubishi Electric Corp Semiconductor device and its manufacture
JP2007134395A (en) * 2005-11-08 2007-05-31 Rohm Co Ltd Semiconductor device
JP2011228604A (en) * 2010-04-23 2011-11-10 Honda Motor Co Ltd Manufacturing method of circuit board and circuit board
JP2012190958A (en) * 2011-03-10 2012-10-04 Denso Corp Resin sealed semiconductor device and manufacturing method therefor
WO2015004956A1 (en) * 2013-07-10 2015-01-15 三菱電機株式会社 Semiconductor device and manufacturing method for same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11186331A (en) * 1997-12-19 1999-07-09 Mitsubishi Electric Corp Semiconductor device and its manufacture
JP2007134395A (en) * 2005-11-08 2007-05-31 Rohm Co Ltd Semiconductor device
JP2011228604A (en) * 2010-04-23 2011-11-10 Honda Motor Co Ltd Manufacturing method of circuit board and circuit board
JP2012190958A (en) * 2011-03-10 2012-10-04 Denso Corp Resin sealed semiconductor device and manufacturing method therefor
WO2015004956A1 (en) * 2013-07-10 2015-01-15 三菱電機株式会社 Semiconductor device and manufacturing method for same

Also Published As

Publication number Publication date
JP6885522B1 (en) 2021-06-16
JPWO2022049697A1 (en) 2022-03-10

Similar Documents

Publication Publication Date Title
US20220028794A1 (en) Semiconductor device, power converter, method for manufacturing semiconductor device, and method for manufacturing power converter
JP6685470B2 (en) Semiconductor device, manufacturing method thereof, and power conversion device
JP6965706B2 (en) Semiconductor module, its manufacturing method and power converter
US11271352B2 (en) Power semiconductor device and manufacturing method thereof, and power conversion device
JP6756407B2 (en) Semiconductor module and power converter
JP2018067611A (en) Semiconductor device and power conversion device
JPWO2020136810A1 (en) Semiconductor devices, manufacturing methods for semiconductor devices, and power conversion devices
JP6575739B1 (en) Semiconductor device, semiconductor device manufacturing method, and power conversion device
CN114846598A (en) Power module and power conversion device
WO2022049697A1 (en) Semiconductor device, power conversion device, and method for manufacturing semiconductor device
WO2022264215A1 (en) Semiconductor device and power conversion device
JP7176662B1 (en) Semiconductor equipment and power conversion equipment
JP7438466B1 (en) Semiconductor device and its manufacturing method, and power conversion device
JP2020009995A (en) Semiconductor device, power conversion apparatus and manufacturing method for semiconductor device
JP7270772B2 (en) Semiconductor device, power conversion device, and method for manufacturing semiconductor device
JP7237192B2 (en) Semiconductor device, manufacturing method thereof, and power conversion device
JP7106007B2 (en) Semiconductor equipment and power conversion equipment
JP7019024B2 (en) Semiconductor equipment and power conversion equipment
JP7387232B2 (en) Semiconductor device, power conversion device, and method for manufacturing semiconductor device
WO2024004026A1 (en) Semiconductor device and power conversion device
WO2024062845A1 (en) Semiconductor device
WO2023193928A1 (en) Arrangement for a power module, power module and method for producing an arrangement for a power module
JP2023173556A (en) Method for manufacturing semiconductor module, method for manufacturing power conversion system, semiconductor module, power conversion system
JP2022007599A (en) Semiconductor device

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref document number: 2020570068

Country of ref document: JP

Kind code of ref document: A

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20952435

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20952435

Country of ref document: EP

Kind code of ref document: A1