WO2024062845A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
WO2024062845A1
WO2024062845A1 PCT/JP2023/030949 JP2023030949W WO2024062845A1 WO 2024062845 A1 WO2024062845 A1 WO 2024062845A1 JP 2023030949 W JP2023030949 W JP 2023030949W WO 2024062845 A1 WO2024062845 A1 WO 2024062845A1
Authority
WO
WIPO (PCT)
Prior art keywords
protective film
electrode
wiring
semiconductor device
main electrode
Prior art date
Application number
PCT/JP2023/030949
Other languages
French (fr)
Japanese (ja)
Inventor
瑛美夏 安部
卓矢 門口
知巳 奥村
Original Assignee
株式会社デンソー
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社デンソー filed Critical 株式会社デンソー
Publication of WO2024062845A1 publication Critical patent/WO2024062845A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N

Definitions

  • the disclosure in this specification relates to a semiconductor device.
  • Patent Document 1 discloses a semiconductor device that includes a semiconductor chip having main electrodes on both sides, a conductive member, and a sintered layer that bonds the main electrodes and the conductive member.
  • the contents of the prior art document are incorporated by reference as explanations of the technical elements in this specification.
  • One of the main electrodes is exposed through an opening in the polyimide protective film so that it can be bonded.
  • a protective film surrounds the exposed portion of the main electrode.
  • the upper surface of the protective film is located above the bonding surface of the main electrode.
  • the sintered layer is provided so as to almost coincide with the exposed portion of the main electrode in a plan view. Therefore, if the sintered layer is misaligned with respect to the main electrode, stress will be concentrated on the protective film side due to the pressure applied during sinter bonding, which may damage the protective film or cause cracks in the wiring portion covered by the protective film. To address this issue, it is possible to reduce the area of the sintered layer, taking into account the tolerance for misalignment. However, this would increase thermal resistance and current density.
  • the present disclosure has been made in view of such problems, and aims to provide a semiconductor device that can improve reliability.
  • the semiconductor device which is one of the disclosures, is A semiconductor substrate, a first main electrode provided on one surface of the semiconductor substrate, a second main electrode provided on the back surface opposite to the one surface in the board thickness direction, and the first main electrode provided on one surface can be bonded.
  • a semiconductor element having a protective film having an opening exposed to the semiconductor element; a conductive member electrically connected to the first main electrode; a sintered member interposed between the first main electrode and the conductive member and joining the first main electrode and the conductive member; At least a portion of the upper surface of the protective film surrounding the opening is located flush with or less than the bonding surface of the first main electrode in the plate thickness direction.
  • the disclosed semiconductor device at least the portion of the upper surface of the protective film surrounding the opening does not protrude above the bonding surface of the first main electrode in the thickness direction. Therefore, even if the position of the sintered member is shifted from the exposed part of the first main electrode, stress concentration on the protective film side due to the pressure applied during sintering and joining can be suppressed. Can be done. Further, stress concentration on the protective film side can be suppressed without reducing the size of the sintered member. As a result, a semiconductor device with improved reliability can be provided.
  • FIG. 1 is a diagram showing a schematic configuration of a vehicle drive system to which a semiconductor device according to a first embodiment is applied.
  • FIG. 1 is a plan view showing a semiconductor device according to a first embodiment.
  • 3 is a sectional view taken along line III-III in FIG. 2.
  • FIG. 3 is a cross-sectional view taken along line IV-IV in FIG. 2 .
  • FIG. 2 is a plan view showing a semiconductor element.
  • 6 is a cross-sectional view taken along the line VI-VI in FIG. 5.
  • FIG. 1 is a cross-sectional view showing a junction structure of a semiconductor element.
  • FIG. 3 is a cross-sectional view showing a joining method. It is a sectional view showing a reference example. It is a sectional view showing a reference example.
  • FIG. 3 is a cross-sectional view showing an example of positional displacement in the present embodiment.
  • FIG. 7 is a cross-sectional view showing a semiconductor element in a semiconductor device according to a second embodiment.
  • FIG. 7 is a plan view showing a semiconductor element in a semiconductor device according to a third embodiment.
  • 14 is a cross-sectional view showing the junction structure of the semiconductor element corresponding to the line XIV-XIV in FIG. 13.
  • FIG. It is a top view which shows a modification. It is a sectional view showing other modifications. It is a sectional view showing other modifications.
  • the semiconductor device of this embodiment is applied, for example, to a power conversion device for a moving object that uses a rotating electric machine as a drive source.
  • mobile objects include electric vehicles such as electric vehicles (BEV), hybrid vehicles (HEV), and plug-in hybrid vehicles (PHEV), flying vehicles such as electric vertical takeoff and landing aircraft and drones, ships, construction machinery, and agricultural machinery.
  • BEV electric vehicles
  • HEV hybrid vehicles
  • PHEV plug-in hybrid vehicles
  • flying vehicles such as electric vertical takeoff and landing aircraft and drones, ships, construction machinery, and agricultural machinery.
  • a vehicle drive system 1 includes a DC power source 2, a motor generator 3, and a power converter 4.
  • the DC power supply 2 is a DC voltage source composed of a rechargeable and dischargeable secondary battery.
  • the secondary battery is, for example, a lithium ion battery or a nickel metal hydride battery.
  • the motor generator 3 is a three-phase AC rotating electric machine.
  • the motor generator 3 functions as a driving source for the vehicle, that is, an electric motor.
  • the motor generator 3 functions as a generator during regeneration.
  • Power conversion device 4 performs power conversion between DC power supply 2 and motor generator 3 .
  • the power conversion device 4 includes a power conversion circuit. As shown in FIG. 1, the power conversion device 4 includes a smoothing capacitor 5 and an inverter 6 that is a power conversion circuit.
  • the smoothing capacitor 5 mainly smoothes the DC voltage supplied from the DC power supply 2.
  • the smoothing capacitor 5 is connected to a P line 7 which is a power line on the high potential side and an N line 8 which is a power line on the low potential side.
  • the P line 7 is connected to the positive pole of the DC power supply 2
  • the N line 8 is connected to the negative pole of the DC power supply 2.
  • a positive terminal of the smoothing capacitor 5 is connected to a P line 7 between the DC power supply 2 and the inverter 6.
  • the negative electrode is connected to the N line 8 between the DC power supply 2 and the inverter 6.
  • Smoothing capacitor 5 is connected in parallel to DC power supply 2 .
  • the inverter 6 is a DC-AC conversion circuit. In accordance with switching control by a control circuit (not shown), the inverter 6 converts DC voltage into three-phase AC voltage and outputs it to the motor generator 3. This drives the motor generator 3 to generate a predetermined torque. During regenerative braking of the vehicle, the inverter 6 converts the three-phase AC voltage generated by the motor generator 3 in response to rotational force from the wheels into DC voltage in accordance with switching control by the control circuit, and outputs it to the P line 7. In this way, the inverter 6 performs bidirectional power conversion between the DC power source 2 and the motor generator 3.
  • the inverter 6 is configured with three-phase upper and lower arm circuits 9.
  • the upper and lower arm circuits 9 are sometimes referred to as legs.
  • the upper and lower arm circuits 9 each have an upper arm 9H and a lower arm 9L.
  • the upper arm 9H and the lower arm 9L are connected in series between the P line 7 and the N line 8, with the upper arm 9H on the P line 7 side.
  • a connection point between upper arm 9H and lower arm 9L is connected to a corresponding phase winding 3a of motor generator 3 via output line 10.
  • Inverter 6 has six arms. At least a portion of each of the P line 7, the N line 8, and the output line 10 is constituted by a conductive member such as a bus bar.
  • each arm includes an IGBT 11 that is a switching element and a diode 12 for freewheeling.
  • IGBT is an abbreviation for Insulated Gate Bipolar Transistor.
  • an n-channel type IGBT 11 is used.
  • the diode 12 is connected in antiparallel to the corresponding IGBT 11.
  • the collector of the IGBT 11 is connected to the P line 7.
  • the emitter of the IGBT 11 is connected to the N line 8.
  • the emitter of the IGBT 11 in the upper arm 9H and the collector of the IGBT 11 in the lower arm 9L are connected to each other.
  • the anode of the diode 12 is connected to the emitter of the corresponding IGBT 11, and the cathode is connected to the collector.
  • the power conversion device 4 may further include a converter as a power conversion circuit.
  • a converter is a DC-DC conversion circuit that converts DC voltage to DC voltages of different values.
  • a converter is provided between DC power supply 2 and smoothing capacitor 5.
  • the converter includes, for example, a reactor and the above-mentioned upper and lower arm circuits 9. According to this configuration, it is possible to raise and lower the voltage.
  • the power conversion device 4 may include a filter capacitor that removes power supply noise from the DC power supply 2.
  • a filter capacitor is provided between the DC power supply 2 and the converter.
  • the power conversion device 4 may include a drive circuit for switching elements that constitute the inverter 6 and the like.
  • the drive circuit supplies a drive voltage to the gate of the IGBT 11 of the corresponding arm based on a drive command from the control circuit.
  • the drive circuit drives the corresponding IGBT 11 by applying a drive voltage, that is, turns it on and turns it off.
  • a drive circuit is sometimes referred to as a driver.
  • the power conversion device 4 may include a control circuit for switching elements.
  • the control circuit generates a drive command for operating the IGBT 11 and outputs it to the drive circuit.
  • the control circuit generates a drive command based on a torque request input from a host ECU (not shown) and signals detected by various sensors.
  • Various sensors include, for example, a current sensor, a rotation angle sensor, and a voltage sensor.
  • the current sensor detects the phase current flowing through the winding 3a of each phase.
  • the rotation angle sensor detects the rotation angle of the rotor of the motor generator 3.
  • the voltage sensor detects the voltage across the smoothing capacitor 5.
  • the control circuit outputs, for example, a PWM signal as a drive command.
  • the control circuit includes, for example, a processor and a memory.
  • ECU is an abbreviation for Electronic Control Unit.
  • PWM is an abbreviation for Pulse Width Modulation.
  • FIG. 2 is a plan view showing the semiconductor device.
  • FIG. 2 is a top plan view of the semiconductor device.
  • FIG. 3 is a sectional view taken along line III-III in FIG. 2.
  • FIG. 4 is a sectional view taken along line IV-IV in FIG. 2.
  • FIG. 5 is a plan view showing the semiconductor element.
  • the thickness direction of the semiconductor element is referred to as the Z direction.
  • One direction perpendicular to the Z direction is defined as the X direction.
  • the direction perpendicular to both the Z direction and the X direction is defined as the Y direction.
  • the planar shape is the shape viewed from the Z direction, in other words, the shape along the XY plane defined by the X direction and the Y direction. Further, a planar view from the Z direction may be simply referred to as a planar view.
  • the semiconductor device 20 includes a sealing body 30, a semiconductor element 40, wiring members 50 and 60, a conductive spacer 70, and an external connection terminal 80.
  • the semiconductor device 20 further includes a bonding wire 90 and a bonding material 100.
  • the semiconductor device 20 constitutes one of the arms described above. That is, the two semiconductor devices 20 constitute the upper and lower arm circuit 9 for one phase.
  • the sealing body 30 seals some of the other elements constituting the semiconductor device 20. The remaining parts of the other elements are exposed outside the sealing body 30.
  • the sealing body 30 is made of resin, for example.
  • An example of the resin is an epoxy resin.
  • the sealing body 30 is molded from resin by, for example, a transfer molding method. Such a sealing body 30 is sometimes referred to as a sealing resin body, a mold resin, a resin molded body, or the like.
  • the sealing body 30 may be formed using gel, for example. The gel is filled (arranged) in opposing regions of the pair of wiring members 50 and 60, for example.
  • the sealing body 30 has a substantially rectangular shape in plan view.
  • the sealing body 30 has one surface 30a and a back surface 30b, which is a surface opposite to the one surface 30a in the Z direction, as a surface forming an outline.
  • One surface 30a and back surface 30b are, for example, substantially flat surfaces.
  • It also has side surfaces 30c, 30d, 30e, and 30f that are continuous with the one surface 30a and the back surface 30b.
  • the side surface 30c is a surface from which the main terminals 81 and 82 of the external connection terminal 80 protrude.
  • the side surface 30d is a surface opposite to the side surface 30c in the Y direction.
  • the side surface 30d is a surface from which the signal terminal 83 projects.
  • the side surfaces 30e and 30f are surfaces from which the external connection terminal 80 does not protrude.
  • the side surface 30e is a surface opposite to the side surface 30f in the X direction.
  • the semiconductor element 40 includes a semiconductor substrate 41, an emitter electrode 42, a collector electrode 43, and a pad 44.
  • the semiconductor element 40 is sometimes referred to as a semiconductor chip.
  • the semiconductor substrate 41 is made of a material such as silicon (Si) or a wide bandgap semiconductor having a wider bandgap than silicon, and has a vertical element formed thereon. Examples of wide bandgap semiconductors include silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga 2 O 3 ), and diamond.
  • the vertical element is configured to allow a main current to flow in the thickness direction of the semiconductor substrate 41 (semiconductor element 40), that is, in the Z direction.
  • the vertical elements of this embodiment are the IGBT 11 and the diode 12 that constitute one arm.
  • the vertical element is an IGBT in which diodes 12 are connected in antiparallel, that is, an RC-IGBT. RC is an abbreviation for Reverse Conducting.
  • the vertical element is a heating element that generates heat when energized.
  • a gate electrode (not shown) is formed on the semiconductor substrate 41.
  • the gate electrode has, for example, a trench structure.
  • the semiconductor substrate 41 has one side 41a and a back side 41b as plate surfaces on which the main electrode is provided.
  • One surface 41a is a surface of the semiconductor substrate 41 on the one surface 30a side of the sealed body 30.
  • the back surface 41b is a surface opposite to the one surface 41a in the thickness direction.
  • the emitter electrode 42 which is one of the main electrodes, is arranged on one surface 41a of the semiconductor substrate 41.
  • a collector electrode 43 which is another one of the main electrodes, is arranged on the back surface 41b of the semiconductor substrate 41.
  • the emitter electrode 42 corresponds to a first main electrode
  • the collector electrode 43 corresponds to a second main electrode.
  • a current flows between the main electrodes, that is, between the emitter electrode 42 and the collector electrode 43.
  • the emitter electrode 42 also serves as an anode electrode of the diode 12.
  • the collector electrode 43 also serves as the cathode electrode of the diode 12.
  • the collector electrode 43 is formed over almost the entire back surface 41b of the semiconductor substrate 41.
  • the emitter electrode 42 is formed on a portion of one surface 41a of the semiconductor substrate 41.
  • the pad 44 is a signal electrode.
  • the pad 44 is formed on one surface 41a of the semiconductor substrate 41 in a region different from the region where the emitter electrode 42 is formed.
  • the pad 44 is formed at the end opposite to the region where the emitter electrode 42 is formed in the Y direction.
  • the pad 44 is provided in parallel with the emitter electrode 42 in the Y direction.
  • Pad 44 includes at least gate pad 44G.
  • the semiconductor element 40 has five pads 44.
  • the gate pad 44G has a gate pad 44G for detecting the emitter potential, for detecting the cathode potential of a temperature-sensitive diode (not shown) included in the semiconductor element 40, for detecting the anode potential, and for current sensing.
  • the five pads 44 are lined up along the X direction. Details of the semiconductor element 40 will be described later.
  • the wiring member 50 is electrically connected to the emitter electrode 42 and provides a wiring function.
  • the wiring member 60 is electrically connected to the collector electrode 43 and provides a wiring function.
  • the wiring members 50 and 60 are arranged to sandwich the semiconductor element 40 in the Z direction.
  • the wiring members 50 and 60 are arranged so that at least a portion thereof faces each other in the Z direction.
  • the wiring members 50 and 60 include the semiconductor element 40 in a plan view.
  • the wiring members 50 and 60 provide a heat radiation function of radiating heat generated by the semiconductor element 40.
  • the wiring members 50 and 60 are sometimes referred to as heat sinks, heat sinks, or the like.
  • the wiring members 50 and 60 of this embodiment are metal plates made of a metal with good conductivity such as Cu or Cu alloy.
  • the metal plate is provided, for example, as part of a lead frame. Instead of the metal plate, a substrate may be used in which metal bodies are arranged on both sides of an insulating base material.
  • the wiring members 50 and 60 may include a plating film of Ni, Au, or the like on the metal surface.
  • the wiring member 50 has a facing surface 50a that is a surface on the semiconductor element 40 side, and a back surface 50b that is a surface opposite to the facing surface 50a.
  • the wiring member 60 also has a facing surface 60a and a back surface 60b.
  • the wiring members 50 and 60 have, for example, a substantially rectangular planar shape.
  • the back surfaces 50b and 60b of the wiring members 50 and 60 are exposed from the sealing body 30.
  • the back surfaces 50b and 60b are sometimes referred to as heat radiation surfaces, exposed surfaces, and the like.
  • the back surface 50b of the wiring member 50 is substantially flush with the one surface 30a of the sealing body 30.
  • the back surface 60b of the wiring member 60 is substantially flush with the back surface 30b of the sealing body 30.
  • the conductive spacer 70 is interposed between the semiconductor element 40 and the wiring member 50.
  • the conductive spacer 70 provides a spacer function to ensure a predetermined distance between the semiconductor element 40 and the wiring member 50.
  • the conductive spacer 70 ensures a height for electrically connecting the corresponding signal terminal 83 to the pad 44 of the semiconductor element 40 .
  • the conductive spacer 70 is located in the middle of the electrical and thermal conduction path between the emitter electrode 42 of the semiconductor element 40 and the wiring member 50, and provides a wiring function and a heat dissipation function.
  • the conductive spacer 70 corresponds to a conductive member connected to the first main electrode via the sintered member.
  • the conductive spacer 70 includes a metal material with good electrical conductivity and thermal conductivity, such as Cu (copper).
  • the conductive spacer 70 may have a plating film on its surface.
  • the conductive spacer 70 is sometimes referred to as a terminal, a terminal block, a metal block, or the like.
  • the semiconductor device 20 includes the same number of conductive spacers 70 as the semiconductor elements 40. Conductive spacers 70 are individually connected to semiconductor elements 40 .
  • the conductive spacer 70 is, for example, a columnar body.
  • the conductive spacer 70 has a shape corresponding to an opening 451 described later in plan view.
  • the conductive spacer 70 has a size that approximately matches or is slightly smaller than the opening 451.
  • the external connection terminal 80 is a terminal for electrically connecting the semiconductor device 20 to external equipment.
  • the external connection terminal 80 is formed using a metal material with good conductivity, such as copper.
  • the external connection terminal 80 is, for example, a plate material.
  • the external connection terminal 80 is sometimes called a lead.
  • the external connection terminal 80 includes main terminals 81 and 82 and a signal terminal 83.
  • the main terminals 81 and 82 are external connection terminals 80 electrically connected to the main electrodes of the semiconductor element 40.
  • the main terminal 81 is electrically connected to the emitter electrode 42.
  • the main terminal 81 is sometimes referred to as an emitter terminal.
  • the main terminal 81 is connected to the emitter electrode 42 via the wiring member 50.
  • the main terminal 81 is connected to one end of the wiring member 50 in the Y direction.
  • the thickness of the main terminal 81 is thinner than that of the wiring member 50.
  • the main terminal 81 is connected to the wiring member 50 so as to be, for example, approximately flush with the opposing surface 50a.
  • the main terminal 81 may be connected by being provided continuously and integrally with the wiring member 50, or may be provided as a separate member and connected by joining.
  • the main terminal 81 of this embodiment is provided integrally with the wiring member 50 as a part of the lead frame.
  • the main terminal 81 extends from the wiring member 50 in the Y direction and projects outward from the side surface 30c of the sealing body 30.
  • the main terminal 81 has a bent part in the middle of the portion covered by the sealing body 30, and protrudes from near the center in the Z direction on the side surface 30c.
  • the main terminal 82 is electrically connected to the collector electrode 43.
  • Main terminal 82 is sometimes referred to as a collector terminal.
  • the main terminal 82 is connected to the collector electrode 43 via the wiring member 60.
  • the main terminal 82 is connected to one end of the wiring member 60 in the Y direction.
  • the thickness of the main terminal 82 is thinner than that of the wiring member 60.
  • the main terminal 82 is connected to the wiring member 60, for example, so as to be substantially flush with the opposing surface 60a.
  • the main terminal 82 may be continuously and integrally provided with the wiring member 60, or may be provided as a separate member and connected by joining.
  • the main terminal 82 of this embodiment is provided integrally with the wiring member 60 as a part of a lead frame separate from the main terminal 81.
  • the main terminal 82 extends from the wiring member 60 in the Y direction and projects outward from the same side surface 30c as the main terminal 81.
  • the main terminal 82 also has a bent part in the middle of the portion covered by the sealing body 30, and protrudes from near the center in the Z direction on the side surface 30c.
  • the two main terminals 81 and 82 are arranged side by side in the X direction so that their side surfaces face each other.
  • the signal terminal 83 is electrically connected to the corresponding pad 44 of the semiconductor element 40.
  • the signal terminal 83 is electrically connected to the pad 44 via a bonding wire 90.
  • the signal terminal 83 extends in the Y direction and projects outward from the side surface 30d of the sealing body 30.
  • the semiconductor device 20 of this embodiment includes five signal terminals 83 corresponding to the pads 44.
  • the five signal terminals 83 are arranged in line in the X direction.
  • the signal terminal 83 is configured, for example, on a common lead frame with the wiring member 60 and the main terminal 82.
  • the plurality of signal terminals 83 are electrically isolated from each other by cutting tie bars (not shown).
  • the bonding material 100 is interposed between the elements constituting the semiconductor device 20 and bonds the elements together.
  • the semiconductor device 20 includes a plurality of bonding materials 100.
  • One of the bonding materials 100 is interposed between the emitter electrode 42 and the conductive spacer 70 to bond the emitter electrode 42 and the conductive spacer 70 together.
  • the other bonding material 100 is interposed between the conductive spacer 70 and the wiring member 50 and joins the conductive spacer 70 and the wiring member 50 together.
  • the other bonding material 100 is interposed between the collector electrode 43 of the semiconductor element 40 and the wiring member 60 to bond the collector electrode 43 and the wiring member 60 together.
  • the bonding material 100 interposed between the emitter electrode 42 and the conductive spacer 70 is a sintered member 101 as described later.
  • the other bonding material 100 may be a sintered member, or may be a bonding material different from the sintered member, such as solder.
  • the semiconductor element 40 constituting one arm is sealed by the sealing body 30.
  • the sealing body 30 integrally seals the semiconductor element 40, a portion of the wiring member 50, a portion of the wiring member 60, a conductive spacer 70, and a portion of each of the external connection terminals 80.
  • the semiconductor element 40 is arranged between the wiring members 50 and 60 in the Z direction.
  • the semiconductor element 40 is sandwiched between wiring members 50 and 60 that are arranged opposite to each other. Thereby, the heat of the semiconductor element 40 can be radiated to both sides in the Z direction.
  • the semiconductor device 20 has a double-sided heat dissipation structure.
  • the back surface 50b of the wiring member 50 is substantially flush with the one surface 30a of the sealing body 30.
  • the back surface 60b of the wiring member 60 is substantially flush with the back surface 30b of the sealing body 30. Since the back surfaces 50b and 60b are exposed surfaces, heat dissipation can be improved.
  • FIG. 6 is a sectional view taken along line VI-VI in FIG. 5.
  • a gate wiring 46 which will be described later, is shown by a broken line.
  • the semiconductor substrate 41 has a substantially rectangular planar shape. As shown in FIGS. 5 and 6, the semiconductor substrate 41 has an active region 411 and an outer peripheral region 412. The two-dot chain line shown in FIGS. 5 and 6 indicates the boundary between the active region 411 and the outer peripheral region 412.
  • the active region 411 is a region where vertical elements are formed.
  • the active region 411 is sometimes referred to as a main region, a main cell region, a cell region, an element region, an element formation region, or the like.
  • the active region 411 has, for example, a substantially rectangular planar shape.
  • the active region 411 is aligned with the pad 44 in the Y direction.
  • the active region 411 is provided with a plurality of cells (unit structures). A plurality of cells are connected in parallel to form an RC-IGBT.
  • the outer peripheral region 412 surrounds the active region 411 in plan view.
  • a pressure-resistant structure is formed in the outer peripheral region 412.
  • a guard ring 413 is formed.
  • the guard ring 413 has an annular shape in a plan view so as to surround the active region 411 .
  • the semiconductor element 40 has a protective film 45 disposed on one surface 41a of the semiconductor substrate 41.
  • the protective film 45 is an insulating film provided on one surface 41a of the semiconductor substrate 41 so as to cover the peripheral portion of the emitter electrode 42, specifically the base electrode 422 described below.
  • polyimide, silicon nitride film, etc. can be used as the material for the protective film 45.
  • the protective film 45 has an opening 451.
  • the opening 451 defines a joining area between the emitter electrode 42 and the sintered member 101.
  • the opening 451 is a through hole that penetrates the protective film 45 in the Z direction.
  • the opening 451 is provided so as to overlap the emitter electrode 42 in plan view.
  • the opening 451 substantially coincides with the active region 411 in plan view.
  • the planar shape of the opening 451, that is, the inner circumferential surface of the protective film 45 that defines the opening 451 has a substantially rectangular planar shape.
  • the protective film 45 has an opening 452 that defines the bonding area in the pad 44 .
  • the emitter electrode 42 has an exposed portion 421 that is exposed from the opening 451 of the protective film 45 and provides a bonding region.
  • the exposed portion 421 forms a joint with the sintered member 101.
  • the external contour of the exposed portion 421 matches the external contour of the opening 451 in a plan view.
  • the exposed portion 421 is arranged on the active region 411 of the semiconductor substrate 41.
  • the emitter electrode 42 has a multilayer structure.
  • the emitter electrode 42 has a base electrode 422 and a connection electrode 423.
  • the pad 44 also has the same configuration as the emitter electrode 42.
  • the base electrode 422 is a metal layer placed on the semiconductor substrate 41 side in the multilayered emitter electrode 42.
  • the base electrode 422 is formed using, for example, a material whose main component is Al (aluminum).
  • the base electrode 422 of this embodiment is formed using an Al alloy such as AlSi or AlSiCu.
  • the base electrode 422 is sometimes referred to as a wiring electrode, a base layer, a first metal layer, or the like.
  • the base electrode 422 in plan view, includes the active region 411 and extends onto the outer peripheral region 412.
  • the base electrode 422 is connected to the emitter and anode of the vertical element.
  • the base electrode 422 has a peripheral portion that surrounds the exposed portion 421 in plan view.
  • the peripheral portion is a portion of the base electrode 422 that overlaps with the protective film 45.
  • the protective film 45 is disposed on one surface 41a of the semiconductor substrate 41 so as to cover the peripheral portion of the base electrode 422.
  • connection electrode 423 is stacked on the base electrode 422.
  • the connection electrode 423 is also referred to as a top electrode, an upper electrode, an upper layer electrode, a top layer, or a second metal layer.
  • the connection electrode 423 contains at least a noble metal such as Au (gold), Ag (silver), Pt (platinum), or Pd (palladium) for bonding with the sintered member 101.
  • the connection electrode 423 may contain a base metal as well as a noble metal.
  • connection electrode 423 of this embodiment contains Ni (nickel). Ni is harder than the Al alloy that constitutes the base electrode 422.
  • Connection electrode 423 includes Ni and a noble metal, such as Au or Ag.
  • the connection electrode 423 is formed in multiple layers by, for example, a plating method. At least a portion of the noble metal of the connection electrode 423 diffuses into the sintered member 101 during bonding.
  • connection electrode 423 is stacked on the base electrode 422 in the opening 451 of the protective film 45 .
  • the outer peripheral end of the connection electrode 423 is in contact with the inner peripheral surface of the protective film 45 that defines the opening 451.
  • the bonding surface of the exposed portion 421 of the emitter electrode 42 is flush with at least the surrounding portion of the opening 451 of the upper surface 45a of the protective film 45.
  • the peripheral portion of the opening 451 is a predetermined range from the opening end.
  • the peripheral portion is a portion within a tolerance range in which the sintered member 101 may be misaligned with respect to the bonding surface of the exposed portion 421.
  • substantially the entire upper surface 45a of the protective film 45 is substantially flush with the bonding surface of the exposed portion 421.
  • flush refers to a state in which the positions in the Z direction are the same.
  • the protective film 45 is arranged on the guard ring 413 in plan view.
  • the protective film 45 is arranged on one surface 41a so as to cover the guard ring 413.
  • the protective film 45 covers a wiring portion located at a position that does not overlap the emitter electrode 42 and the pad 44 in plan view.
  • the semiconductor element 40 includes a gate wiring 46 as a wiring part.
  • the gate wiring 46 electrically connects the gate electrode of the IGBT 11 formed on the semiconductor substrate 41 and the gate pad 44G.
  • the gate wiring 46 is a metal wiring formed using a material whose main component is Al (aluminum), for example.
  • the gate wiring 46 is electrically connected to the gate electrode via a polysilicon wiring (not shown) formed by introducing impurities into polysilicon.
  • the polysilicon wiring is arranged between the emitter electrode 42 and the semiconductor substrate 41.
  • the entire length of the gate wiring 46 in this embodiment is arranged on the outer peripheral region 412.
  • the gate wiring 46 is provided in a ring shape so as to surround the active region 411 . At least a portion of the gate wiring 46 is arranged around the opening 451 described above.
  • FIG. 7 corresponds to FIG. 6.
  • FIG. 7 shows an ideal bonding structure between the semiconductor element 40 and the conductive spacer 70.
  • the sintered member 101 is interposed between the emitter electrode 42 of the semiconductor element 40 and the conductive spacer 70.
  • the sintered member 101 joins the emitter electrode 42 and the conductive spacer 70.
  • the sintered member 101 is made of Ag or Cu.
  • the sintered member 101 is a sintered body made of Ag particles or Cu particles.
  • the sintered member 101 can be joined at a lower temperature than solder.
  • the sintered member 101 is arranged so as to substantially match the bonding surface of the exposed portion 421 of the emitter electrode 42 in plan view.
  • the sintered member 101 is arranged so that its outer peripheral end substantially coincides with the inner peripheral surface of the protective film 45 that defines the opening 451.
  • the protective film 45 ideally includes the sintered member 101 in plan view.
  • the conductive spacer 70 has a metal film (not shown) on the joint surface with the sintered member 101.
  • the metal film contains at least a precious metal, like the connection electrode 423.
  • the metal film is a plating film containing Ni and a precious metal, such as Au or Ag.
  • the conductive spacer 70 has, for example, a substantially rectangular shape in plan view.
  • the outer periphery of the conductive spacer 70 is positioned outside or substantially coincident with the outer periphery of the sintered member 101 in plan view.
  • FIG. 8 is a cross-sectional view showing the joining method.
  • FIG. 8 corresponds to FIG. 7.
  • a sintered sheet 101S is used in order to form the sintered member 101.
  • the sintered sheet 101S is sometimes referred to as a sintered film.
  • the sintered sheet 101S contains Ag or Cu.
  • the sintered sheet 101S is placed on the exposed portion 421 of the emitter electrode 42 of the semiconductor element 40.
  • the sintered sheet 101S has a predetermined size smaller than the opening 451 of the protective film 45 in plan view before being pressurized.
  • conductive spacers 70 are placed on the sintered sheet 101S to form a laminate. Then, while heating, the laminate is pressurized from the conductive spacer 70 side using a pressurizing device (not shown). As a result, the sintered sheet 101S is expanded between the facing surfaces of the exposed portion 421 of the emitter electrode 42 and the conductive spacer 70, becomes thinner, and is sintered to become the sintered member 101.
  • the size of the sintered sheet 101S of the sintered member 101 is determined so that the above-described predetermined positional relationship is achieved in the joined state.
  • Sintered members are formed by heating below the melting point. Sintered members do not become molten like solder during bonding. Sintered members have lower wettability with respect to main electrodes and conductive members than solder. The sintered member does not wet and spread on the surface of the main electrode or the surface of the conductive member during bonding, unlike solder. A sintered member may be placed on the protective film.
  • 9 and 10 show reference examples. 9 and 10 both show the joining method. 9 and 10 correspond to FIG. 8.
  • the reference numeral of each element is such that r is added to the end of the reference numeral of the related element of the semiconductor device 20.
  • the upper surface 45ar of the protective film 45r is located above the bonding surface of the exposed portion 421r of the emitter electrode 42r in the Z direction. As a result, a step is formed between the upper surface 45a and the bonding surface of the exposed portion 421r, with the protective film 45r side being convex.
  • the size of the sintered sheet 101Sr is determined so that at least a portion of the sintered member in the circumferential direction contacts the inner circumferential surface of the protective film in the bonded state.
  • the sintered sheet 101Sr is misaligned within the manufacturing tolerance and placed so as to rest on the upper surface 45ar of the protective film 45r, stress will be concentrated on the protective film 45r due to the pressure applied during sinter bonding. This may result in damage to the protective film 45r, wiring parts such as the gate wiring 46r covered by the protective film 45r, and even the substrate part directly below the protective film 45r. Note that a similar problem may occur if a configuration is used in which a portion of the sintered sheet 101Sr is placed on the upper surface 45ar of the protective film 45r due to misalignment.
  • the size of the sintered sheet 101Sr is determined so that even if the sintered sheet 101Sr is misaligned within manufacturing tolerances, it will not be placed on the upper surface 45ar of the protective film 45r. In other words, the size of the sintered sheet 101Sr is small. For this reason, after sintering and joining, the cross-sectional area of the sintered member (not shown) becomes smaller, resulting in increased thermal resistance and current density.
  • the upper surface 45a of the protective film 45 is flush with the bonding surface of the exposed portion 421 of the emitter electrode 42 in the Z direction. In other words, the position of the upper surface 45a in the Z direction is approximately equal to the position of the bonding surface of the exposed portion 421.
  • the semiconductor element 40 of this embodiment has a gate wiring 46 as a wiring portion that is arranged at a position that does not overlap the emitter electrode 42 in a plan view and is covered by a protective film 45.
  • the semiconductor element 40 also has a guard ring 413 as a pressure-resistant structure portion formed in the peripheral region 412.
  • a guard ring 413 as a pressure-resistant structure portion formed in the peripheral region 412.
  • the upper surface 45a of the protective film 45 is flush with the bonding surface of the exposed portion 421 of the emitter electrode 42, at least in the peripheral portion of the opening 451.
  • the peripheral portion of the upper surface 45a of the protective film 45 around the opening 451 may be flush with the bonding surface of the exposed portion 421, and the other portion may be located above the bonding surface of the exposed portion 421.
  • This embodiment is a modification based on the previous embodiment, and the description of the previous embodiment can be used.
  • the upper surface 45a of the protective film 45 was positioned flush with the upper surface of the emitter electrode 42.
  • the upper surface 45a of the protective film 45 may be positioned not flush with the upper surface of the emitter electrode 42.
  • FIG. 12 is a cross-sectional view showing the semiconductor element 40 in the semiconductor device 20 according to this embodiment.
  • FIG. 12 corresponds to FIG. 6.
  • the portion of the upper surface 45a of the protective film 45 surrounding the opening 451 is located closer to the surface 41a than the bonding surface of the exposed portion 421 of the emitter electrode 42 in the Z direction.
  • the other portions of the upper surface 45a are also located closer to the surface 41a than the bonding surface of the exposed portion 421 of the emitter electrode 42.
  • the entire upper surface 45a of the protective film 45 is closer to the surface 41a than the bonding surface of the exposed portion 421 of the emitter electrode 42.
  • the height of the protective film 45 to the top surface with respect to the one surface 41 a is lower than that of the emitter electrode 42 .
  • the upper surface 45a of the protective film 45 is located below the upper surface of the emitter electrode 42.
  • the upper surface 45a of the protective film 45 is located closer to the one surface 41a of the semiconductor substrate 41 than the bonding surface of the exposed portion 421 of the emitter electrode 42 in the Z direction. Due to this positional relationship, even if the sintered sheet 101S is displaced, it does not come into contact with the periphery of the opening of the upper surface 45a, or even if it does, the stress acting on the protective film 45 becomes smaller. Therefore, the reliability of the semiconductor device 20 can be further improved.
  • At least a portion of the upper surface 45a of the protective film 45 surrounding the opening 451 may be located below the bonding surface of the exposed portion 421 of the emitter electrode 42.
  • a portion of the upper surface 45a of the protective film 45 around the opening 451 may be placed below the bonding surface of the exposed portion 421, and the other portion may be placed above the bonding surface of the exposed portion 421.
  • a portion of the upper surface 45a of the protective film 45 around the opening 451 is located below the bonding surface of the exposed portion 421, and the other portion is flush with or less than the bonding surface of the exposed portion 421.
  • the above-described positional relationship may be satisfied while the surface has irregularities.
  • FIG. 13 is a plan view showing the semiconductor element 40 in the semiconductor device 20 according to this embodiment.
  • FIG. 13 corresponds to FIG. 5.
  • FIG. 14 is a sectional view taken along the line XIV-XIV in FIG. 13.
  • FIG. 14 shows a bonding structure between the semiconductor element 40 and the conductive spacer 70.
  • FIG. 14 corresponds to FIG. 7.
  • the protective film 45 has an outer peripheral portion 453 and a partition portion 454.
  • the outer peripheral portion 453 is arranged to substantially coincide with the outer peripheral region 412 in a plan view.
  • the division section 454 divides the emitter electrode 42 into a plurality of sections.
  • the partition section 454 of this embodiment is provided so as to substantially divide the emitter electrode 42 into two in the X direction.
  • the dividing portion 454 divides the opening 451 into two.
  • the partition portion 454 passes through the center of the semiconductor element 40 and extends in the Y direction. One of the ends of the partition 454 is connected to the outer peripheral part 453 on the pad 44 side, and the other end is connected to the outer peripheral part 453 on the opposite side from the pad 44.
  • the gate wiring 46 has an outer wiring part 461 and a partition wiring part 462.
  • the outer circumferential wiring portion 461 is arranged at a position overlapping the outer circumferential portion 453 in a plan view.
  • the outer peripheral wiring portion 461 corresponds to the gate wiring 46 shown in the preceding embodiment.
  • the outer peripheral wiring portion 461 has a rectangular ring shape.
  • the partition wiring section 462 is arranged at a position overlapping with the partition section 454 in plan view.
  • the partition wiring section 462 passes through the center of the semiconductor element 40 and extends in the Y direction. One end of the divided wiring section 462 is connected to the outer peripheral wiring section 461 on the pad 44 side, and the other end is connected to the outer peripheral wiring section 461 on the opposite side from the pad 44.
  • the divided wiring section 462 is arranged between the two divided emitter electrodes 42. In the direction in which the divided exposed portions 421 and the divided wiring portions 462 are lined up, that is, in the X direction, the width of the divided wiring portions 462 is narrower than the width of each of the exposed portions 421 . In the X direction, the width of the partition section 454 is narrower than the width of each of the exposed sections 421.
  • the sintered member 101 is arranged across a plurality of partitioned exposed parts 421.
  • the sintered member 101 is arranged not only at a position overlapping each of the exposed parts 421 in a plan view but also at a position overlapping with the partition part 454.
  • the sintered member 101 is located above the upper surface 45a of the partition 454.
  • the area around the opening 451 of the protective film 45 includes a partition 454 .
  • at least a portion of the upper surface 45 a of the protective film 45 around the opening 451 is flush with or less than the bonding surface of the exposed portion 421 .
  • the upper surface 45a of the peripheral portion including the partition portion 454 is located below the joint surface of the exposed portion 421.
  • the other configurations of the semiconductor device 20 are similar to those described in the preceding embodiments.
  • the semiconductor device 20 of the present embodiment not only the upper surface 45a of the peripheral portion of the opening 451 in the outer peripheral region 412 but also the upper surface 45a of the partitioned portion 454 covering the partitioned wiring portion 462 is connected to the bonding surface of the exposed portion 421. It is located at less than the same level.
  • the sintered sheet 101S sintered member 101
  • the width of the divided wiring section 462 is narrower than the width of each of the exposed sections 421.
  • the wiring section covered by the partition section 454 is not limited to the partition wiring section 462 which is the gate wiring 46 . Any wiring may be used as long as it does not overlap the emitter electrode 42 and overlaps the partition 454 in plan view.
  • the arrangement of the partition portions 454 is not limited to the above example.
  • the exposed portion 421 may be divided into four sections by three partition sections 454.
  • the partition portion 454 divides the exposed portion 421 into approximately four equal parts in the X direction.
  • FIG. 15 corresponds to FIG. 13.
  • the partition portions 454 may be arranged in a substantially cross shape in plan, for example, so as to divide the exposed portion 421 into approximately four equal parts.
  • the partition 454 includes a portion extending in the X direction and a portion extending in the Y direction.
  • Spatial relative terms such as “in”, “out”, “behind”, “below”, “low”, “above”, “high” etc. refer to a single element or feature as illustrated. It is used herein to facilitate description that describes relationships to other elements or features. Spatially relative terms may be intended to encompass different orientations of the device during use or operation in addition to the orientation depicted in the figures. For example, when the device in the figures is turned over, elements described as being “below” or “beneath” other elements or features are oriented “above” the other elements or features. Thus, the term “bottom” can encompass both orientations, top and bottom. The device may be oriented in other directions (rotated 90 degrees or other orientations) and the spatially relative descriptors used in this specification shall be interpreted accordingly. .
  • the vehicle drive system 1 is not limited to the above configuration.
  • one motor generator 3 is provided, the present invention is not limited to this.
  • a plurality of motor generators may be provided.
  • the power conversion device 4 includes the inverter 6 as a power conversion section, the present invention is not limited to this.
  • a configuration may include a plurality of inverters.
  • the configuration may include at least one inverter and a converter. It may also include only a converter.
  • the configuration of the semiconductor device 20 is not limited to the above example.
  • the semiconductor device 20 may include at least a semiconductor element having dissimilar electrodes on both sides, a conductive member, and a sintered member that bonds the first main electrode exposed from the protective film to the conductive member.
  • the switching element is not limited to the IGBT 11.
  • a MOSFET may be used.
  • MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor.
  • a protrusion may be provided on the wiring member 50.
  • the wiring member 50 corresponds to a conductive member.
  • the present invention is not limited to this. It can also be applied to a single-sided heat dissipation structure.
  • the collector electrode 43 is connected to a heat sink or a metal body of a substrate, and the emitter electrode 42 is connected to a lead.
  • the lead corresponds to the conductive member.
  • the semiconductor device 20 may include a plurality of semiconductor elements 40 forming one arm. That is, a plurality of semiconductor elements 40 may be connected in parallel to each other to form one arm. Furthermore, the semiconductor device 20 may include a plurality of semiconductor elements 40 that constitute the upper and lower arm circuits 9 for one phase. A plurality of semiconductor elements 40 forming a multi-phase upper and lower arm circuit 9 may be provided.
  • the present invention is not limited to this. At least one of the back surfaces 50b and 60b may be covered with the sealing body 30. At least one of the back surfaces 50b and 60b may be covered with an insulating member (not shown) that is separate from the sealing body 30.
  • the semiconductor device 20 may be configured without the sealing body 30.
  • the configuration of the emitter electrode 42 which is the first main electrode, is not limited to the above example.
  • the emitter electrode 42 may have an intermediate electrode 424.
  • the intermediate electrode 424 is arranged between the base electrode 422 whose main component is Al and the connection electrode 423.
  • the intermediate electrode 424 is formed using a material containing Cu as a main component.
  • the emitter electrode 42 is connected to the semiconductor substrate 41 through a contact hole provided in an insulating film 47 such as a silicon oxide film.
  • the base electrode 422A and the gate wiring 46A are formed using a material containing Cu as a main component.
  • a connection electrode 423 is laminated on a base electrode 422A whose main component is Cu.
  • the gate wiring 46A whose main component is Cu is covered with a protective film 45.
  • 16 and 17 show an example in which the upper surface 45a of the protective film 45 is flush with the bonding surface of the exposed portion 421. However, it goes without saying that the upper surface 45a of the protective film 45 may be located below the bonding surface of the exposed portion 421.
  • the semiconductor element has a wiring portion (46, 46A) that is disposed on the one surface at a position that does not overlap with the first main electrode in a plan view in the thickness direction, and is covered with the protective film.
  • the semiconductor device according to Technical Idea 1 or Technical Idea 2.
  • the protective film has a division part (454) that divides the exposed part (421) of the first main electrode into a plurality of parts,
  • the sintered member is arranged across the plurality of exposed parts,
  • the wiring portion includes a partitioned wiring portion (462) arranged at a position overlapping with the partitioned portion in a plan view in the thickness direction,
  • the semiconductor device according to technical idea 3 wherein the width of the divided wiring portion is narrower than the width of the exposed portion.
  • the semiconductor substrate includes an active region (411) that is an element formation region, an outer peripheral region (412) surrounding the active region in plan view in the thickness direction, and a voltage-resistant structure (413) provided in the outer peripheral region. and, The semiconductor device according to any one of technical ideas 1 to 4, wherein the protective film covers the voltage-resistant structure.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A semiconductor element (40) comprises: an emitter electrode (42) disposed on one surface of a semiconductor substrate (41); and a collector electrode (43) disposed on the reverse surface. The one surface of the semiconductor substrate (41) is provided with a protective film (45) having an opening (451) that exposes the emitter electrode (42) to enable connection. A sintered member (101) is interposed between the emitter electrode (42) and a conductive spacer (70), and connects the emitter electrode (42) and the conductive spacer (70). At least the peripheral portion of the opening (451) among the upper surface (45a) of the protective film (45) is positioned as flush with or lower than the connection surface of the emitter electrode (42) in the Z direction.

Description

半導体装置semiconductor equipment 関連出願の相互参照Cross-reference of related applications
　この出願は、２０２２年９月２１日に日本に出願された特許出願第２０２２－１５０５８４号を基礎としており、基礎の出願の内容を、全体的に、参照により援用している。 This application is based on Patent Application No. 2022-150584 filed in Japan on September 21, 2022, and the content of the underlying application is incorporated by reference in its entirety.
　この明細書における開示は、半導体装置に関する。 The disclosure in this specification relates to a semiconductor device.
　特許文献１は、両面に主電極を有する半導体チップと、導電部材と、主電極と導電部材とを接合する焼結層を備えた半導体装置を開示している。先行技術文献の記載内容は、この明細書における技術的要素の説明として、参照により援用される。 Patent Document 1 discloses a semiconductor device that includes a semiconductor chip having main electrodes on both sides, a conductive member, and a sintered layer that bonds the main electrodes and the conductive member. The contents of the prior art document are incorporated by reference as explanations of the technical elements in this specification.
特開２０１８－１１７０５４号公報Japanese Patent Application Publication No. 2018-117054
　主電極のひとつは、保護膜であるポリイミドの開口部から接合可能に露出している。主電極の露出部の周囲には、保護膜が存在する。保護膜の上面は、主電極の接合面よりも上方に位置している。また、焼結層は、平面視において主電極の露出部にほぼ一致して設けられている。よって、主電極に対して焼結層の位置がずれて配置されると、焼結接合する際の加圧により保護膜側に応力が集中し、保護膜の損傷、保護膜により覆われた配線部のクラックなどが生じる虞がある。これに対し、位置ずれ公差を考慮して、焼結層の面積を小さくすることが考えられる。しかしながら、熱抵抗や電流密度が増加してしまう。 One of the main electrodes is exposed through an opening in the polyimide protective film so that it can be bonded. A protective film surrounds the exposed portion of the main electrode. The upper surface of the protective film is located above the bonding surface of the main electrode. The sintered layer is provided so as to almost coincide with the exposed portion of the main electrode in a plan view. Therefore, if the sintered layer is misaligned with respect to the main electrode, stress will be concentrated on the protective film side due to the pressure applied during sinter bonding, which may damage the protective film or cause cracks in the wiring portion covered by the protective film. To address this issue, it is possible to reduce the area of the sintered layer, taking into account the tolerance for misalignment. However, this would increase thermal resistance and current density.
　このように、いずれにおいても半導体装置の信頼性が低下してしまう。上述の観点において、または言及されていない他の観点において、半導体装置にはさらなる改良が求められている。 In this way, the reliability of the semiconductor device decreases in either case. Further improvements in semiconductor devices are required from the above-mentioned viewpoints and from other viewpoints not mentioned.
　本開示はこのような課題に鑑みてなされたものであり、信頼性を向上できる半導体装置を提供することを目的とする。 The present disclosure has been made in view of such problems, and aims to provide a semiconductor device that can improve reliability.
　開示のひとつである半導体装置は、
　半導体基板と、半導体基板の一面に設けられた第１主電極と、板厚方向において一面とは反対の裏面に設けられた第２主電極と、一面に設けられ、第１主電極を接合可能に露出させる開口部を備えた保護膜と、を有する半導体素子と、
　第１主電極に電気的に接続された導電部材と、
　第１主電極と導電部材との間に介在し、第１主電極と導電部材とを接合する焼結部材と、を備え、
　保護膜の上面のうち、少なくとも開口部の周囲部分は、板厚方向において第１主電極の接合面に対して面一以下の位置である。 The semiconductor device, which is one of the disclosures, is
A semiconductor substrate, a first main electrode provided on one surface of the semiconductor substrate, a second main electrode provided on the back surface opposite to the one surface in the board thickness direction, and the first main electrode provided on one surface can be bonded. a semiconductor element having a protective film having an opening exposed to the semiconductor element;
a conductive member electrically connected to the first main electrode;
a sintered member interposed between the first main electrode and the conductive member and joining the first main electrode and the conductive member;
At least a portion of the upper surface of the protective film surrounding the opening is located flush with or less than the bonding surface of the first main electrode in the plate thickness direction.
　開示の半導体装置によれば、保護膜の上面のうち、少なくとも開口部の周囲部分は、板厚方向において第１主電極の接合面よりも上方に突出していない。このため、第１主電極の露出部に対して焼結部材の位置がずれて配置されたとしても、焼結接合する際の加圧により、保護膜側に応力が集中するのを抑制することができる。また、焼結部材を小さくしなくても、保護膜側に応力が集中するのを抑制することができる。この結果、信頼性を向上できる半導体装置を提供することができる。 According to the disclosed semiconductor device, at least the portion of the upper surface of the protective film surrounding the opening does not protrude above the bonding surface of the first main electrode in the thickness direction. Therefore, even if the position of the sintered member is shifted from the exposed part of the first main electrode, stress concentration on the protective film side due to the pressure applied during sintering and joining can be suppressed. Can be done. Further, stress concentration on the protective film side can be suppressed without reducing the size of the sintered member. As a result, a semiconductor device with improved reliability can be provided.
　この明細書における開示された複数の態様は、それぞれの目的を達成するために、互いに異なる技術的手段を採用する。請求の範囲およびこの項に記載した括弧内の符号は、後述する実施形態の部分との対応関係を例示的に示すものであって、技術的範囲を限定することを意図するものではない。この明細書に開示される目的、特徴、および効果は、後続の詳細な説明、および添付の図面を参照することによってより明確になる。 The multiple embodiments disclosed in this specification employ different technical means to achieve their respective objectives. The claims and the reference numerals in parentheses described in this section exemplarily indicate correspondence with parts of the embodiment described later, and are not intended to limit the technical scope. The objects, features, and advantages disclosed in this specification will become more apparent by reference to the subsequent detailed description and accompanying drawings.
第１実施形態に係る半導体装置が適用される車両の駆動システムの概略構成を示す図である。1 is a diagram showing a schematic configuration of a vehicle drive system to which a semiconductor device according to a first embodiment is applied. 第１実施形態に係る半導体装置を示す平面図である。FIG. 1 is a plan view showing a semiconductor device according to a first embodiment. 図２のIII-III線に沿う断面図である。3 is a sectional view taken along line III-III in FIG. 2. FIG. 図２のIV-IV線に沿う断面図である。FIG. 3 is a cross-sectional view taken along line IV-IV in FIG. 2 . 半導体素子を示す平面図である。FIG. 2 is a plan view showing a semiconductor element. 図５のVI-VI線に沿う断面図である。6 is a cross-sectional view taken along the line VI-VI in FIG. 5. FIG. 半導体素子の接合構造を示す断面図である。1 is a cross-sectional view showing a junction structure of a semiconductor element. 接合方法を示す断面図である。FIG. 3 is a cross-sectional view showing a joining method. 参考例を示す断面図である。It is a sectional view showing a reference example. 参考例を示す断面図である。It is a sectional view showing a reference example. 本実施形態における位置ずれの例を示す断面図である。FIG. 3 is a cross-sectional view showing an example of positional displacement in the present embodiment. 第２実施形態に係る半導体装置において、半導体素子を示す断面図である。FIG. 7 is a cross-sectional view showing a semiconductor element in a semiconductor device according to a second embodiment. 第３実施形態に係る半導体装置において、半導体素子を示す平面図である。FIG. 7 is a plan view showing a semiconductor element in a semiconductor device according to a third embodiment. 図１３のXIV-XIV線に対応する半導体素子の接合構造を示す断面図である。14 is a cross-sectional view showing the junction structure of the semiconductor element corresponding to the line XIV-XIV in FIG. 13. FIG. 変形例を示す平面図である。It is a top view which shows a modification. その他変形例を示す断面図である。It is a sectional view showing other modifications. その他変形例を示す断面図である。It is a sectional view showing other modifications.
　以下、図面に基づいて複数の実施形態を説明する。なお、各実施形態において対応する構成要素には同一の符号を付すことにより、重複する説明を省略する場合がある。各実施形態において構成の一部分のみを説明している場合、当該構成の他の部分については、先行して説明した他の実施形態の構成を適用することができる。また、各実施形態の説明において明示している構成の組み合わせばかりではなく、特に組み合わせに支障が生じなければ、明示していなくても複数の実施形態の構成同士を部分的に組み合せることができる。 Hereinafter, multiple embodiments will be described based on the drawings. Note that redundant explanation may be omitted by assigning the same reference numerals to corresponding components in each embodiment. When only a part of the configuration is described in each embodiment, the configuration of the other embodiments previously described can be applied to other parts of the configuration. Furthermore, in addition to the combinations of configurations specified in the description of each embodiment, it is also possible to partially combine the configurations of multiple embodiments even if the combinations are not explicitly stated. .
　本実施形態の半導体装置は、たとえば、回転電機を駆動源とする移動体の電力変換装置に適用される。移動体は、たとえば、電気自動車（ＢＥＶ）、ハイブリッド自動車（ＨＥＶ）、プラグインハイブリッド自動車（ＰＨＥＶ）などの電動車両、電動垂直離着陸機やドローンなどの飛行体、船舶、建設機械、農業機械である。以下では、車両に適用される例について説明する。 The semiconductor device of this embodiment is applied, for example, to a power conversion device for a moving object that uses a rotating electric machine as a drive source. Examples of mobile objects include electric vehicles such as electric vehicles (BEV), hybrid vehicles (HEV), and plug-in hybrid vehicles (PHEV), flying vehicles such as electric vertical takeoff and landing aircraft and drones, ships, construction machinery, and agricultural machinery. . An example applied to a vehicle will be described below.
　（第１実施形態）
　先ず、図１に基づき、車両の駆動システムの概略構成について説明する。 (First embodiment)
First, based on FIG. 1, a schematic configuration of a vehicle drive system will be described.
　＜車両の駆動システム＞
　図１に示すように、車両の駆動システム１は、直流電源２と、モータジェネレータ３と、電力変換装置４を備えている。 <Vehicle drive system>
As shown in FIG. 1, a vehicle drive system 1 includes a DC power source 2, a motor generator 3, and a power converter 4.
　直流電源２は、充放電可能な二次電池で構成された直流電圧源である。二次電池は、たとえばリチウムイオン電池、ニッケル水素電池である。モータジェネレータ３は、三相交流方式の回転電機である。モータジェネレータ３は、車両の走行駆動源、すなわち電動機として機能する。モータジェネレータ３は、回生時に発電機として機能する。電力変換装置４は、直流電源２とモータジェネレータ３との間で電力変換を行う。 The DC power supply 2 is a DC voltage source composed of a rechargeable and dischargeable secondary battery. The secondary battery is, for example, a lithium ion battery or a nickel metal hydride battery. The motor generator 3 is a three-phase AC rotating electric machine. The motor generator 3 functions as a driving source for the vehicle, that is, an electric motor. The motor generator 3 functions as a generator during regeneration. Power conversion device 4 performs power conversion between DC power supply 2 and motor generator 3 .
　＜電力変換装置＞
　次に、図１に基づき、電力変換装置４の回路構成について説明する。電力変換装置４は、電力変換回路を備えている。図１に示すように電力変換装置４は、平滑コンデンサ５と、電力変換回路であるインバータ６を備えている。 <Power converter>
Next, the circuit configuration of the power conversion device 4 will be explained based on FIG. 1. The power conversion device 4 includes a power conversion circuit. As shown in FIG. 1, the power conversion device 4 includes a smoothing capacitor 5 and an inverter 6 that is a power conversion circuit.
　平滑コンデンサ５は、主として、直流電源２から供給される直流電圧を平滑化する。平滑コンデンサ５は、高電位側の電力ラインであるＰライン７と低電位側の電力ラインであるＮライン８とに接続されている。Ｐライン７は直流電源２の正極に接続され、Ｎライン８は直流電源２の負極に接続されている。平滑コンデンサ５の正極は、直流電源２とインバータ６との間において、Ｐライン７に接続されている。同じく負極は、直流電源２とインバータ６との間において、Ｎライン８に接続されている。平滑コンデンサ５は、直流電源２に並列に接続されている。 The smoothing capacitor 5 mainly smoothes the DC voltage supplied from the DC power supply 2. The smoothing capacitor 5 is connected to a P line 7 which is a power line on the high potential side and an N line 8 which is a power line on the low potential side. The P line 7 is connected to the positive pole of the DC power supply 2, and the N line 8 is connected to the negative pole of the DC power supply 2. A positive terminal of the smoothing capacitor 5 is connected to a P line 7 between the DC power supply 2 and the inverter 6. Similarly, the negative electrode is connected to the N line 8 between the DC power supply 2 and the inverter 6. Smoothing capacitor 5 is connected in parallel to DC power supply 2 .
　インバータ６は、ＤＣ－ＡＣ変換回路である。インバータ６は、図示しない制御回路によるスイッチング制御にしたがって、直流電圧を三相交流電圧に変換し、モータジェネレータ３へ出力する。これにより、モータジェネレータ３は、所定のトルクを発生するように駆動する。インバータ６は、車両の回生制動時、車輪からの回転力を受けてモータジェネレータ３が発電した三相交流電圧を、制御回路によるスイッチング制御にしたがって直流電圧に変換し、Ｐライン７へ出力する。このように、インバータ６は、直流電源２とモータジェネレータ３との間で双方向の電力変換を行う。 The inverter 6 is a DC-AC conversion circuit. In accordance with switching control by a control circuit (not shown), the inverter 6 converts DC voltage into three-phase AC voltage and outputs it to the motor generator 3. This drives the motor generator 3 to generate a predetermined torque. During regenerative braking of the vehicle, the inverter 6 converts the three-phase AC voltage generated by the motor generator 3 in response to rotational force from the wheels into DC voltage in accordance with switching control by the control circuit, and outputs it to the P line 7. In this way, the inverter 6 performs bidirectional power conversion between the DC power source 2 and the motor generator 3.
　インバータ６は、三相分の上下アーム回路９を備えて構成されている。上下アーム回路９は、レグと称されることがある。上下アーム回路９は、上アーム９Ｈと、下アーム９Ｌをそれぞれ有している。上アーム９Ｈと下アーム９Ｌは、上アーム９ＨをＰライン７側として、Ｐライン７とＮライン８との間で直列接続されている。上アーム９Ｈと下アーム９Ｌとの接続点は、出力ライン１０を介して、モータジェネレータ３における対応する相の巻線３ａに接続されている。インバータ６は、６つのアームを有している。Ｐライン７、Ｎライン８、および出力ライン１０それぞれの少なくとも一部は、たとえばバスバーなどの導電部材により構成されている。 The inverter 6 is configured with three-phase upper and lower arm circuits 9. The upper and lower arm circuits 9 are sometimes referred to as legs. The upper and lower arm circuits 9 each have an upper arm 9H and a lower arm 9L. The upper arm 9H and the lower arm 9L are connected in series between the P line 7 and the N line 8, with the upper arm 9H on the P line 7 side. A connection point between upper arm 9H and lower arm 9L is connected to a corresponding phase winding 3a of motor generator 3 via output line 10. Inverter 6 has six arms. At least a portion of each of the P line 7, the N line 8, and the output line 10 is constituted by a conductive member such as a bus bar.
　各アームを構成する素子は、スイッチング素子であるＩＧＢＴ１１と、還流用のダイオード１２を備えている。ＩＧＢＴは、Insulated Gate Bipolar Transistorの略称である。本実施形態では、ｎチャネル型のＩＧＢＴ１１を採用している。ダイオード１２は、対応するＩＧＢＴ１１に対して逆並列に接続されている。上アーム９Ｈにおいて、ＩＧＢＴ１１のコレクタが、Ｐライン７に接続されている。下アーム９Ｌにおいて、ＩＧＢＴ１１のエミッタが、Ｎライン８に接続されている。そして、上アーム９ＨにおけるＩＧＢＴ１１のエミッタと、下アーム９ＬにおけるＩＧＢＴ１１のコレクタが相互に接続されている。ダイオード１２のアノードは対応するＩＧＢＴ１１のエミッタに接続され、カソードはコレクタに接続されている。 The elements constituting each arm include an IGBT 11 that is a switching element and a diode 12 for freewheeling. IGBT is an abbreviation for Insulated Gate Bipolar Transistor. In this embodiment, an n-channel type IGBT 11 is used. The diode 12 is connected in antiparallel to the corresponding IGBT 11. In the upper arm 9H, the collector of the IGBT 11 is connected to the P line 7. In the lower arm 9L, the emitter of the IGBT 11 is connected to the N line 8. The emitter of the IGBT 11 in the upper arm 9H and the collector of the IGBT 11 in the lower arm 9L are connected to each other. The anode of the diode 12 is connected to the emitter of the corresponding IGBT 11, and the cathode is connected to the collector.
　電力変換装置４は、電力変換回路として、コンバータをさらに備えてもよい。コンバータは、直流電圧を異なる値の直流電圧に変換するＤＣ－ＤＣ変換回路である。コンバータは、直流電源２と平滑コンデンサ５との間に設けられる。コンバータは、たとえばリアクトルと、上記した上下アーム回路９を備えて構成される。この構成によれば、昇降圧が可能である。電力変換装置４は、直流電源２からの電源ノイズを除去するフィルタコンデンサを備えてもよい。フィルタコンデンサは、直流電源２とコンバータとの間に設けられる。 The power conversion device 4 may further include a converter as a power conversion circuit. A converter is a DC-DC conversion circuit that converts DC voltage to DC voltages of different values. A converter is provided between DC power supply 2 and smoothing capacitor 5. The converter includes, for example, a reactor and the above-mentioned upper and lower arm circuits 9. According to this configuration, it is possible to raise and lower the voltage. The power conversion device 4 may include a filter capacitor that removes power supply noise from the DC power supply 2. A filter capacitor is provided between the DC power supply 2 and the converter.
　電力変換装置４は、インバータ６などを構成するスイッチング素子の駆動回路を備えてもよい。駆動回路は、制御回路の駆動指令に基づいて、対応するアームのＩＧＢＴ１１のゲートに駆動電圧を供給する。駆動回路は、駆動電圧の印加により、対応するＩＧＢＴ１１を駆動、すなわちオン駆動、オフ駆動させる。駆動回路は、ドライバと称されることがある。 The power conversion device 4 may include a drive circuit for switching elements that constitute the inverter 6 and the like. The drive circuit supplies a drive voltage to the gate of the IGBT 11 of the corresponding arm based on a drive command from the control circuit. The drive circuit drives the corresponding IGBT 11 by applying a drive voltage, that is, turns it on and turns it off. A drive circuit is sometimes referred to as a driver.
　電力変換装置４は、スイッチング素子の制御回路を備えてもよい。制御回路は、ＩＧＢＴ１１を動作させるための駆動指令を生成し、駆動回路に出力する。制御回路は、図示しない上位ＥＣＵから入力されるトルク要求、各種センサにて検出された信号に基づいて、駆動指令を生成する。各種センサとして、たとえば電流センサ、回転角センサ、電圧センサがある。電流センサは、各相の巻線３ａに流れる相電流を検出する。回転角センサは、モータジェネレータ３の回転子の回転角を検出する。電圧センサは、平滑コンデンサ５の両端電圧を検出する。制御回路は、駆動指令として、たとえばＰＷＭ信号を出力する。制御回路は、たとえばプロセッサとメモリを備えて構成されている。ＥＣＵは、Electronic Control Unitの略称である。ＰＷＭは、Pulse Width Modulationの略称である。 The power conversion device 4 may include a control circuit for switching elements. The control circuit generates a drive command for operating the IGBT 11 and outputs it to the drive circuit. The control circuit generates a drive command based on a torque request input from a host ECU (not shown) and signals detected by various sensors. Various sensors include, for example, a current sensor, a rotation angle sensor, and a voltage sensor. The current sensor detects the phase current flowing through the winding 3a of each phase. The rotation angle sensor detects the rotation angle of the rotor of the motor generator 3. The voltage sensor detects the voltage across the smoothing capacitor 5. The control circuit outputs, for example, a PWM signal as a drive command. The control circuit includes, for example, a processor and a memory. ECU is an abbreviation for Electronic Control Unit. PWM is an abbreviation for Pulse Width Modulation.
　＜半導体装置＞
　次に、図２～図５に基づき、半導体装置の概略構成について説明する。図２は、半導体装置を示す平面図である。図２は、半導体装置の上面視平面図である。図３は、図２のIII-III線に沿う断面図である。図４は、図２のIV-IV線に沿う断面図である。図５は、半導体素子を示す平面図である。 <Semiconductor device>
Next, the schematic structure of the semiconductor device will be explained based on FIGS. 2 to 5. FIG. 2 is a plan view showing the semiconductor device. FIG. 2 is a top plan view of the semiconductor device. FIG. 3 is a sectional view taken along line III-III in FIG. 2. FIG. 4 is a sectional view taken along line IV-IV in FIG. 2. FIG. 5 is a plan view showing the semiconductor element.
　以下において、半導体素子（半導体基板）の板厚方向をＺ方向とする。Ｚ方向に直交する一方向をＸ方向とする。Ｚ方向およびＸ方向の両方向に直交する方向をＹ方向とする。特に断わりのない限り、Ｚ方向から平面視した形状、換言すればＸ方向およびＹ方向により規定されるＸＹ面に沿う形状を平面形状とする。また、Ｚ方向からの平面視を、単に平面視と示すことがある。 In the following, the thickness direction of the semiconductor element (semiconductor substrate) is referred to as the Z direction. One direction perpendicular to the Z direction is defined as the X direction. The direction perpendicular to both the Z direction and the X direction is defined as the Y direction. Unless otherwise specified, the planar shape is the shape viewed from the Z direction, in other words, the shape along the XY plane defined by the X direction and the Y direction. Further, a planar view from the Z direction may be simply referred to as a planar view.
　図２～図５に示すように、半導体装置２０は、封止体３０と、半導体素子４０と、配線部材５０、６０と、導電スペーサ７０と、外部接続端子８０を備えている。半導体装置２０は、さらにボンディングワイヤ９０と、接合材１００を備えている。半導体装置２０は、上記したアームのひとつを構成する。すなわち、２つの半導体装置２０により、一相分の上下アーム回路９が構成される。 As shown in FIGS. 2 to 5, the semiconductor device 20 includes a sealing body 30, a semiconductor element 40, wiring members 50 and 60, a conductive spacer 70, and an external connection terminal 80. The semiconductor device 20 further includes a bonding wire 90 and a bonding material 100. The semiconductor device 20 constitutes one of the arms described above. That is, the two semiconductor devices 20 constitute the upper and lower arm circuit 9 for one phase.
　封止体３０は、半導体装置２０を構成する他の要素の一部を封止している。他の要素の残りの部分は、封止体３０の外に露出している。封止体３０は、たとえば樹脂を材料とする。樹脂の一例は、エポキシ系樹脂である。封止体３０は、樹脂を材料として、たとえばトランスファモールド法により成形されている。このような封止体３０は、封止樹脂体、モールド樹脂、樹脂成形体などと称されることがある。封止体３０は、たとえばゲルを用いて形成されてもよい。ゲルは、たとえば一対の配線部材５０、６０の対向領域に充填（配置）される。 The sealing body 30 seals some of the other elements constituting the semiconductor device 20. The remaining parts of the other elements are exposed outside the sealing body 30. The sealing body 30 is made of resin, for example. An example of the resin is an epoxy resin. The sealing body 30 is molded from resin by, for example, a transfer molding method. Such a sealing body 30 is sometimes referred to as a sealing resin body, a mold resin, a resin molded body, or the like. The sealing body 30 may be formed using gel, for example. The gel is filled (arranged) in opposing regions of the pair of wiring members 50 and 60, for example.
　図２～図４に示すように、封止体３０は平面略矩形状をなしている。封止体３０は、外郭をなす表面として、一面３０ａと、Ｚ方向において一面３０ａとは反対の面である裏面３０ｂを有している。一面３０ａおよび裏面３０ｂは、たとえば略平坦な面である。また、一面３０ａおよび裏面３０ｂに連なる側面３０ｃ、３０ｄ、３０ｅ、３０ｆを有している。側面３０ｃは、外部接続端子８０のうち、主端子８１、８２が突出する面である。側面３０ｄは、Ｙ方向において側面３０ｃとは反対の面である。側面３０ｄは、信号端子８３が突出する面である。側面３０ｅ、３０ｆは、外部接続端子８０が突出していない面である。側面３０ｅは、Ｘ方向において側面３０ｆとは反対の面である。 As shown in FIGS. 2 to 4, the sealing body 30 has a substantially rectangular shape in plan view. The sealing body 30 has one surface 30a and a back surface 30b, which is a surface opposite to the one surface 30a in the Z direction, as a surface forming an outline. One surface 30a and back surface 30b are, for example, substantially flat surfaces. It also has side surfaces 30c, 30d, 30e, and 30f that are continuous with the one surface 30a and the back surface 30b. The side surface 30c is a surface from which the main terminals 81 and 82 of the external connection terminal 80 protrude. The side surface 30d is a surface opposite to the side surface 30c in the Y direction. The side surface 30d is a surface from which the signal terminal 83 projects. The side surfaces 30e and 30f are surfaces from which the external connection terminal 80 does not protrude. The side surface 30e is a surface opposite to the side surface 30f in the X direction.
　半導体素子４０は、半導体基板４１と、エミッタ電極４２と、コレクタ電極４３と、パッド４４を備えている。半導体素子４０は、半導体チップと称されることがある。半導体基板４１は、シリコン（Ｓｉ）、シリコンよりもバンドギャップが広いワイドバンドギャップ半導体などを材料とし、縦型素子が形成されてなる。ワイドバンドギャップ半導体としては、たとえばシリコンカーバイド（ＳｉＣ）、窒化ガリウム（ＧａＮ）、酸化ガリウム（Ｇａ２Ｏ３）、ダイヤモンドがある。 The semiconductor element 40 includes a semiconductor substrate 41, an emitter electrode 42, a collector electrode 43, and a pad 44. The semiconductor element 40 is sometimes referred to as a semiconductor chip. The semiconductor substrate 41 is made of a material such as silicon (Si) or a wide bandgap semiconductor having a wider bandgap than silicon, and has a vertical element formed thereon. Examples of wide bandgap semiconductors include silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga 2 O 3 ), and diamond.
　縦型素子は、半導体基板４１（半導体素子４０）の板厚方向、すなわちＺ方向に主電流を流すように構成されている。本実施形態の縦型素子は、ひとつのアームを構成するＩＧＢＴ１１およびダイオード１２である。縦型素子は、ダイオード１２が逆並列に接続されたＩＧＢＴ、つまりＲＣ－ＩＧＢＴである。ＲＣは、Reverse Conductingの略称である。縦型素子は、通電により発熱する発熱素子である。半導体基板４１には、図示しないゲート電極が形成されている。ゲート電極は、たとえばトレンチ構造をなしている。 The vertical element is configured to allow a main current to flow in the thickness direction of the semiconductor substrate 41 (semiconductor element 40), that is, in the Z direction. The vertical elements of this embodiment are the IGBT 11 and the diode 12 that constitute one arm. The vertical element is an IGBT in which diodes 12 are connected in antiparallel, that is, an RC-IGBT. RC is an abbreviation for Reverse Conducting. The vertical element is a heating element that generates heat when energized. A gate electrode (not shown) is formed on the semiconductor substrate 41. The gate electrode has, for example, a trench structure.
　半導体基板４１は、主電極が設けられる板面として、一面４１ａおよび裏面４１ｂを有している。一面４１ａは、半導体基板４１において封止体３０の一面３０ａ側の面である。裏面４１ｂは、一面４１ａとは板厚方向において反対の面である。主電極のひとつであるエミッタ電極４２は、半導体基板４１の一面４１ａ上に配置されている。主電極の他のひとつであるコレクタ電極４３は、半導体基板４１の裏面４１ｂ上に配置されている。エミッタ電極４２が第１主電極に相当し、コレクタ電極４３が第２主電極に相当する。 The semiconductor substrate 41 has one side 41a and a back side 41b as plate surfaces on which the main electrode is provided. One surface 41a is a surface of the semiconductor substrate 41 on the one surface 30a side of the sealed body 30. The back surface 41b is a surface opposite to the one surface 41a in the thickness direction. The emitter electrode 42, which is one of the main electrodes, is arranged on one surface 41a of the semiconductor substrate 41. A collector electrode 43, which is another one of the main electrodes, is arranged on the back surface 41b of the semiconductor substrate 41. The emitter electrode 42 corresponds to a first main electrode, and the collector electrode 43 corresponds to a second main electrode.
　ＩＧＢＴ１１がオンすることで、主電極間、つまりエミッタ電極４２とコレクタ電極４３との間に、電流（主電流）が流れる。エミッタ電極４２は、ダイオード１２のアノード電極を兼ねている。コレクタ電極４３は、ダイオード１２のカソード電極を兼ねている。コレクタ電極４３は、半導体基板４１の裏面４１ｂのほぼ全域に形成されている。エミッタ電極４２は、半導体基板４１の一面４１ａの一部分に形成されている。 When the IGBT 11 is turned on, a current (main current) flows between the main electrodes, that is, between the emitter electrode 42 and the collector electrode 43. The emitter electrode 42 also serves as an anode electrode of the diode 12. The collector electrode 43 also serves as the cathode electrode of the diode 12. The collector electrode 43 is formed over almost the entire back surface 41b of the semiconductor substrate 41. The emitter electrode 42 is formed on a portion of one surface 41a of the semiconductor substrate 41.
　パッド４４は、信号用の電極である。パッド４４は、半導体基板４１の一面４１ａにおいて、エミッタ電極４２の形成領域とは異なる領域に形成されている。パッド４４は、Ｙ方向において、エミッタ電極４２の形成領域とは反対側の端部に形成されている。パッド４４は、Ｙ方向においてエミッタ電極４２と並んで設けられている。パッド４４は、ゲートパッド４４Ｇを少なくとも含む。 The pad 44 is a signal electrode. The pad 44 is formed on one surface 41a of the semiconductor substrate 41 in a region different from the region where the emitter electrode 42 is formed. The pad 44 is formed at the end opposite to the region where the emitter electrode 42 is formed in the Y direction. The pad 44 is provided in parallel with the emitter electrode 42 in the Y direction. Pad 44 includes at least gate pad 44G.
　一例として図５に示すように、半導体素子４０は５つのパッド４４を有している。具体的には、ゲートパッド４４Ｇ、エミッタ電位の検出用、半導体素子４０が備える図示しない感温ダイオードのカソード電位検出用、同じくアノード電位検出用、電流センス用を有している。５つのパッド４４は、Ｘ方向に沿って並んでいる。半導体素子４０の詳細については、後述する。 As an example, as shown in FIG. 5, the semiconductor element 40 has five pads 44. Specifically, the gate pad 44G has a gate pad 44G for detecting the emitter potential, for detecting the cathode potential of a temperature-sensitive diode (not shown) included in the semiconductor element 40, for detecting the anode potential, and for current sensing. The five pads 44 are lined up along the X direction. Details of the semiconductor element 40 will be described later.
　配線部材５０は、エミッタ電極４２に電気的に接続され、配線機能を提供する。同様に、配線部材６０は、コレクタ電極４３に電気的に接続され、配線機能を提供する。配線部材５０、６０は、Ｚ方向において、半導体素子４０を挟むように配置されている。配線部材５０、６０は、Ｚ方向において互いに少なくとも一部が対向するように配置されている。配線部材５０、６０は、平面視において半導体素子４０を内包している。 The wiring member 50 is electrically connected to the emitter electrode 42 and provides a wiring function. Similarly, the wiring member 60 is electrically connected to the collector electrode 43 and provides a wiring function. The wiring members 50 and 60 are arranged to sandwich the semiconductor element 40 in the Z direction. The wiring members 50 and 60 are arranged so that at least a portion thereof faces each other in the Z direction. The wiring members 50 and 60 include the semiconductor element 40 in a plan view.
　配線部材５０、６０は、半導体素子４０の生じた熱を放熱する放熱機能を提供する。配線部材５０、６０は、放熱板、ヒートシンクなどと称されることがある。本実施形態の配線部材５０、６０は、Ｃｕ、Ｃｕ合金などの導電性が良好な金属を材料とする金属板である。金属板は、たとえばリードフレームの一部として提供される。金属板に代えて、絶縁基材の両面に金属体が配置された基板を採用してもよい。配線部材５０、６０は、金属の表面に、ＮｉやＡｕなどのめっき膜を備えてもよい。 The wiring members 50 and 60 provide a heat radiation function of radiating heat generated by the semiconductor element 40. The wiring members 50 and 60 are sometimes referred to as heat sinks, heat sinks, or the like. The wiring members 50 and 60 of this embodiment are metal plates made of a metal with good conductivity such as Cu or Cu alloy. The metal plate is provided, for example, as part of a lead frame. Instead of the metal plate, a substrate may be used in which metal bodies are arranged on both sides of an insulating base material. The wiring members 50 and 60 may include a plating film of Ni, Au, or the like on the metal surface.
　配線部材５０は、半導体素子４０側の面である対向面５０ａと、対向面５０ａとは反対の面である裏面５０ｂを有している。同様に、配線部材６０も、対向面６０ａと裏面６０ｂを有している。配線部材５０、６０は、たとえば平面略矩形状をなしている。配線部材５０、６０それぞれの裏面５０ｂ、６０ｂは、封止体３０から露出している。裏面５０ｂ、６０ｂは、放熱面、露出面などと称されることがある。配線部材５０の裏面５０ｂは、封止体３０の一面３０ａと略面一である。配線部材６０の裏面６０ｂは、封止体３０の裏面３０ｂと略面一である。 The wiring member 50 has a facing surface 50a that is a surface on the semiconductor element 40 side, and a back surface 50b that is a surface opposite to the facing surface 50a. Similarly, the wiring member 60 also has a facing surface 60a and a back surface 60b. The wiring members 50 and 60 have, for example, a substantially rectangular planar shape. The back surfaces 50b and 60b of the wiring members 50 and 60 are exposed from the sealing body 30. The back surfaces 50b and 60b are sometimes referred to as heat radiation surfaces, exposed surfaces, and the like. The back surface 50b of the wiring member 50 is substantially flush with the one surface 30a of the sealing body 30. The back surface 60b of the wiring member 60 is substantially flush with the back surface 30b of the sealing body 30.
　導電スペーサ７０は、半導体素子４０と配線部材５０の間に介在している。導電スペーサ７０は、半導体素子４０と配線部材５０との間に所定の間隔を確保するスペーサ機能を提供する。たとえば導電スペーサ７０は、半導体素子４０のパッド４４に、対応する信号端子８３を電気的に接続するための高さを確保する。導電スペーサ７０は、半導体素子４０のエミッタ電極４２と配線部材５０との電気伝導、熱伝導経路の途中に位置し、配線機能および放熱機能を提供する。導電スペーサ７０が、焼結部材を介して第１主電極に接続される導電部材に相当する。 The conductive spacer 70 is interposed between the semiconductor element 40 and the wiring member 50. The conductive spacer 70 provides a spacer function to ensure a predetermined distance between the semiconductor element 40 and the wiring member 50. For example, the conductive spacer 70 ensures a height for electrically connecting the corresponding signal terminal 83 to the pad 44 of the semiconductor element 40 . The conductive spacer 70 is located in the middle of the electrical and thermal conduction path between the emitter electrode 42 of the semiconductor element 40 and the wiring member 50, and provides a wiring function and a heat dissipation function. The conductive spacer 70 corresponds to a conductive member connected to the first main electrode via the sintered member.
　導電スペーサ７０は、Ｃｕ（銅）などの導電性、熱伝導性が良好な金属材料を含んでいる。導電スペーサ７０は、表面にめっき膜を備えてもよい。導電スペーサ７０は、ターミナル、ターミナルブロック、金属ブロック体などと称されることがある。半導体装置２０は、半導体素子４０と同数の導電スペーサ７０を備えている。導電スペーサ７０は、半導体素子４０に個別に接続されている。導電スペーサ７０は、たとえば柱状体である。導電スペーサ７０は、平面視において後述する開口部４５１に対応する形状を有している。導電スペーサ７０は、開口部４５１にほぼ一致するか若干小さい大きさを有している。 The conductive spacer 70 includes a metal material with good electrical conductivity and thermal conductivity, such as Cu (copper). The conductive spacer 70 may have a plating film on its surface. The conductive spacer 70 is sometimes referred to as a terminal, a terminal block, a metal block, or the like. The semiconductor device 20 includes the same number of conductive spacers 70 as the semiconductor elements 40. Conductive spacers 70 are individually connected to semiconductor elements 40 . The conductive spacer 70 is, for example, a columnar body. The conductive spacer 70 has a shape corresponding to an opening 451 described later in plan view. The conductive spacer 70 has a size that approximately matches or is slightly smaller than the opening 451.
　外部接続端子８０は、半導体装置２０を外部機器と電気的に接続するための端子である。外部接続端子８０は、銅などの導電性が良好な金属材料を用いて形成されている。外部接続端子８０は、たとえば板材である。外部接続端子８０は、リードと称されることがある。外部接続端子８０は、主端子８１、８２と、信号端子８３を備えている。主端子８１、８２は、半導体素子４０の主電極に電気的に接続された外部接続端子８０である。 The external connection terminal 80 is a terminal for electrically connecting the semiconductor device 20 to external equipment. The external connection terminal 80 is formed using a metal material with good conductivity, such as copper. The external connection terminal 80 is, for example, a plate material. The external connection terminal 80 is sometimes called a lead. The external connection terminal 80 includes main terminals 81 and 82 and a signal terminal 83. The main terminals 81 and 82 are external connection terminals 80 electrically connected to the main electrodes of the semiconductor element 40.
　主端子８１は、エミッタ電極４２に電気的に接続されている。主端子８１は、エミッタ端子と称されることがある。主端子８１は、配線部材５０を介して、エミッタ電極４２に接続されている。主端子８１は、配線部材５０におけるＹ方向の一端に連なっている。主端子８１の厚みは、配線部材５０よりも薄い。主端子８１は、たとえば対向面５０ａと略面一となるように、配線部材５０に連なっている。主端子８１は、配線部材５０に対して連続して一体的に設けられることで連なってもよいし、別部材として設けられ、接合により連なってもよい。 The main terminal 81 is electrically connected to the emitter electrode 42. The main terminal 81 is sometimes referred to as an emitter terminal. The main terminal 81 is connected to the emitter electrode 42 via the wiring member 50. The main terminal 81 is connected to one end of the wiring member 50 in the Y direction. The thickness of the main terminal 81 is thinner than that of the wiring member 50. The main terminal 81 is connected to the wiring member 50 so as to be, for example, approximately flush with the opposing surface 50a. The main terminal 81 may be connected by being provided continuously and integrally with the wiring member 50, or may be provided as a separate member and connected by joining.
　本実施形態の主端子８１は、リードフレームの一部として、配線部材５０と一体的に設けられている。主端子８１は、配線部材５０からＹ方向に延び、封止体３０の側面３０ｃから外部に突出している。主端子８１は、封止体３０により覆われる部分の途中に屈曲部を有し、側面３０ｃにおいてＺ方向の中央付近から突出している。 The main terminal 81 of this embodiment is provided integrally with the wiring member 50 as a part of the lead frame. The main terminal 81 extends from the wiring member 50 in the Y direction and projects outward from the side surface 30c of the sealing body 30. The main terminal 81 has a bent part in the middle of the portion covered by the sealing body 30, and protrudes from near the center in the Z direction on the side surface 30c.
　主端子８２は、コレクタ電極４３に電気的に接続されている。主端子８２は、コレクタ端子と称されることがある。主端子８２は、配線部材６０を介して、コレクタ電極４３に接続されている。主端子８２は、配線部材６０におけるＹ方向の一端に連なっている。主端子８２の厚みは、配線部材６０よりも薄い。主端子８２は、たとえば、対向面６０ａと略面一となるように配線部材６０に連なっている。主端子８２は、配線部材６０に対して連続して一体的に設けられることで連なってもよいし、別部材として設けられ、接合により連なってもよい。 The main terminal 82 is electrically connected to the collector electrode 43. Main terminal 82 is sometimes referred to as a collector terminal. The main terminal 82 is connected to the collector electrode 43 via the wiring member 60. The main terminal 82 is connected to one end of the wiring member 60 in the Y direction. The thickness of the main terminal 82 is thinner than that of the wiring member 60. The main terminal 82 is connected to the wiring member 60, for example, so as to be substantially flush with the opposing surface 60a. The main terminal 82 may be continuously and integrally provided with the wiring member 60, or may be provided as a separate member and connected by joining.
　本実施形態の主端子８２は、主端子８１とは別のリードフレームの一部として、配線部材６０と一体的に設けられている。主端子８２は、配線部材６０からＹ方向に延び、主端子８１と同じ側面３０ｃから外部に突出している。主端子８２も、封止体３０により覆われる部分の途中に屈曲部を有し、側面３０ｃにおいてＺ方向の中央付近から突出している。２本の主端子８１、８２は、側面同士が対向するようにＸ方向に並んで配置されている。 The main terminal 82 of this embodiment is provided integrally with the wiring member 60 as a part of a lead frame separate from the main terminal 81. The main terminal 82 extends from the wiring member 60 in the Y direction and projects outward from the same side surface 30c as the main terminal 81. The main terminal 82 also has a bent part in the middle of the portion covered by the sealing body 30, and protrudes from near the center in the Z direction on the side surface 30c. The two main terminals 81 and 82 are arranged side by side in the X direction so that their side surfaces face each other.
　信号端子８３は、半導体素子４０の対応するパッド４４に電気的に接続されている。信号端子８３は、ボンディングワイヤ９０を介してパッド４４に電気的に接続されている。信号端子８３は、Ｙ方向に延び、封止体３０の側面３０ｄから外部に突出している。本実施形態の半導体装置２０は、パッド４４に対応して５本の信号端子８３を備えている。５本の信号端子８３は、Ｘ方向に並んで配置されている。信号端子８３は、たとえば配線部材６０および主端子８２と共通のリードフレームに構成されている。複数の信号端子８３は、図示しないタイバーをカットすることで、互いに電気的に分離されている。 The signal terminal 83 is electrically connected to the corresponding pad 44 of the semiconductor element 40. The signal terminal 83 is electrically connected to the pad 44 via a bonding wire 90. The signal terminal 83 extends in the Y direction and projects outward from the side surface 30d of the sealing body 30. The semiconductor device 20 of this embodiment includes five signal terminals 83 corresponding to the pads 44. The five signal terminals 83 are arranged in line in the X direction. The signal terminal 83 is configured, for example, on a common lead frame with the wiring member 60 and the main terminal 82. The plurality of signal terminals 83 are electrically isolated from each other by cutting tie bars (not shown).
　接合材１００は、半導体装置２０を構成する要素間に介在し、要素同士を接合する。半導体装置２０は、複数の接合材１００を備えている。接合材１００のひとつは、エミッタ電極４２と導電スペーサ７０との間に介在し、エミッタ電極４２と導電スペーサ７０とを接合している。接合材１００の他のひとつは、導電スペーサ７０と配線部材５０との間に介在し、導電スペーサ７０と配線部材５０とを接合している。接合材１００の他のひとつは、半導体素子４０のコレクタ電極４３と配線部材６０との間に介在し、コレクタ電極４３と配線部材６０とを接合している。 The bonding material 100 is interposed between the elements constituting the semiconductor device 20 and bonds the elements together. The semiconductor device 20 includes a plurality of bonding materials 100. One of the bonding materials 100 is interposed between the emitter electrode 42 and the conductive spacer 70 to bond the emitter electrode 42 and the conductive spacer 70 together. The other bonding material 100 is interposed between the conductive spacer 70 and the wiring member 50 and joins the conductive spacer 70 and the wiring member 50 together. The other bonding material 100 is interposed between the collector electrode 43 of the semiconductor element 40 and the wiring member 60 to bond the collector electrode 43 and the wiring member 60 together.
　複数の接合材１００のうち、エミッタ電極４２と導電スペーサ７０との間に介在する接合材１００は、後述するように焼結部材１０１である。他の接合材１００は、焼結部材でもよいし、はんだなどの焼結部材とは異なる接合材でもよい。 Among the plurality of bonding materials 100, the bonding material 100 interposed between the emitter electrode 42 and the conductive spacer 70 is a sintered member 101 as described later. The other bonding material 100 may be a sintered member, or may be a bonding material different from the sintered member, such as solder.
　上記したように、半導体装置２０では、封止体３０によってひとつのアームを構成する半導体素子４０が封止されている。封止体３０は、半導体素子４０、配線部材５０の一部、配線部材６０の一部、導電スペーサ７０、および外部接続端子８０それぞれの一部を、一体的に封止している。 As described above, in the semiconductor device 20, the semiconductor element 40 constituting one arm is sealed by the sealing body 30. The sealing body 30 integrally seals the semiconductor element 40, a portion of the wiring member 50, a portion of the wiring member 60, a conductive spacer 70, and a portion of each of the external connection terminals 80.
　半導体素子４０は、Ｚ方向において配線部材５０、６０の間に配置されている。半導体素子４０は、対向配置された配線部材５０、６０によって挟まれている。これにより、半導体素子４０の熱を、Ｚ方向において両側に放熱することができる。半導体装置２０は、両面放熱構造をなしている。配線部材５０の裏面５０ｂは、封止体３０の一面３０ａと略面一となっている。配線部材６０の裏面６０ｂは、封止体３０の裏面３０ｂと略面一となっている。裏面５０ｂ、６０ｂが露出面であるため、放熱性を高めることができる。 The semiconductor element 40 is arranged between the wiring members 50 and 60 in the Z direction. The semiconductor element 40 is sandwiched between wiring members 50 and 60 that are arranged opposite to each other. Thereby, the heat of the semiconductor element 40 can be radiated to both sides in the Z direction. The semiconductor device 20 has a double-sided heat dissipation structure. The back surface 50b of the wiring member 50 is substantially flush with the one surface 30a of the sealing body 30. The back surface 60b of the wiring member 60 is substantially flush with the back surface 30b of the sealing body 30. Since the back surfaces 50b and 60b are exposed surfaces, heat dissipation can be improved.
　＜半導体素子＞
　次に、図５および図６に基づき、半導体素子４０について説明する。図６は、図５のVI-VI線に沿う断面図である。図５では、後述するゲート配線４６を破線で示している。 <Semiconductor element>
Next, the semiconductor element 40 will be explained based on FIGS. 5 and 6. FIG. 6 is a sectional view taken along line VI-VI in FIG. 5. In FIG. 5, a gate wiring 46, which will be described later, is shown by a broken line.
　半導体基板４１は、平面略矩形状をなしている。図５および図６に示すように、半導体基板４１は、アクティブ領域４１１と、外周領域４１２を有している。図５および図６に示す二点鎖線は、アクティブ領域４１１と外周領域４１２の境界を示している。 The semiconductor substrate 41 has a substantially rectangular planar shape. As shown in FIGS. 5 and 6, the semiconductor substrate 41 has an active region 411 and an outer peripheral region 412. The two-dot chain line shown in FIGS. 5 and 6 indicates the boundary between the active region 411 and the outer peripheral region 412.
　アクティブ領域４１１は、縦型素子の形成領域である。アクティブ領域４１１は、メイン領域、メインセル領域、セル領域、素子領域、素子形成領域などと称されることがある。アクティブ領域４１１は、たとえば平面略矩形状をなしている。アクティブ領域４１１は、Ｙ方向においてパッド４４と並んでいる。アクティブ領域４１１には、複数のセル（単位構造部）が設けられている。複数のセルが互いに並列接続されて、ＲＣ－ＩＧＢＴが構成されている。 The active region 411 is a region where vertical elements are formed. The active region 411 is sometimes referred to as a main region, a main cell region, a cell region, an element region, an element formation region, or the like. The active region 411 has, for example, a substantially rectangular planar shape. The active region 411 is aligned with the pad 44 in the Y direction. The active region 411 is provided with a plurality of cells (unit structures). A plurality of cells are connected in parallel to form an RC-IGBT.
　外周領域４１２は、平面視においてアクティブ領域４１１を取り囲んでいる。外周領域４１２には、耐圧構造部が形成されている。一例として本実施形態では、ガードリング４１３が形成されている。ガードリング４１３は、アクティブ領域４１１を取り囲むように平面視において環状をなしている。 The outer peripheral region 412 surrounds the active region 411 in plan view. A pressure-resistant structure is formed in the outer peripheral region 412. As an example, in this embodiment, a guard ring 413 is formed. The guard ring 413 has an annular shape in a plan view so as to surround the active region 411 .
　図５および図６に示すように、半導体素子４０は、半導体基板４１の一面４１ａ上に配置された保護膜４５を備えている。保護膜４５は、エミッタ電極４２、具体的には後述の下地電極４２２の周縁部を覆うように、半導体基板４１の一面４１ａ上に設けられた絶縁膜である。保護膜４５の材料として、たとえばポリイミド、シリコン窒化膜などを採用することができる。 As shown in Figures 5 and 6, the semiconductor element 40 has a protective film 45 disposed on one surface 41a of the semiconductor substrate 41. The protective film 45 is an insulating film provided on one surface 41a of the semiconductor substrate 41 so as to cover the peripheral portion of the emitter electrode 42, specifically the base electrode 422 described below. For example, polyimide, silicon nitride film, etc. can be used as the material for the protective film 45.
　保護膜４５は、開口部４５１を有している。開口部４５１は、エミッタ電極４２と焼結部材１０１との接合領域を規定している。開口部４５１は、保護膜４５をＺ方向に貫通する貫通孔である。開口部４５１は、平面視においてエミッタ電極４２と重なるように設けられている。開口部４５１は、平面視においてアクティブ領域４１１とほぼ一致している。開口部４５１の平面形状、つまり開口部４５１を規定する保護膜４５の内周面は、平面略矩形状をなしている。同様に、保護膜４５は、パッド４４における接合領域を規定する開口部４５２を有している。 The protective film 45 has an opening 451. The opening 451 defines a joining area between the emitter electrode 42 and the sintered member 101. The opening 451 is a through hole that penetrates the protective film 45 in the Z direction. The opening 451 is provided so as to overlap the emitter electrode 42 in plan view. The opening 451 substantially coincides with the active region 411 in plan view. The planar shape of the opening 451, that is, the inner circumferential surface of the protective film 45 that defines the opening 451 has a substantially rectangular planar shape. Similarly, the protective film 45 has an opening 452 that defines the bonding area in the pad 44 .
　エミッタ電極４２は、保護膜４５の開口部４５１から露出して接合領域を提供する露出部４２１を有している。露出部４２１は、焼結部材１０１との間に接合部を形成する。平面視において露出部４２１の外形輪郭は、開口部４５１の外形輪郭に一致している。露出部４２１は、半導体基板４１のアクティブ領域４１１上に配置されている。エミッタ電極４２は、多層構造をなしている。エミッタ電極４２は、下地電極４２２と、接続電極４２３を有している。パッド４４も、エミッタ電極４２と同様の構成を有している。 The emitter electrode 42 has an exposed portion 421 that is exposed from the opening 451 of the protective film 45 and provides a bonding region. The exposed portion 421 forms a joint with the sintered member 101. The external contour of the exposed portion 421 matches the external contour of the opening 451 in a plan view. The exposed portion 421 is arranged on the active region 411 of the semiconductor substrate 41. The emitter electrode 42 has a multilayer structure. The emitter electrode 42 has a base electrode 422 and a connection electrode 423. The pad 44 also has the same configuration as the emitter electrode 42.
　下地電極４２２は、多層構造のエミッタ電極４２において、半導体基板４１側に配置された金属層である。下地電極４２２は、一例としてＡｌ（アルミニウム）を主成分とする材料を用いて形成されている。本実施形態の下地電極４２２は、ＡｌＳｉ、ＡｌＳｉＣｕなどのＡｌ合金を用いて形成されている。下地電極４２２は、配線電極、下地層、第１金属層などと称されることがある。 The base electrode 422 is a metal layer placed on the semiconductor substrate 41 side in the multilayered emitter electrode 42. The base electrode 422 is formed using, for example, a material whose main component is Al (aluminum). The base electrode 422 of this embodiment is formed using an Al alloy such as AlSi or AlSiCu. The base electrode 422 is sometimes referred to as a wiring electrode, a base layer, a first metal layer, or the like.
　下地電極４２２は、平面視において、アクティブ領域４１１を内包しつつ、外周領域４１２上まで延設されている。下地電極４２２は、縦型素子のエミッタおよびアノードに接続されている。下地電極４２２は、平面視において露出部４２１を取り囲む周縁部を有している。周縁部は、下地電極４２２において保護膜４５と重なる部分である。保護膜４５は、下地電極４２２の周縁部を覆うように、半導体基板４１の一面４１ａ上に配置されている。 The base electrode 422, in plan view, includes the active region 411 and extends onto the outer peripheral region 412. The base electrode 422 is connected to the emitter and anode of the vertical element. The base electrode 422 has a peripheral portion that surrounds the exposed portion 421 in plan view. The peripheral portion is a portion of the base electrode 422 that overlaps with the protective film 45. The protective film 45 is disposed on one surface 41a of the semiconductor substrate 41 so as to cover the peripheral portion of the base electrode 422.
　接続電極４２３は、下地電極４２２上に積層配置されている。接続電極４２３は、上地電極、上部電極、上層電極、上地層、第２金属層とも称される。接続電極４２３は、焼結部材１０１との接合のために、Ａｕ（金）、Ａｇ（銀）、Ｐｔ（プラチナ）、Ｐｄ（パラジウム）などの貴金属を少なくとも含む。接続電極４２３は、貴金属とともに、卑金属を含んでもよい。 The connection electrode 423 is stacked on the base electrode 422. The connection electrode 423 is also referred to as a top electrode, an upper electrode, an upper layer electrode, a top layer, or a second metal layer. The connection electrode 423 contains at least a noble metal such as Au (gold), Ag (silver), Pt (platinum), or Pd (palladium) for bonding with the sintered member 101. The connection electrode 423 may contain a base metal as well as a noble metal.
　本実施形態の接続電極４２３は、Ｎｉ（ニッケル）を含む。Ｎｉは、下地電極４２２を構成するＡｌ合金よりも硬い。接続電極４２３は、Ｎｉと貴金属、たとえばＡｕまたはＡｇを含む。接続電極４２３は、たとえばめっき法によって多層に形成される。接続電極４２３の貴金属の少なくとも一部は、接合時において焼結部材１０１に拡散する。 The connection electrode 423 of this embodiment contains Ni (nickel). Ni is harder than the Al alloy that constitutes the base electrode 422. Connection electrode 423 includes Ni and a noble metal, such as Au or Ag. The connection electrode 423 is formed in multiple layers by, for example, a plating method. At least a portion of the noble metal of the connection electrode 423 diffuses into the sintered member 101 during bonding.
　接続電極４２３は、保護膜４５の開口部４５１において、下地電極４２２に積層配置されている。接続電極４２３の外周端は、開口部４５１を規定する保護膜４５の内周面に接触している。 The connection electrode 423 is stacked on the base electrode 422 in the opening 451 of the protective film 45 . The outer peripheral end of the connection electrode 423 is in contact with the inner peripheral surface of the protective film 45 that defines the opening 451.
　図６に示すように、エミッタ電極４２の露出部４２１の接合面、つまり接続電極４２３の上面は、保護膜４５の上面４５ａのうち、少なくとも開口部４５１の周囲部分と面一である。開口部４５１の周囲部分とは、開口端から所定の範囲である。周囲部分とは、露出部４２１の接合面に対して焼結部材１０１が位置ずれし得る公差範囲内の部分である。一例として本実施形態では、保護膜４５の上面４５ａのほぼ全面が、露出部４２１の接合面に対してほぼ面一となっている。面一とは、Ｚ方向における位置が等しい状態を示す。 As shown in FIG. 6, the bonding surface of the exposed portion 421 of the emitter electrode 42, that is, the upper surface of the connection electrode 423, is flush with at least the surrounding portion of the opening 451 of the upper surface 45a of the protective film 45. The peripheral portion of the opening 451 is a predetermined range from the opening end. The peripheral portion is a portion within a tolerance range in which the sintered member 101 may be misaligned with respect to the bonding surface of the exposed portion 421. As an example, in this embodiment, substantially the entire upper surface 45a of the protective film 45 is substantially flush with the bonding surface of the exposed portion 421. The term "flush" refers to a state in which the positions in the Z direction are the same.
　保護膜４５は、平面視においてガードリング４１３上に配置されている。保護膜４５は、ガードリング４１３を覆うように、一面４１ａ上に配置されている。保護膜４５は、平面視においてエミッタ電極４２およびパッド４４と重ならない位置に配置された配線部を覆っている。半導体素子４０は、配線部としてゲート配線４６を備えている。 The protective film 45 is arranged on the guard ring 413 in plan view. The protective film 45 is arranged on one surface 41a so as to cover the guard ring 413. The protective film 45 covers a wiring portion located at a position that does not overlap the emitter electrode 42 and the pad 44 in plan view. The semiconductor element 40 includes a gate wiring 46 as a wiring part.
　ゲート配線４６は、半導体基板４１に形成されたＩＧＢＴ１１のゲート電極とゲートパッド４４Ｇとを電気的に接続する。ゲート配線４６は、たとえばＡｌ（アルミニウム）を主成分とする材料を用いて形成された金属配線である。ゲート配線４６は、ポリシリコンに不純物が導入されてなる図示しないポリシリ配線を介して、ゲート電極に電気的に接続されている。ポリシリ配線は、エミッタ電極４２と半導体基板４１との間に配置されている。一例として本実施形態のゲート配線４６は、その全長が外周領域４１２上に配置されている。ゲート配線４６は、アクティブ領域４１１を取り囲むように環状に設けられている。ゲート配線４６の少なくとも一部は、上記した開口部４５１の周囲部分に配置されている。 The gate wiring 46 electrically connects the gate electrode of the IGBT 11 formed on the semiconductor substrate 41 and the gate pad 44G. The gate wiring 46 is a metal wiring formed using a material whose main component is Al (aluminum), for example. The gate wiring 46 is electrically connected to the gate electrode via a polysilicon wiring (not shown) formed by introducing impurities into polysilicon. The polysilicon wiring is arranged between the emitter electrode 42 and the semiconductor substrate 41. As an example, the entire length of the gate wiring 46 in this embodiment is arranged on the outer peripheral region 412. The gate wiring 46 is provided in a ring shape so as to surround the active region 411 . At least a portion of the gate wiring 46 is arranged around the opening 451 described above.
　＜接合構造＞
　次に、図７に基づいて、半導体素子４０の接合構造について説明する。図７は、図６に対応している。図７は、半導体素子４０と導電スペーサ７０との理想的な接合構造を示している。 <Joining structure>
Next, the bonding structure of the semiconductor element 40 will be described based on FIG. 7. FIG. 7 corresponds to FIG. 6. FIG. 7 shows an ideal bonding structure between the semiconductor element 40 and the conductive spacer 70.
　図７に示すように、焼結部材１０１は、半導体素子４０のエミッタ電極４２と導電スペーサ７０との間に介在している。焼結部材１０１は、エミッタ電極４２と導電スペーサ７０を接合している。 As shown in FIG. 7, the sintered member 101 is interposed between the emitter electrode 42 of the semiconductor element 40 and the conductive spacer 70. The sintered member 101 joins the emitter electrode 42 and the conductive spacer 70.
　焼結部材１０１は、ＡｇまたはＣｕを材料とする。焼結部材１０１は、Ａｇ粒子またはＣｕ粒子による焼結体である。焼結部材１０１は、はんだに較べて低温での接合が可能である。焼結部材１０１は、理想的には、平面視においてエミッタ電極４２の露出部４２１の接合面にほぼ一致するように配置されている。焼結部材１０１は、その外周端が開口部４５１を規定する保護膜４５の内周面とほぼ一致するように配置されている。保護膜４５は、理想的には、平面視において焼結部材１０１を内包している。 The sintered member 101 is made of Ag or Cu. The sintered member 101 is a sintered body made of Ag particles or Cu particles. The sintered member 101 can be joined at a lower temperature than solder. Ideally, the sintered member 101 is arranged so as to substantially match the bonding surface of the exposed portion 421 of the emitter electrode 42 in plan view. The sintered member 101 is arranged so that its outer peripheral end substantially coincides with the inner peripheral surface of the protective film 45 that defines the opening 451. The protective film 45 ideally includes the sintered member 101 in plan view.
　導電スペーサ７０は、焼結部材１０１との接合面に、図示しない金属膜を有している。金属膜は、接続電極４２３同様、貴金属を少なくとも含む。本実施形態では、金属膜がＮｉと貴金属、たとえばＡｕまたはＡｇを含むめっき膜である。導電スペーサ７０は、たとえば平面略矩形状をなしている。導電スペーサ７０の外周端は、平面視において焼結部材１０１の外周端よりも外側、もしくは、ほぼ一致するように配置されている。 The conductive spacer 70 has a metal film (not shown) on the joint surface with the sintered member 101. The metal film contains at least a precious metal, like the connection electrode 423. In this embodiment, the metal film is a plating film containing Ni and a precious metal, such as Au or Ag. The conductive spacer 70 has, for example, a substantially rectangular shape in plan view. The outer periphery of the conductive spacer 70 is positioned outside or substantially coincident with the outer periphery of the sintered member 101 in plan view.
　＜接合方法＞
　次に、図８に基づき、上記した接合構造の形成方法、つまり接合方法について説明する。図８は、接合方法を示す断面図である。図８は、図７に対応している。 <Joining method>
Next, a method for forming the above-described bonding structure, that is, a bonding method will be described based on FIG. 8. FIG. 8 is a cross-sectional view showing the joining method. FIG. 8 corresponds to FIG. 7.
　本実施形態では、焼結部材１０１を形成するために、焼結シート１０１Ｓを用いる。焼結シート１０１Ｓは、焼結フィルムと称されることがある。焼結シート１０１Ｓは、ＡｇまたはＣｕを含んでいる。図８に示すように、焼結シート１０１Ｓを、半導体素子４０のエミッタ電極４２の露出部４２１上に配置する。焼結シート１０１Ｓは、加圧前の状態で、平面視において保護膜４５の開口部４５１よりも小さい所定のサイズを有している。 In this embodiment, in order to form the sintered member 101, a sintered sheet 101S is used. The sintered sheet 101S is sometimes referred to as a sintered film. The sintered sheet 101S contains Ag or Cu. As shown in FIG. 8, the sintered sheet 101S is placed on the exposed portion 421 of the emitter electrode 42 of the semiconductor element 40. The sintered sheet 101S has a predetermined size smaller than the opening 451 of the protective film 45 in plan view before being pressurized.
　次いで、焼結シート１０１Ｓ上に導電スペーサ７０を配置して積層体とする。そして、加熱しながら、図示しない加圧装置で導電スペーサ７０側から積層体を加圧する。これにより、焼結シート１０１Ｓはエミッタ電極４２の露出部４２１と導電スペーサ７０との対向面間で押し拡げられて厚みが薄くなるとともに、焼結して焼結部材１０１となる。焼結部材１０１は、接合状態で上記した所定の位置関係となるように、焼結シート１０１Ｓのサイズが決定される。 Next, conductive spacers 70 are placed on the sintered sheet 101S to form a laminate. Then, while heating, the laminate is pressurized from the conductive spacer 70 side using a pressurizing device (not shown). As a result, the sintered sheet 101S is expanded between the facing surfaces of the exposed portion 421 of the emitter electrode 42 and the conductive spacer 70, becomes thinner, and is sintered to become the sintered member 101. The size of the sintered sheet 101S of the sintered member 101 is determined so that the above-described predetermined positional relationship is achieved in the joined state.
　＜第１実施形態のまとめ＞
　焼結部材は、融点よりも低い温度の加熱により形成される。焼結部材は、接合時においてはんだのように溶融状態にならない。焼結部材は、はんだに較べると主電極や導電部材に対する濡れ性が低い。焼結部材は、接合時において主電極の表面や導電部材の表面を、はんだのように濡れ拡がらない。焼結部材は、保護膜上に配置され得る。 <Summary of the first embodiment>
Sintered members are formed by heating below the melting point. Sintered members do not become molten like solder during bonding. Sintered members have lower wettability with respect to main electrodes and conductive members than solder. The sintered member does not wet and spread on the surface of the main electrode or the surface of the conductive member during bonding, unlike solder. A sintered member may be placed on the protective film.
　図９および図１０は、参考例を示している。図９および図１０は、いずれも接合方法を示している。図９および図１０は、図８に対応している。参考例では、各要素の符号を、半導体装置２０の関連する要素の符号の末尾にｒを付加したものとしている。 9 and 10 show reference examples. 9 and 10 both show the joining method. 9 and 10 correspond to FIG. 8. In the reference example, the reference numeral of each element is such that r is added to the end of the reference numeral of the related element of the semiconductor device 20.
　図９および図１０に示すように、参考例では保護膜４５ｒの上面４５ａｒが、Ｚ方向においてエミッタ電極４２ｒの露出部４２１ｒの接合面よりも上方に位置している。これにより、上面４５ａと露出部４２１ｒの接合面との間に、保護膜４５ｒ側を凸とする段差が形成されている。 As shown in FIGS. 9 and 10, in the reference example, the upper surface 45ar of the protective film 45r is located above the bonding surface of the exposed portion 421r of the emitter electrode 42r in the Z direction. As a result, a step is formed between the upper surface 45a and the bonding surface of the exposed portion 421r, with the protective film 45r side being convex.
　図９に示す参考例では、接合状態で、焼結部材の周方向の少なくとも一部が保護膜の内周面に接触するように、焼結シート１０１Ｓｒのサイズが定められている。このような構成では、図９に示すように、焼結シート１０１Ｓｒが製造公差内で位置ずれし、保護膜４５ｒの上面４５ａｒにかかるように配置されると、焼結接合時の加圧によって保護膜４５ｒに応力が集中する。よって、保護膜４５ｒ、保護膜４５ｒに覆われたゲート配線４６ｒなどの配線部、ひいては保護膜４５ｒ直下の基板部分が損傷する虞がある。なお、位置ずれにより焼結シート１０１Ｓｒの一部が保護膜４５ｒの上面４５ａｒに配置される構成であれば、同様の問題が生じ得る。 In the reference example shown in FIG. 9, the size of the sintered sheet 101Sr is determined so that at least a portion of the sintered member in the circumferential direction contacts the inner circumferential surface of the protective film in the bonded state. In such a configuration, as shown in FIG. 9, if the sintered sheet 101Sr is misaligned within the manufacturing tolerance and placed so as to rest on the upper surface 45ar of the protective film 45r, stress will be concentrated on the protective film 45r due to the pressure applied during sinter bonding. This may result in damage to the protective film 45r, wiring parts such as the gate wiring 46r covered by the protective film 45r, and even the substrate part directly below the protective film 45r. Note that a similar problem may occur if a configuration is used in which a portion of the sintered sheet 101Sr is placed on the upper surface 45ar of the protective film 45r due to misalignment.
　図１０に示す参考例では、焼結シート１０１Ｓｒが製造公差内で位置ずれしても、保護膜４５ｒの上面４５ａｒに配置されないように、焼結シート１０１Ｓｒのサイズが定められている。つまり、焼結シート１０１Ｓｒのサイズが小さい。このため、焼結接合後において図示しない焼結部材の断面積が小さくなり、熱抵抗や電流密度が増加してしまう。 In the reference example shown in FIG. 10, the size of the sintered sheet 101Sr is determined so that even if the sintered sheet 101Sr is misaligned within manufacturing tolerances, it will not be placed on the upper surface 45ar of the protective film 45r. In other words, the size of the sintered sheet 101Sr is small. For this reason, after sintering and joining, the cross-sectional area of the sintered member (not shown) becomes smaller, resulting in increased thermal resistance and current density.
　これに対し、本実施形態の半導体装置２０によれば、保護膜４５の上面４５ａが、Ｚ方向においてエミッタ電極４２の露出部４２１の接合面に対して面一の位置となっている。つまり上面４５ａのＺ方向の位置は、露出部４２１の接合面の位置とほぼ等しい。 In contrast, according to the semiconductor device 20 of this embodiment, the upper surface 45a of the protective film 45 is flush with the bonding surface of the exposed portion 421 of the emitter electrode 42 in the Z direction. In other words, the position of the upper surface 45a in the Z direction is approximately equal to the position of the bonding surface of the exposed portion 421.
　この位置関係により、図１１に示すようにエミッタ電極４２の露出部４２１に対して焼結シート１０１Ｓ（焼結部材１０１）の位置がずれて配置されたとしても、焼結接合する際の加圧により保護膜４５側に応力が集中するのを抑制することができる。また、焼結部材１０１の平面視の面積を小さくしなくても、保護膜４５側に応力が集中するのを抑制することができる。この結果、信頼性を向上できる半導体装置２０を提供することができる。保護膜４５側に応力が集中するのを抑制しつつ、熱抵抗や電流密度が増加するのを抑制することができる。 Due to this positional relationship, even if the position of the sintered sheet 101S (sintered member 101) is shifted from the exposed part 421 of the emitter electrode 42 as shown in FIG. This makes it possible to suppress concentration of stress on the protective film 45 side. Further, stress concentration on the protective film 45 side can be suppressed without reducing the area of the sintered member 101 in plan view. As a result, a semiconductor device 20 with improved reliability can be provided. It is possible to suppress an increase in thermal resistance and current density while suppressing stress concentration on the protective film 45 side.
　一例として本実施形態の半導体素子４０は、平面視においてエミッタ電極４２と重ならない位置に配置され、保護膜４５により覆われた配線部として、ゲート配線４６を有している。また、半導体素子４０が、外周領域４１２に形成された耐圧構造部として、ガードリング４１３を有している。しかしながら、上記した保護膜上面の位置関係により、焼結接合時に、保護膜４５に応力が集中するのを抑制し、ひいては保護膜４５に覆われたゲート配線４６などの配線部、ひいては保護膜４５の直下に位置する基板部分が損傷するのを抑制することができる。 As an example, the semiconductor element 40 of this embodiment has a gate wiring 46 as a wiring portion that is arranged at a position that does not overlap the emitter electrode 42 in a plan view and is covered by a protective film 45. The semiconductor element 40 also has a guard ring 413 as a pressure-resistant structure portion formed in the peripheral region 412. However, due to the positional relationship of the upper surface of the protective film described above, it is possible to suppress the concentration of stress on the protective film 45 during sintering bonding, and thus to suppress damage to wiring portions such as the gate wiring 46 covered by the protective film 45, and ultimately to the substrate portion located directly below the protective film 45.
　＜変形例＞
　保護膜４５の上面４５ａは、少なくとも開口部４５１の周囲部分において、エミッタ電極４２の露出部４２１の接合面と面一の関係にあればよい。たとえば、保護膜４５の上面４５ａのうち、開口部４５１の周囲部分を露出部４２１の接合面に対して面一とし、その他の部分を露出部４２１の接合面よりも上方としてもよい。 <Modification>
It is sufficient that the upper surface 45a of the protective film 45 is flush with the bonding surface of the exposed portion 421 of the emitter electrode 42, at least in the peripheral portion of the opening 451. For example, the peripheral portion of the upper surface 45a of the protective film 45 around the opening 451 may be flush with the bonding surface of the exposed portion 421, and the other portion may be located above the bonding surface of the exposed portion 421.
　（第２実施形態）
　この実施形態は、先行する実施形態を基礎的形態とする変形例であり、先行実施形態の記載を援用できる。先行実施形態では、保護膜４５の上面４５ａをエミッタ電極４２の上面に対して面一の位置とした。これに代えて、保護膜４５の上面４５ａをエミッタ電極４２の上面に対して面一ではない位置としてもよい。 (Second embodiment)
This embodiment is a modification based on the previous embodiment, and the description of the previous embodiment can be used. In the preceding embodiment, the upper surface 45a of the protective film 45 was positioned flush with the upper surface of the emitter electrode 42. Alternatively, the upper surface 45a of the protective film 45 may be positioned not flush with the upper surface of the emitter electrode 42.
　図１２は、本実施形態に係る半導体装置２０において、半導体素子４０を示す断面図である。図１２は、図６に対応している。図１２に示すように、保護膜４５の上面４５ａのうち、開口部４５１の周囲部分は、Ｚ方向においてエミッタ電極４２の露出部４２１の接合面よりも一面４１ａに近い位置となっている。上面４５ａの他の部分も、エミッタ電極４２の露出部４２１の接合面よりも一面４１ａに近い位置となっている。 FIG. 12 is a cross-sectional view showing the semiconductor element 40 in the semiconductor device 20 according to this embodiment. FIG. 12 corresponds to FIG. 6. As shown in FIG. 12, the portion of the upper surface 45a of the protective film 45 surrounding the opening 451 is located closer to the surface 41a than the bonding surface of the exposed portion 421 of the emitter electrode 42 in the Z direction. The other portions of the upper surface 45a are also located closer to the surface 41a than the bonding surface of the exposed portion 421 of the emitter electrode 42.
　つまり、保護膜４５の上面４５ａは、その全域においてエミッタ電極４２の露出部４２１の接合面よりも一面４１ａに近い。一面４１ａを基準とする上面までの高さは、保護膜４５のほうがエミッタ電極４２よりも低い。保護膜４５の上面４５ａは、エミッタ電極４２の上面よりも下方に位置する。半導体装置２０のその他の構成は、先行実施形態に記載の構成と同様である。 In other words, the entire upper surface 45a of the protective film 45 is closer to the surface 41a than the bonding surface of the exposed portion 421 of the emitter electrode 42. The height of the protective film 45 to the top surface with respect to the one surface 41 a is lower than that of the emitter electrode 42 . The upper surface 45a of the protective film 45 is located below the upper surface of the emitter electrode 42. The other configurations of the semiconductor device 20 are similar to those described in the preceding embodiments.
　＜第２実施形態のまとめ＞
　本実施形態の半導体装置２０によれば、保護膜４５の上面４５ａが、Ｚ方向においてエミッタ電極４２の露出部４２１の接合面よりも半導体基板４１の一面４１ａに近い位置となっている。この位置関係により、焼結シート１０１Ｓが位置ずれしたとしても、上面４５ａの開口部周囲に接触しないか、接触したとしても保護膜４５に作用する応力がより小さくなる。よって、半導体装置２０の信頼性をさらに向上することができる。 <Summary of the second embodiment>
According to the semiconductor device 20 of this embodiment, the upper surface 45a of the protective film 45 is located closer to the one surface 41a of the semiconductor substrate 41 than the bonding surface of the exposed portion 421 of the emitter electrode 42 in the Z direction. Due to this positional relationship, even if the sintered sheet 101S is displaced, it does not come into contact with the periphery of the opening of the upper surface 45a, or even if it does, the stress acting on the protective film 45 becomes smaller. Therefore, the reliability of the semiconductor device 20 can be further improved.
　＜変形例＞
　保護膜４５の上面４５ａのうち、少なくとも開口部４５１の周囲部分が、エミッタ電極４２の露出部４２１の接合面よりも下方に位置すればよい。たとえば、保護膜４５の上面４５ａのうち、開口部４５１の周囲部分を露出部４２１の接合面よりも下方とし、その他の部分を露出部４２１の接合面よりも上方としてもよい。好ましくは、保護膜４５の上面４５ａのうち、開口部４５１の周囲部分を露出部４２１の接合面よりも下方とし、その他の部分を露出部４２１の接合面に対して面一以下にするとよい。表面が凹凸を有しつつ、上記した位置関係を満たしてもよい。 <Modified example>
At least a portion of the upper surface 45a of the protective film 45 surrounding the opening 451 may be located below the bonding surface of the exposed portion 421 of the emitter electrode 42. For example, a portion of the upper surface 45a of the protective film 45 around the opening 451 may be placed below the bonding surface of the exposed portion 421, and the other portion may be placed above the bonding surface of the exposed portion 421. Preferably, a portion of the upper surface 45a of the protective film 45 around the opening 451 is located below the bonding surface of the exposed portion 421, and the other portion is flush with or less than the bonding surface of the exposed portion 421. The above-described positional relationship may be satisfied while the surface has irregularities.
　（第３実施形態）
　この実施形態は、先行する実施形態を基礎的形態とする変形例であり、先行実施形態の記載を援用できる。先行実施形態では、保護膜４５およびゲート配線４６を外周領域４１２上のみに配置していた。これに代えて、保護膜４５およびゲート配線４６をアクティブ領域４１１上に配置してもよい。 (Third embodiment)
This embodiment is a modification based on the previous embodiment, and the description of the previous embodiment can be used. In the previous embodiment, the protective film 45 and the gate wiring 46 were arranged only on the outer peripheral region 412. Alternatively, the protective film 45 and the gate wiring 46 may be placed on the active region 411.
　図１３は、本実施形態に係る半導体装置２０において、半導体素子４０を示す平面図である。図１３は、図５に対応している。図１４は、図１３のXIV-XIV線に沿う断面図である。図１４は、半導体素子４０と導電スペーサ７０との接合構造を示している。図１４は、図７に対応している。 FIG. 13 is a plan view showing the semiconductor element 40 in the semiconductor device 20 according to this embodiment. FIG. 13 corresponds to FIG. 5. FIG. 14 is a sectional view taken along the line XIV-XIV in FIG. 13. FIG. 14 shows a bonding structure between the semiconductor element 40 and the conductive spacer 70. FIG. 14 corresponds to FIG. 7.
　図１３および図１４に示すように、保護膜４５は、外周部４５３と、区画部４５４を有している。外周部４５３は、平面視において外周領域４１２とほぼ一致するように配置されている。区画部４５４は、エミッタ電極４２を複数に区画している。一例として本実施形態の区画部４５４は、Ｘ方向においてエミッタ電極４２を略二等分するように設けられている。区画部４５４は、開口部４５１を２つに区画している。区画部４５４は、半導体素子４０の中心を通り、Ｙ方向に延びている。区画部４５４の端部のひとつはパッド４４側において外周部４５３に連なり、端部の他のひとつはパッド４４とは反対側において外周部４５３に連なっている。 As shown in FIGS. 13 and 14, the protective film 45 has an outer peripheral portion 453 and a partition portion 454. The outer peripheral portion 453 is arranged to substantially coincide with the outer peripheral region 412 in a plan view. The division section 454 divides the emitter electrode 42 into a plurality of sections. As an example, the partition section 454 of this embodiment is provided so as to substantially divide the emitter electrode 42 into two in the X direction. The dividing portion 454 divides the opening 451 into two. The partition portion 454 passes through the center of the semiconductor element 40 and extends in the Y direction. One of the ends of the partition 454 is connected to the outer peripheral part 453 on the pad 44 side, and the other end is connected to the outer peripheral part 453 on the opposite side from the pad 44.
　ゲート配線４６は、外周配線部４６１と、区画配線部４６２を有している。外周配線部４６１は、平面視において外周部４５３と重なる位置に配置されている。外周配線部４６１は、先行実施形態に示したゲート配線４６に相当する。一例として外周配線部４６１は、矩形環状をなしている。区画配線部４６２は、平面視において区画部４５４と重なる位置に配置されている。区画配線部４６２は、半導体素子４０の中心を通り、Ｙ方向に延びている。区画配線部４６２の端部のひとつはパッド４４側において外周配線部４６１に連なり、端部の他のひとつはパッド４４とは反対側において外周配線部４６１に連なっている。 The gate wiring 46 has an outer wiring part 461 and a partition wiring part 462. The outer circumferential wiring portion 461 is arranged at a position overlapping the outer circumferential portion 453 in a plan view. The outer peripheral wiring portion 461 corresponds to the gate wiring 46 shown in the preceding embodiment. As an example, the outer peripheral wiring portion 461 has a rectangular ring shape. The partition wiring section 462 is arranged at a position overlapping with the partition section 454 in plan view. The partition wiring section 462 passes through the center of the semiconductor element 40 and extends in the Y direction. One end of the divided wiring section 462 is connected to the outer peripheral wiring section 461 on the pad 44 side, and the other end is connected to the outer peripheral wiring section 461 on the opposite side from the pad 44.
　区画配線部４６２は、２つに区画されたエミッタ電極４２の間に配置されている。区画された露出部４２１および区画配線部４６２の並び方向、つまりＸ方向において、区画配線部４６２の幅は、露出部４２１それぞれの幅よりも狭い。Ｘ方向において、区画部４５４の幅は、露出部４２１それぞれの幅よりも狭い。 The divided wiring section 462 is arranged between the two divided emitter electrodes 42. In the direction in which the divided exposed portions 421 and the divided wiring portions 462 are lined up, that is, in the X direction, the width of the divided wiring portions 462 is narrower than the width of each of the exposed portions 421 . In the X direction, the width of the partition section 454 is narrower than the width of each of the exposed sections 421.
　図１４に示すように、焼結部材１０１は、区画された複数の露出部４２１を跨いで配置されている。焼結部材１０１は、平面視において露出部４２１のそれぞれと重なる位置だけでなく、区画部４５４と重なる位置にも配置されている。焼結部材１０１は、区画部４５４における上面４５ａの上方に位置している。 As shown in FIG. 14, the sintered member 101 is arranged across a plurality of partitioned exposed parts 421. The sintered member 101 is arranged not only at a position overlapping each of the exposed parts 421 in a plan view but also at a position overlapping with the partition part 454. The sintered member 101 is located above the upper surface 45a of the partition 454.
　保護膜４５の開口部４５１の周囲部分は、区画部４５４を含む。先行実施形態同様、保護膜４５の上面４５ａのうち、少なくとも開口部４５１の周囲部分は、露出部４２１の接合面に対して面一以下となっている。一例として本実施形態では、区画部４５４を含む周囲部分の上面４５ａが、露出部４２１の接合面よりも下方に位置している。半導体装置２０のその他の構成は、先行実施形態に記載の構成と同様である。 The area around the opening 451 of the protective film 45 includes a partition 454 . As in the previous embodiment, at least a portion of the upper surface 45 a of the protective film 45 around the opening 451 is flush with or less than the bonding surface of the exposed portion 421 . As an example, in this embodiment, the upper surface 45a of the peripheral portion including the partition portion 454 is located below the joint surface of the exposed portion 421. The other configurations of the semiconductor device 20 are similar to those described in the preceding embodiments.
　＜第３実施形態のまとめ＞
　本実施形態の半導体装置２０によれば、外周領域４１２における開口部４５１の周囲部分の上面４５ａだけでなく、区画配線部４６２を覆う区画部４５４の上面４５ａも、露出部４２１の接合面に対して面一以下の位置となっている。これにより、複数の露出部４２１を跨ぐように焼結シート１０１Ｓ（焼結部材１０１）を配置する構成において、焼結接合する際の加圧により区画部４５４に応力が集中するのを抑制することができる。また、保護膜４５の区画部４５４に覆われた区画配線部４６２や区画部４５４の直下に位置する基板部分が損傷するのを抑制することができる。 <Summary of the third embodiment>
According to the semiconductor device 20 of the present embodiment, not only the upper surface 45a of the peripheral portion of the opening 451 in the outer peripheral region 412 but also the upper surface 45a of the partitioned portion 454 covering the partitioned wiring portion 462 is connected to the bonding surface of the exposed portion 421. It is located at less than the same level. As a result, in a configuration in which the sintered sheet 101S (sintered member 101) is arranged so as to straddle the plurality of exposed parts 421, it is possible to suppress concentration of stress on the partitioned part 454 due to pressure during sintering and joining. Can be done. Further, it is possible to suppress damage to the partitioned wiring portion 462 covered by the partitioned portion 454 of the protective film 45 and the substrate portion located directly below the partitioned portion 454.
　また、Ｘ方向において、区画配線部４６２の幅は、露出部４２１それぞれの幅よりも狭い。これにより、焼結シート１０１Ｓ（焼結部材１０１）が複数の露出部４２１を跨ぐ構成において、複数の露出部４２１による焼結シート１０１Ｓの支持が安定する。よって、焼結接合時に過剰な応力が作用するのを抑制することができる。 Furthermore, in the X direction, the width of the divided wiring section 462 is narrower than the width of each of the exposed sections 421. Thereby, in a configuration in which the sintered sheet 101S (sintered member 101) straddles the plurality of exposed parts 421, the support of the sintered sheet 101S by the plurality of exposed parts 421 is stabilized. Therefore, it is possible to suppress excessive stress from acting upon sintering and joining.
　＜変形例＞
　区画部４５４に覆われる配線部は、ゲート配線４６である区画配線部４６２に限定されない。平面視においてエミッタ電極４２と重ならず、区画部４５４と重なる位置に配置された配線であればよい。 <Modified example>
The wiring section covered by the partition section 454 is not limited to the partition wiring section 462 which is the gate wiring 46 . Any wiring may be used as long as it does not overlap the emitter electrode 42 and overlaps the partition 454 in plan view.
　区画部４５４の配置は、上記した例に限定されない。たとえば図１５に示すように３つの区画部４５４により、露出部４２１が４つに区画された構成としてもよい。区画部４５４は、露出部４２１をＸ方向において略四等分している。図１５は、図１３に対応している。 The arrangement of the partition portions 454 is not limited to the above example. For example, as shown in FIG. 15, the exposed portion 421 may be divided into four sections by three partition sections 454. The partition portion 454 divides the exposed portion 421 into approximately four equal parts in the X direction. FIG. 15 corresponds to FIG. 13.
　図示を省略するが、たとえば露出部４２１を略四等分するように、区画部４５４を平面略十字状に配置してもよい。このような区画部４５４は、Ｘ方向に延びる部分と、Ｙ方向に延びる部分を含む。 Although not shown, the partition portions 454 may be arranged in a substantially cross shape in plan, for example, so as to divide the exposed portion 421 into approximately four equal parts. The partition 454 includes a portion extending in the X direction and a portion extending in the Y direction.
　（他の実施形態）
　この明細書および図面等における開示は、例示された実施形態に制限されない。開示は、例示された実施形態と、それらに基づく当業者による変形態様を包含する。たとえば、開示は、実施形態において示された部品および／または要素の組み合わせに限定されない。開示は、多様な組み合わせによって実施可能である。開示は、実施形態に追加可能な追加的な部分をもつことができる。開示は、実施形態の部品および／または要素が省略されたものを包含する。開示は、ひとつの実施形態と他の実施形態との間における部品および／または要素の置き換え、または組み合わせを包含する。開示される技術的範囲は、実施形態の記載に限定されない。開示されるいくつかの技術的範囲は、請求の範囲の記載によって示され、さらに請求の範囲の記載と均等の意味および範囲内でのすべての変更を含むものと解されるべきである。 (Other embodiments)
The disclosure in this specification, drawings, etc. is not limited to the illustrated embodiments. The disclosure includes the illustrated embodiments and variations thereon by those skilled in the art. For example, the disclosure is not limited to the combinations of parts and/or elements illustrated in the embodiments. The disclosure can be implemented in various combinations. The disclosure may have additional parts that can be added to the embodiments. The disclosure includes those in which parts and/or elements of the embodiments are omitted. The disclosure encompasses any substitutions or combinations of parts and/or elements between one embodiment and other embodiments. The disclosed technical scope is not limited to the description of the embodiments. The technical scope of some of the disclosed technical scopes is indicated by the description of the claims, and should be understood to include equivalent meanings and all changes within the scope of the claims.
　明細書および図面等における開示は、請求の範囲の記載によって限定されない。明細書および図面等における開示は、請求の範囲に記載された技術的思想を包含し、さらに請求の範囲に記載された技術的思想より多様で広範な技術的思想に及んでいる。よって、請求の範囲の記載に拘束されることなく、明細書および図面等の開示から、多様な技術的思想を抽出することができる。 The disclosure in the specification, drawings, etc. is not limited by the scope of the claims. The disclosure in the specification, drawings, etc. includes the technical ideas described in the claims, and further extends to a more diverse and broader range of technical ideas than the technical ideas described in the claims. Therefore, various technical ideas can be extracted from the disclosure of the specification, drawings, etc. without being restricted by the claims.
　ある要素または層が「上にある」、「連結されている」、「接続されている」または「結合されている」と言及されている場合、それは、他の要素、または他の層に対して、直接的に上に、連結され、接続され、または結合されていることがあり、さらに、介在要素または介在層が存在していることがある。対照的に、ある要素が別の要素または層に「直接的に上に」、「直接的に連結されている」、「直接的に接続されている」または「直接的に結合されている」と言及されている場合、介在要素または介在層は存在しない。要素間の関係を説明するために使用される他の言葉は、同様のやり方で（例えば、「間に」対「直接的に間に」、「隣接する」対「直接的に隣接する」など）解釈されるべきである。この明細書で使用される場合、用語「および／または」は、関連する列挙されたひとつまたは複数の項目に関する任意の組み合わせ、およびすべての組み合わせを含む。 When an element or layer is referred to as being ``on'', ``coupled'', ``connected'' or ``coupled with'' another element or layer, it is referring to another element or layer. may be connected, connected, or bonded directly thereon, and intervening elements or layers may be present. In contrast, one element is "directly upon", "directly coupled to," "directly connected to," or "directly coupled to" another element or layer. , there are no intervening elements or layers present. Other words used to describe relationships between elements can be used in a similar manner (e.g., "between" vs. "directly between", "adjacent" vs. "directly adjacent", etc.). ) should be interpreted. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
　空間的に相対的な用語「内」、「外」、「裏」、「下」、「低」、「上」、「高」などは、図示されているような、ひとつの要素または特徴の他の要素または特徴に対する関係を説明する記載を容易にするためにここでは利用されている。空間的に相対的な用語は、図面に描かれている向きに加えて、使用または操作中の装置の異なる向きを包含することを意図することができる。例えば、図中の装置をひっくり返すと、他の要素または特徴の「下」または「真下」として説明されている要素は、他の要素または特徴の「上」に向けられる。したがって、用語「下」は、上と下の両方の向きを包含することができる。この装置は、他の方向に向いていてもよく（９０度または他の向きに回転されてもよい）、この明細書で使用される空間的に相対的な記述子はそれに応じて解釈される。 Spatial relative terms such as "in", "out", "behind", "below", "low", "above", "high" etc. refer to a single element or feature as illustrated. It is used herein to facilitate description that describes relationships to other elements or features. Spatially relative terms may be intended to encompass different orientations of the device during use or operation in addition to the orientation depicted in the figures. For example, when the device in the figures is turned over, elements described as being "below" or "beneath" other elements or features are oriented "above" the other elements or features. Thus, the term "bottom" can encompass both orientations, top and bottom. The device may be oriented in other directions (rotated 90 degrees or other orientations) and the spatially relative descriptors used in this specification shall be interpreted accordingly. .
　車両の駆動システム１は、上記した構成に限定されない。たとえば、モータジェネレータ３をひとつ備える例を示したが、これに限定されない。複数のモータジェネレータを備えてもよい。電力変換装置４が、電力変換部としてインバータ６を備える例を示したが、これに限定されない。たとえば、複数のインバータを備える構成としてもよい。すくなくともひとつのインバータと、コンバータを備える構成としてもよい。コンバータのみを備えてもよい。 The vehicle drive system 1 is not limited to the above configuration. For example, although an example is shown in which one motor generator 3 is provided, the present invention is not limited to this. A plurality of motor generators may be provided. Although an example has been shown in which the power conversion device 4 includes the inverter 6 as a power conversion section, the present invention is not limited to this. For example, a configuration may include a plurality of inverters. The configuration may include at least one inverter and a converter. It may also include only a converter.
　半導体装置２０の構成は、上記した例に限定されない。半導体装置２０は、両面異種電極を有する半導体素子と、導電部材と、保護膜から露出する第１主電極と導電部材とを接合する焼結部材を少なくとも備えればよい。 The configuration of the semiconductor device 20 is not limited to the above example. The semiconductor device 20 may include at least a semiconductor element having dissimilar electrodes on both sides, a conductive member, and a sintered member that bonds the first main electrode exposed from the protective film to the conductive member.
　スイッチング素子は、ＩＧＢＴ１１に限定されない。たとえばＭＯＳＦＥＴを採用してもよい。ＭＯＳＦＥＴは、Metal Oxide Semiconductor Field Effect Transistorの略称である。 The switching element is not limited to the IGBT 11. For example, a MOSFET may be used. MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor.
　導電スペーサ７０に代えて、配線部材５０に凸部を設けてもよい。この場合、配線部材５０が導電部材に相当する。 Instead of the conductive spacer 70, a protrusion may be provided on the wiring member 50. In this case, the wiring member 50 corresponds to a conductive member.
　半導体装置２０として、両面放熱構造の例を示したが、これに限定されない。片面放熱構造にも適用することができる。たとえばコレクタ電極４３はヒートシンクまたは基板の金属体に接続され、エミッタ電極４２はリードに接続される。この場合、リードが導電部材に相当する。 Although an example of a double-sided heat dissipation structure is shown as the semiconductor device 20, the present invention is not limited to this. It can also be applied to a single-sided heat dissipation structure. For example, the collector electrode 43 is connected to a heat sink or a metal body of a substrate, and the emitter electrode 42 is connected to a lead. In this case, the lead corresponds to the conductive member.
　半導体装置２０が、ひとつのアームを構成する半導体素子４０をひとつのみ備える例を示したが、これに限定されない。半導体装置２０が、ひとつのアームを構成する複数の半導体素子４０を備えてもよい。つまり、複数の半導体素子４０が互いに並列接続されてひとつのアームを構成してもよい。また、半導体装置２０が、一相分の上下アーム回路９を構成する複数の半導体素子４０を備えてもよい。複数相の上下アーム回路９を構成する複数の半導体素子４０を備えてもよい。 Although an example has been shown in which the semiconductor device 20 includes only one semiconductor element 40 constituting one arm, the present invention is not limited to this. The semiconductor device 20 may include a plurality of semiconductor elements 40 forming one arm. That is, a plurality of semiconductor elements 40 may be connected in parallel to each other to form one arm. Furthermore, the semiconductor device 20 may include a plurality of semiconductor elements 40 that constitute the upper and lower arm circuits 9 for one phase. A plurality of semiconductor elements 40 forming a multi-phase upper and lower arm circuit 9 may be provided.
　配線部材５０、６０の裏面５０ｂ、６０ｂが、封止体３０から露出する例を示したが、これに限定されない。裏面５０ｂ、６０ｂの少なくとも一方が、封止体３０によって覆われた構成としてもよい。裏面５０ｂ、６０ｂの少なくとも一方が、封止体３０とは別の図示しない絶縁部材によって覆われた構成としてもよい。半導体装置２０が封止体３０を備えない構成としてもよい。 Although an example has been shown in which the back surfaces 50b and 60b of the wiring members 50 and 60 are exposed from the sealing body 30, the present invention is not limited to this. At least one of the back surfaces 50b and 60b may be covered with the sealing body 30. At least one of the back surfaces 50b and 60b may be covered with an insulating member (not shown) that is separate from the sealing body 30. The semiconductor device 20 may be configured without the sealing body 30.
　第１主電極であるエミッタ電極４２の構成は、上記した例に限定されない。たとえば図１６に示すように、エミッタ電極４２が中間電極４２４を有してもよい。中間電極４２４は、Ａｌを主成分とする下地電極４２２と接続電極４２３との間に配置されている。中間電極４２４は、Ｃｕを主成分とする材料を用いて形成されている。エミッタ電極４２は、シリコン酸化膜などの絶縁膜４７に設けられたコンタクトホールを介して半導体基板４１に接続されている。 The configuration of the emitter electrode 42, which is the first main electrode, is not limited to the above example. For example, as shown in FIG. 16, the emitter electrode 42 may have an intermediate electrode 424. The intermediate electrode 424 is arranged between the base electrode 422 whose main component is Al and the connection electrode 423. The intermediate electrode 424 is formed using a material containing Cu as a main component. The emitter electrode 42 is connected to the semiconductor substrate 41 through a contact hole provided in an insulating film 47 such as a silicon oxide film.
　図１７に示す例では、下地電極４２２Ａおよびゲート配線４６Ａが、Ｃｕを主成分とする材料を用いて形成されている。そして、Ｃｕを主成分とする下地電極４２２Ａ上に接続電極４２３が積層配置されている。Ｃｕを主成分とするゲート配線４６Ａは、保護膜４５によって覆われている。 In the example shown in FIG. 17, the base electrode 422A and the gate wiring 46A are formed using a material containing Cu as a main component. A connection electrode 423 is laminated on a base electrode 422A whose main component is Cu. The gate wiring 46A whose main component is Cu is covered with a protective film 45.
　図１６および図１７では、保護膜４５の上面４５ａが露出部４２１の接合面に対して面一の例を示している。しかしながら、保護膜４５の上面４５ａが露出部４２１の接合面よりも下方に位置する構成としてもよいのは言うまでもない。 16 and 17 show an example in which the upper surface 45a of the protective film 45 is flush with the bonding surface of the exposed portion 421. However, it goes without saying that the upper surface 45a of the protective film 45 may be located below the bonding surface of the exposed portion 421.
　（技術的思想の開示）
　この明細書は、以下に列挙する複数の項に記載された複数の技術的思想を開示している。いくつかの項は、後続の項において先行する項を択一的に引用する多項従属形式（a multiple dependent form）により記載されている場合がある。さらに、いくつかの項は、他の多項従属形式の項を引用する多項従属形式（a multiple dependent form referring to another multiple dependent form）により記載されている場合がある。これらの多項従属形式で記載された項は、複数の技術的思想を定義している。 (Disclosure of technical ideas)
This specification discloses multiple technical ideas described in the following multiple dependent claims. Some of the claims may be described in a multiple dependent form, in which the subsequent claim alternatively refers to the preceding claim. Furthermore, some of the claims may be described in a multiple dependent form, in which the subsequent claim alternatively refers to the preceding claim. The claims described in these multiple dependent forms define multiple technical ideas.
　＜技術的思想１＞
　半導体基板（４１）と、前記半導体基板の一面に設けられた第１主電極（４２）と、板厚方向において前記一面とは反対の裏面に設けられた第２主電極（４３）と、前記一面に設けられ、前記第１主電極を接合可能に露出させる開口部（４５１）を備えた保護膜（４５）と、を有する半導体素子（４０）と、
　前記第１主電極に電気的に接続された導電部材（７０）と、
　前記第１主電極と前記導電部材との間に介在し、前記第１主電極と前記導電部材とを接合する焼結部材（１０１）と、を備え、
　前記保護膜の上面のうち、少なくとも前記開口部の周囲部分は、前記板厚方向において前記第１主電極の接合面に対して面一以下の位置である、半導体装置。 <Technical philosophy 1>
a semiconductor substrate (41); a first main electrode (42) provided on one surface of the semiconductor substrate; a second main electrode (43) provided on a back surface opposite to the one surface in the thickness direction; a semiconductor element (40) having a protective film (45) provided on one surface and having an opening (451) through which the first main electrode is exposed so as to be bondable;
a conductive member (70) electrically connected to the first main electrode;
A sintered member (101) interposed between the first main electrode and the conductive member and joining the first main electrode and the conductive member,
In the semiconductor device, at least a portion of the upper surface of the protective film surrounding the opening is flush with or less than a bonding surface of the first main electrode in the plate thickness direction.
　＜技術的思想２＞
　前記保護膜の上面のうち、少なくとも前記開口部の周囲部分は、前記板厚方向において前記第１主電極の接合面よりも前記一面に近い、技術的思想１に記載の半導体装置。 <Technical philosophy 2>
The semiconductor device according to technical idea 1, wherein at least a portion of the upper surface of the protective film surrounding the opening is closer to the one surface than a bonding surface of the first main electrode in the thickness direction.
　＜技術的思想３＞
　前記半導体素子は、前記一面上であって、前記板厚方向の平面視において前記第１主電極と重ならない位置に配置され、前記保護膜により覆われた配線部（４６、４６Ａ）を有する、技術的思想１または技術的思想２に記載の半導体装置。 <Technical philosophy 3>
The semiconductor element has a wiring portion (46, 46A) that is disposed on the one surface at a position that does not overlap with the first main electrode in a plan view in the thickness direction, and is covered with the protective film. The semiconductor device according to Technical Idea 1 or Technical Idea 2.
　＜技術的思想４＞
　前記保護膜は、前記第１主電極の露出部（４２１）を複数に区画する区画部（４５４）を有し、
　前記焼結部材は、複数の前記露出部を跨いで配置され、
　前記配線部は、前記板厚方向の平面視において前記区画部と重なる位置に配置された区画配線部（４６２）を含み、
　前記区画配線部の幅は、前記露出部の幅よりも狭い、技術的思想３に記載の半導体装置。 <Technical philosophy 4>
The protective film has a division part (454) that divides the exposed part (421) of the first main electrode into a plurality of parts,
The sintered member is arranged across the plurality of exposed parts,
The wiring portion includes a partitioned wiring portion (462) arranged at a position overlapping with the partitioned portion in a plan view in the thickness direction,
The semiconductor device according to technical idea 3, wherein the width of the divided wiring portion is narrower than the width of the exposed portion.
　＜技術的思想５＞
　前記半導体基板は、素子の形成領域であるアクティブ領域（４１１）と、板厚方向の平面視において前記アクティブ領域を取り囲む外周領域（４１２）と、前記外周領域に設けられた耐圧構造部（４１３）と、を有し、
　前記保護膜は、前記耐圧構造部を覆っている、技術的思想１～４いずれかひとつに記載の半導体装置。 <Technical philosophy 5>
The semiconductor substrate includes an active region (411) that is an element formation region, an outer peripheral region (412) surrounding the active region in plan view in the thickness direction, and a voltage-resistant structure (413) provided in the outer peripheral region. and,
The semiconductor device according to any one of technical ideas 1 to 4, wherein the protective film covers the voltage-resistant structure.

Claims (5)

  1. 　半導体基板（４１）と、前記半導体基板の一面に設けられた第１主電極（４２）と、板厚方向において前記一面とは反対の裏面に設けられた第２主電極（４３）と、前記一面に設けられ、前記第１主電極を接合可能に露出させる開口部（４５１）を備えた保護膜（４５）と、を有する半導体素子（４０）と、
    　前記第１主電極に電気的に接続された導電部材（７０）と、
    　前記第１主電極と前記導電部材との間に介在し、前記第１主電極と前記導電部材とを接合する焼結部材（１０１）と、を備え、
    　前記保護膜の上面のうち、少なくとも前記開口部の周囲部分は、前記板厚方向において前記第１主電極の接合面に対して面一以下の位置である、半導体装置。     a semiconductor substrate (41); a first main electrode (42) provided on one surface of the semiconductor substrate; a second main electrode (43) provided on a back surface opposite to the one surface in the thickness direction; a semiconductor element (40) having a protective film (45) provided on one surface and having an opening (451) through which the first main electrode is exposed so as to be bondable;
    a conductive member (70) electrically connected to the first main electrode;
    A sintered member (101) interposed between the first main electrode and the conductive member and joining the first main electrode and the conductive member,
    In the semiconductor device, at least a portion of the upper surface of the protective film surrounding the opening is flush with or less than a bonding surface of the first main electrode in the thickness direction.
  2. 　前記保護膜の上面のうち、少なくとも前記開口部の周囲部分は、前記板厚方向において前記第１主電極の接合面よりも前記一面に近い、請求項１に記載の半導体装置。 2. The semiconductor device according to claim 1, wherein at least a portion of the upper surface of the protective film surrounding the opening is closer to the one surface than a bonding surface of the first main electrode in the thickness direction.
  3. 　前記半導体素子は、前記一面上であって、前記板厚方向の平面視において前記第１主電極と重ならない位置に配置され、前記保護膜により覆われた配線部（４６、４６Ａ）を有する、請求項１または請求項２に記載の半導体装置。 The semiconductor element has a wiring portion (46, 46A) that is disposed on the one surface at a position that does not overlap with the first main electrode in a plan view in the thickness direction, and is covered with the protective film. The semiconductor device according to claim 1 or 2.
  4. 　前記保護膜は、前記第１主電極の露出部（４２１）を複数に区画する区画部（４５４）を有し、
    　前記焼結部材は、複数の前記露出部を跨いで配置され、
    　前記配線部は、前記板厚方向の平面視において前記区画部と重なる位置に配置された区画配線部（４６２）を含み、
    　前記区画配線部の幅は、前記露出部の幅よりも狭い、請求項３に記載の半導体装置。     The protective film has a division part (454) that divides the exposed part (421) of the first main electrode into a plurality of parts,
    The sintered member is arranged across the plurality of exposed parts,
    The wiring portion includes a partitioned wiring portion (462) arranged at a position overlapping with the partitioned portion in a plan view in the thickness direction,
    4. The semiconductor device according to claim 3, wherein the width of the divided wiring portion is narrower than the width of the exposed portion.
  5. 　前記半導体基板は、素子の形成領域であるアクティブ領域（４１１）と、前記板厚方向の平面視において前記アクティブ領域を取り囲む外周領域（４１２）と、前記外周領域に設けられた耐圧構造部（４１３）と、を有し、
    　前記保護膜は、前記耐圧構造部を覆っている、請求項１または請求項２に記載の半導体装置。     The semiconductor substrate includes an active region (411) that is an element formation region, an outer peripheral region (412) surrounding the active region in a plan view in the thickness direction, and a voltage-resistant structure (413) provided in the outer peripheral region. ) and,
    3. The semiconductor device according to claim 1, wherein the protective film covers the voltage-resistant structure.
PCT/JP2023/030949 2022-09-21 2023-08-28 Semiconductor device WO2024062845A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2022150584A JP2024044822A (en) 2022-09-21 2022-09-21 Semiconductor Device
JP2022-150584 2022-09-21

Publications (1)

Publication Number Publication Date
WO2024062845A1 true WO2024062845A1 (en) 2024-03-28

Family

ID=90454111

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2023/030949 WO2024062845A1 (en) 2022-09-21 2023-08-28 Semiconductor device

Country Status (2)

Country Link
JP (1) JP2024044822A (en)
WO (1) WO2024062845A1 (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004111885A (en) * 2002-07-23 2004-04-08 Toshiba Corp Semiconductor device
WO2016189643A1 (en) * 2015-05-26 2016-12-01 三菱電機株式会社 Method for manufacturing semiconductor device
JP2018117054A (en) * 2017-01-19 2018-07-26 株式会社 日立パワーデバイス Semiconductor device and power conversion device
WO2019103028A1 (en) * 2017-11-22 2019-05-31 三菱電機株式会社 Semiconductor device and method for manufacturing semiconductor device
JP2020035812A (en) * 2018-08-28 2020-03-05 株式会社 日立パワーデバイス Semiconductor device and power converter
JP2021009869A (en) * 2019-06-28 2021-01-28 日立オートモティブシステムズ株式会社 Semiconductor device and manufacturing method therefor

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004111885A (en) * 2002-07-23 2004-04-08 Toshiba Corp Semiconductor device
WO2016189643A1 (en) * 2015-05-26 2016-12-01 三菱電機株式会社 Method for manufacturing semiconductor device
JP2018117054A (en) * 2017-01-19 2018-07-26 株式会社 日立パワーデバイス Semiconductor device and power conversion device
WO2019103028A1 (en) * 2017-11-22 2019-05-31 三菱電機株式会社 Semiconductor device and method for manufacturing semiconductor device
JP2020035812A (en) * 2018-08-28 2020-03-05 株式会社 日立パワーデバイス Semiconductor device and power converter
JP2021009869A (en) * 2019-06-28 2021-01-28 日立オートモティブシステムズ株式会社 Semiconductor device and manufacturing method therefor

Also Published As

Publication number Publication date
JP2024044822A (en) 2024-04-02

Similar Documents

Publication Publication Date Title
WO2012051704A1 (en) A power module for converting dc to ac
JP3673776B2 (en) Semiconductor module and power conversion device
WO2024062845A1 (en) Semiconductor device
JP2022152703A (en) Semiconductor device
US20230016437A1 (en) Semiconductor device
WO2023002795A1 (en) Semiconductor device
WO2024004683A1 (en) Semiconductor device
WO2024048371A1 (en) Semiconductor device
JP2024000845A (en) Semiconductor device
JP7363682B2 (en) semiconductor equipment
WO2022049997A1 (en) Element package and semiconductor device
US11804423B2 (en) Semiconductor device
US20240079383A1 (en) Semiconductor device
JP2023170769A (en) Semiconductor device
WO2023047881A1 (en) Semiconductor device and method for manufacturing same
JP7392557B2 (en) semiconductor equipment
WO2023166952A1 (en) Semiconductor device
US20240145349A1 (en) Semiconductor device
JP2023168060A (en) Semiconductor device and manufacturing method thereof
US20240213123A1 (en) Semiconductor device
US20240038868A1 (en) Semiconductor device
JP7363586B2 (en) semiconductor equipment
JP2023183160A (en) Semiconductor device and manufacturing method thereof
JP2024006354A (en) Semiconductor device
JP2023078915A (en) Semiconductor device and manufacturing method thereof

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23867969

Country of ref document: EP

Kind code of ref document: A1