WO2024062845A1 - Dispositif à semi-conducteur - Google Patents

Dispositif à semi-conducteur Download PDF

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Publication number
WO2024062845A1
WO2024062845A1 PCT/JP2023/030949 JP2023030949W WO2024062845A1 WO 2024062845 A1 WO2024062845 A1 WO 2024062845A1 JP 2023030949 W JP2023030949 W JP 2023030949W WO 2024062845 A1 WO2024062845 A1 WO 2024062845A1
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WO
WIPO (PCT)
Prior art keywords
protective film
electrode
wiring
semiconductor device
main electrode
Prior art date
Application number
PCT/JP2023/030949
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English (en)
Japanese (ja)
Inventor
瑛美夏 安部
卓矢 門口
知巳 奥村
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株式会社デンソー
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Publication of WO2024062845A1 publication Critical patent/WO2024062845A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N

Definitions

  • the disclosure in this specification relates to a semiconductor device.
  • Patent Document 1 discloses a semiconductor device that includes a semiconductor chip having main electrodes on both sides, a conductive member, and a sintered layer that bonds the main electrodes and the conductive member.
  • the contents of the prior art document are incorporated by reference as explanations of the technical elements in this specification.
  • One of the main electrodes is exposed through an opening in the polyimide protective film so that it can be bonded.
  • a protective film surrounds the exposed portion of the main electrode.
  • the upper surface of the protective film is located above the bonding surface of the main electrode.
  • the sintered layer is provided so as to almost coincide with the exposed portion of the main electrode in a plan view. Therefore, if the sintered layer is misaligned with respect to the main electrode, stress will be concentrated on the protective film side due to the pressure applied during sinter bonding, which may damage the protective film or cause cracks in the wiring portion covered by the protective film. To address this issue, it is possible to reduce the area of the sintered layer, taking into account the tolerance for misalignment. However, this would increase thermal resistance and current density.
  • the present disclosure has been made in view of such problems, and aims to provide a semiconductor device that can improve reliability.
  • the semiconductor device which is one of the disclosures, is A semiconductor substrate, a first main electrode provided on one surface of the semiconductor substrate, a second main electrode provided on the back surface opposite to the one surface in the board thickness direction, and the first main electrode provided on one surface can be bonded.
  • a semiconductor element having a protective film having an opening exposed to the semiconductor element; a conductive member electrically connected to the first main electrode; a sintered member interposed between the first main electrode and the conductive member and joining the first main electrode and the conductive member; At least a portion of the upper surface of the protective film surrounding the opening is located flush with or less than the bonding surface of the first main electrode in the plate thickness direction.
  • the disclosed semiconductor device at least the portion of the upper surface of the protective film surrounding the opening does not protrude above the bonding surface of the first main electrode in the thickness direction. Therefore, even if the position of the sintered member is shifted from the exposed part of the first main electrode, stress concentration on the protective film side due to the pressure applied during sintering and joining can be suppressed. Can be done. Further, stress concentration on the protective film side can be suppressed without reducing the size of the sintered member. As a result, a semiconductor device with improved reliability can be provided.
  • FIG. 1 is a diagram showing a schematic configuration of a vehicle drive system to which a semiconductor device according to a first embodiment is applied.
  • FIG. 1 is a plan view showing a semiconductor device according to a first embodiment.
  • 3 is a sectional view taken along line III-III in FIG. 2.
  • FIG. 3 is a cross-sectional view taken along line IV-IV in FIG. 2 .
  • FIG. 2 is a plan view showing a semiconductor element.
  • 6 is a cross-sectional view taken along the line VI-VI in FIG. 5.
  • FIG. 1 is a cross-sectional view showing a junction structure of a semiconductor element.
  • FIG. 3 is a cross-sectional view showing a joining method. It is a sectional view showing a reference example. It is a sectional view showing a reference example.
  • FIG. 3 is a cross-sectional view showing an example of positional displacement in the present embodiment.
  • FIG. 7 is a cross-sectional view showing a semiconductor element in a semiconductor device according to a second embodiment.
  • FIG. 7 is a plan view showing a semiconductor element in a semiconductor device according to a third embodiment.
  • 14 is a cross-sectional view showing the junction structure of the semiconductor element corresponding to the line XIV-XIV in FIG. 13.
  • FIG. It is a top view which shows a modification. It is a sectional view showing other modifications. It is a sectional view showing other modifications.
  • the semiconductor device of this embodiment is applied, for example, to a power conversion device for a moving object that uses a rotating electric machine as a drive source.
  • mobile objects include electric vehicles such as electric vehicles (BEV), hybrid vehicles (HEV), and plug-in hybrid vehicles (PHEV), flying vehicles such as electric vertical takeoff and landing aircraft and drones, ships, construction machinery, and agricultural machinery.
  • BEV electric vehicles
  • HEV hybrid vehicles
  • PHEV plug-in hybrid vehicles
  • flying vehicles such as electric vertical takeoff and landing aircraft and drones, ships, construction machinery, and agricultural machinery.
  • a vehicle drive system 1 includes a DC power source 2, a motor generator 3, and a power converter 4.
  • the DC power supply 2 is a DC voltage source composed of a rechargeable and dischargeable secondary battery.
  • the secondary battery is, for example, a lithium ion battery or a nickel metal hydride battery.
  • the motor generator 3 is a three-phase AC rotating electric machine.
  • the motor generator 3 functions as a driving source for the vehicle, that is, an electric motor.
  • the motor generator 3 functions as a generator during regeneration.
  • Power conversion device 4 performs power conversion between DC power supply 2 and motor generator 3 .
  • the power conversion device 4 includes a power conversion circuit. As shown in FIG. 1, the power conversion device 4 includes a smoothing capacitor 5 and an inverter 6 that is a power conversion circuit.
  • the smoothing capacitor 5 mainly smoothes the DC voltage supplied from the DC power supply 2.
  • the smoothing capacitor 5 is connected to a P line 7 which is a power line on the high potential side and an N line 8 which is a power line on the low potential side.
  • the P line 7 is connected to the positive pole of the DC power supply 2
  • the N line 8 is connected to the negative pole of the DC power supply 2.
  • a positive terminal of the smoothing capacitor 5 is connected to a P line 7 between the DC power supply 2 and the inverter 6.
  • the negative electrode is connected to the N line 8 between the DC power supply 2 and the inverter 6.
  • Smoothing capacitor 5 is connected in parallel to DC power supply 2 .
  • the inverter 6 is a DC-AC conversion circuit. In accordance with switching control by a control circuit (not shown), the inverter 6 converts DC voltage into three-phase AC voltage and outputs it to the motor generator 3. This drives the motor generator 3 to generate a predetermined torque. During regenerative braking of the vehicle, the inverter 6 converts the three-phase AC voltage generated by the motor generator 3 in response to rotational force from the wheels into DC voltage in accordance with switching control by the control circuit, and outputs it to the P line 7. In this way, the inverter 6 performs bidirectional power conversion between the DC power source 2 and the motor generator 3.
  • the inverter 6 is configured with three-phase upper and lower arm circuits 9.
  • the upper and lower arm circuits 9 are sometimes referred to as legs.
  • the upper and lower arm circuits 9 each have an upper arm 9H and a lower arm 9L.
  • the upper arm 9H and the lower arm 9L are connected in series between the P line 7 and the N line 8, with the upper arm 9H on the P line 7 side.
  • a connection point between upper arm 9H and lower arm 9L is connected to a corresponding phase winding 3a of motor generator 3 via output line 10.
  • Inverter 6 has six arms. At least a portion of each of the P line 7, the N line 8, and the output line 10 is constituted by a conductive member such as a bus bar.
  • each arm includes an IGBT 11 that is a switching element and a diode 12 for freewheeling.
  • IGBT is an abbreviation for Insulated Gate Bipolar Transistor.
  • an n-channel type IGBT 11 is used.
  • the diode 12 is connected in antiparallel to the corresponding IGBT 11.
  • the collector of the IGBT 11 is connected to the P line 7.
  • the emitter of the IGBT 11 is connected to the N line 8.
  • the emitter of the IGBT 11 in the upper arm 9H and the collector of the IGBT 11 in the lower arm 9L are connected to each other.
  • the anode of the diode 12 is connected to the emitter of the corresponding IGBT 11, and the cathode is connected to the collector.
  • the power conversion device 4 may further include a converter as a power conversion circuit.
  • a converter is a DC-DC conversion circuit that converts DC voltage to DC voltages of different values.
  • a converter is provided between DC power supply 2 and smoothing capacitor 5.
  • the converter includes, for example, a reactor and the above-mentioned upper and lower arm circuits 9. According to this configuration, it is possible to raise and lower the voltage.
  • the power conversion device 4 may include a filter capacitor that removes power supply noise from the DC power supply 2.
  • a filter capacitor is provided between the DC power supply 2 and the converter.
  • the power conversion device 4 may include a drive circuit for switching elements that constitute the inverter 6 and the like.
  • the drive circuit supplies a drive voltage to the gate of the IGBT 11 of the corresponding arm based on a drive command from the control circuit.
  • the drive circuit drives the corresponding IGBT 11 by applying a drive voltage, that is, turns it on and turns it off.
  • a drive circuit is sometimes referred to as a driver.
  • the power conversion device 4 may include a control circuit for switching elements.
  • the control circuit generates a drive command for operating the IGBT 11 and outputs it to the drive circuit.
  • the control circuit generates a drive command based on a torque request input from a host ECU (not shown) and signals detected by various sensors.
  • Various sensors include, for example, a current sensor, a rotation angle sensor, and a voltage sensor.
  • the current sensor detects the phase current flowing through the winding 3a of each phase.
  • the rotation angle sensor detects the rotation angle of the rotor of the motor generator 3.
  • the voltage sensor detects the voltage across the smoothing capacitor 5.
  • the control circuit outputs, for example, a PWM signal as a drive command.
  • the control circuit includes, for example, a processor and a memory.
  • ECU is an abbreviation for Electronic Control Unit.
  • PWM is an abbreviation for Pulse Width Modulation.
  • FIG. 2 is a plan view showing the semiconductor device.
  • FIG. 2 is a top plan view of the semiconductor device.
  • FIG. 3 is a sectional view taken along line III-III in FIG. 2.
  • FIG. 4 is a sectional view taken along line IV-IV in FIG. 2.
  • FIG. 5 is a plan view showing the semiconductor element.
  • the thickness direction of the semiconductor element is referred to as the Z direction.
  • One direction perpendicular to the Z direction is defined as the X direction.
  • the direction perpendicular to both the Z direction and the X direction is defined as the Y direction.
  • the planar shape is the shape viewed from the Z direction, in other words, the shape along the XY plane defined by the X direction and the Y direction. Further, a planar view from the Z direction may be simply referred to as a planar view.
  • the semiconductor device 20 includes a sealing body 30, a semiconductor element 40, wiring members 50 and 60, a conductive spacer 70, and an external connection terminal 80.
  • the semiconductor device 20 further includes a bonding wire 90 and a bonding material 100.
  • the semiconductor device 20 constitutes one of the arms described above. That is, the two semiconductor devices 20 constitute the upper and lower arm circuit 9 for one phase.
  • the sealing body 30 seals some of the other elements constituting the semiconductor device 20. The remaining parts of the other elements are exposed outside the sealing body 30.
  • the sealing body 30 is made of resin, for example.
  • An example of the resin is an epoxy resin.
  • the sealing body 30 is molded from resin by, for example, a transfer molding method. Such a sealing body 30 is sometimes referred to as a sealing resin body, a mold resin, a resin molded body, or the like.
  • the sealing body 30 may be formed using gel, for example. The gel is filled (arranged) in opposing regions of the pair of wiring members 50 and 60, for example.
  • the sealing body 30 has a substantially rectangular shape in plan view.
  • the sealing body 30 has one surface 30a and a back surface 30b, which is a surface opposite to the one surface 30a in the Z direction, as a surface forming an outline.
  • One surface 30a and back surface 30b are, for example, substantially flat surfaces.
  • It also has side surfaces 30c, 30d, 30e, and 30f that are continuous with the one surface 30a and the back surface 30b.
  • the side surface 30c is a surface from which the main terminals 81 and 82 of the external connection terminal 80 protrude.
  • the side surface 30d is a surface opposite to the side surface 30c in the Y direction.
  • the side surface 30d is a surface from which the signal terminal 83 projects.
  • the side surfaces 30e and 30f are surfaces from which the external connection terminal 80 does not protrude.
  • the side surface 30e is a surface opposite to the side surface 30f in the X direction.
  • the semiconductor element 40 includes a semiconductor substrate 41, an emitter electrode 42, a collector electrode 43, and a pad 44.
  • the semiconductor element 40 is sometimes referred to as a semiconductor chip.
  • the semiconductor substrate 41 is made of a material such as silicon (Si) or a wide bandgap semiconductor having a wider bandgap than silicon, and has a vertical element formed thereon. Examples of wide bandgap semiconductors include silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga 2 O 3 ), and diamond.
  • the vertical element is configured to allow a main current to flow in the thickness direction of the semiconductor substrate 41 (semiconductor element 40), that is, in the Z direction.
  • the vertical elements of this embodiment are the IGBT 11 and the diode 12 that constitute one arm.
  • the vertical element is an IGBT in which diodes 12 are connected in antiparallel, that is, an RC-IGBT. RC is an abbreviation for Reverse Conducting.
  • the vertical element is a heating element that generates heat when energized.
  • a gate electrode (not shown) is formed on the semiconductor substrate 41.
  • the gate electrode has, for example, a trench structure.
  • the semiconductor substrate 41 has one side 41a and a back side 41b as plate surfaces on which the main electrode is provided.
  • One surface 41a is a surface of the semiconductor substrate 41 on the one surface 30a side of the sealed body 30.
  • the back surface 41b is a surface opposite to the one surface 41a in the thickness direction.
  • the emitter electrode 42 which is one of the main electrodes, is arranged on one surface 41a of the semiconductor substrate 41.
  • a collector electrode 43 which is another one of the main electrodes, is arranged on the back surface 41b of the semiconductor substrate 41.
  • the emitter electrode 42 corresponds to a first main electrode
  • the collector electrode 43 corresponds to a second main electrode.
  • a current flows between the main electrodes, that is, between the emitter electrode 42 and the collector electrode 43.
  • the emitter electrode 42 also serves as an anode electrode of the diode 12.
  • the collector electrode 43 also serves as the cathode electrode of the diode 12.
  • the collector electrode 43 is formed over almost the entire back surface 41b of the semiconductor substrate 41.
  • the emitter electrode 42 is formed on a portion of one surface 41a of the semiconductor substrate 41.
  • the pad 44 is a signal electrode.
  • the pad 44 is formed on one surface 41a of the semiconductor substrate 41 in a region different from the region where the emitter electrode 42 is formed.
  • the pad 44 is formed at the end opposite to the region where the emitter electrode 42 is formed in the Y direction.
  • the pad 44 is provided in parallel with the emitter electrode 42 in the Y direction.
  • Pad 44 includes at least gate pad 44G.
  • the semiconductor element 40 has five pads 44.
  • the gate pad 44G has a gate pad 44G for detecting the emitter potential, for detecting the cathode potential of a temperature-sensitive diode (not shown) included in the semiconductor element 40, for detecting the anode potential, and for current sensing.
  • the five pads 44 are lined up along the X direction. Details of the semiconductor element 40 will be described later.
  • the wiring member 50 is electrically connected to the emitter electrode 42 and provides a wiring function.
  • the wiring member 60 is electrically connected to the collector electrode 43 and provides a wiring function.
  • the wiring members 50 and 60 are arranged to sandwich the semiconductor element 40 in the Z direction.
  • the wiring members 50 and 60 are arranged so that at least a portion thereof faces each other in the Z direction.
  • the wiring members 50 and 60 include the semiconductor element 40 in a plan view.
  • the wiring members 50 and 60 provide a heat radiation function of radiating heat generated by the semiconductor element 40.
  • the wiring members 50 and 60 are sometimes referred to as heat sinks, heat sinks, or the like.
  • the wiring members 50 and 60 of this embodiment are metal plates made of a metal with good conductivity such as Cu or Cu alloy.
  • the metal plate is provided, for example, as part of a lead frame. Instead of the metal plate, a substrate may be used in which metal bodies are arranged on both sides of an insulating base material.
  • the wiring members 50 and 60 may include a plating film of Ni, Au, or the like on the metal surface.
  • the wiring member 50 has a facing surface 50a that is a surface on the semiconductor element 40 side, and a back surface 50b that is a surface opposite to the facing surface 50a.
  • the wiring member 60 also has a facing surface 60a and a back surface 60b.
  • the wiring members 50 and 60 have, for example, a substantially rectangular planar shape.
  • the back surfaces 50b and 60b of the wiring members 50 and 60 are exposed from the sealing body 30.
  • the back surfaces 50b and 60b are sometimes referred to as heat radiation surfaces, exposed surfaces, and the like.
  • the back surface 50b of the wiring member 50 is substantially flush with the one surface 30a of the sealing body 30.
  • the back surface 60b of the wiring member 60 is substantially flush with the back surface 30b of the sealing body 30.
  • the conductive spacer 70 is interposed between the semiconductor element 40 and the wiring member 50.
  • the conductive spacer 70 provides a spacer function to ensure a predetermined distance between the semiconductor element 40 and the wiring member 50.
  • the conductive spacer 70 ensures a height for electrically connecting the corresponding signal terminal 83 to the pad 44 of the semiconductor element 40 .
  • the conductive spacer 70 is located in the middle of the electrical and thermal conduction path between the emitter electrode 42 of the semiconductor element 40 and the wiring member 50, and provides a wiring function and a heat dissipation function.
  • the conductive spacer 70 corresponds to a conductive member connected to the first main electrode via the sintered member.
  • the conductive spacer 70 includes a metal material with good electrical conductivity and thermal conductivity, such as Cu (copper).
  • the conductive spacer 70 may have a plating film on its surface.
  • the conductive spacer 70 is sometimes referred to as a terminal, a terminal block, a metal block, or the like.
  • the semiconductor device 20 includes the same number of conductive spacers 70 as the semiconductor elements 40. Conductive spacers 70 are individually connected to semiconductor elements 40 .
  • the conductive spacer 70 is, for example, a columnar body.
  • the conductive spacer 70 has a shape corresponding to an opening 451 described later in plan view.
  • the conductive spacer 70 has a size that approximately matches or is slightly smaller than the opening 451.
  • the external connection terminal 80 is a terminal for electrically connecting the semiconductor device 20 to external equipment.
  • the external connection terminal 80 is formed using a metal material with good conductivity, such as copper.
  • the external connection terminal 80 is, for example, a plate material.
  • the external connection terminal 80 is sometimes called a lead.
  • the external connection terminal 80 includes main terminals 81 and 82 and a signal terminal 83.
  • the main terminals 81 and 82 are external connection terminals 80 electrically connected to the main electrodes of the semiconductor element 40.
  • the main terminal 81 is electrically connected to the emitter electrode 42.
  • the main terminal 81 is sometimes referred to as an emitter terminal.
  • the main terminal 81 is connected to the emitter electrode 42 via the wiring member 50.
  • the main terminal 81 is connected to one end of the wiring member 50 in the Y direction.
  • the thickness of the main terminal 81 is thinner than that of the wiring member 50.
  • the main terminal 81 is connected to the wiring member 50 so as to be, for example, approximately flush with the opposing surface 50a.
  • the main terminal 81 may be connected by being provided continuously and integrally with the wiring member 50, or may be provided as a separate member and connected by joining.
  • the main terminal 81 of this embodiment is provided integrally with the wiring member 50 as a part of the lead frame.
  • the main terminal 81 extends from the wiring member 50 in the Y direction and projects outward from the side surface 30c of the sealing body 30.
  • the main terminal 81 has a bent part in the middle of the portion covered by the sealing body 30, and protrudes from near the center in the Z direction on the side surface 30c.
  • the main terminal 82 is electrically connected to the collector electrode 43.
  • Main terminal 82 is sometimes referred to as a collector terminal.
  • the main terminal 82 is connected to the collector electrode 43 via the wiring member 60.
  • the main terminal 82 is connected to one end of the wiring member 60 in the Y direction.
  • the thickness of the main terminal 82 is thinner than that of the wiring member 60.
  • the main terminal 82 is connected to the wiring member 60, for example, so as to be substantially flush with the opposing surface 60a.
  • the main terminal 82 may be continuously and integrally provided with the wiring member 60, or may be provided as a separate member and connected by joining.
  • the main terminal 82 of this embodiment is provided integrally with the wiring member 60 as a part of a lead frame separate from the main terminal 81.
  • the main terminal 82 extends from the wiring member 60 in the Y direction and projects outward from the same side surface 30c as the main terminal 81.
  • the main terminal 82 also has a bent part in the middle of the portion covered by the sealing body 30, and protrudes from near the center in the Z direction on the side surface 30c.
  • the two main terminals 81 and 82 are arranged side by side in the X direction so that their side surfaces face each other.
  • the signal terminal 83 is electrically connected to the corresponding pad 44 of the semiconductor element 40.
  • the signal terminal 83 is electrically connected to the pad 44 via a bonding wire 90.
  • the signal terminal 83 extends in the Y direction and projects outward from the side surface 30d of the sealing body 30.
  • the semiconductor device 20 of this embodiment includes five signal terminals 83 corresponding to the pads 44.
  • the five signal terminals 83 are arranged in line in the X direction.
  • the signal terminal 83 is configured, for example, on a common lead frame with the wiring member 60 and the main terminal 82.
  • the plurality of signal terminals 83 are electrically isolated from each other by cutting tie bars (not shown).
  • the bonding material 100 is interposed between the elements constituting the semiconductor device 20 and bonds the elements together.
  • the semiconductor device 20 includes a plurality of bonding materials 100.
  • One of the bonding materials 100 is interposed between the emitter electrode 42 and the conductive spacer 70 to bond the emitter electrode 42 and the conductive spacer 70 together.
  • the other bonding material 100 is interposed between the conductive spacer 70 and the wiring member 50 and joins the conductive spacer 70 and the wiring member 50 together.
  • the other bonding material 100 is interposed between the collector electrode 43 of the semiconductor element 40 and the wiring member 60 to bond the collector electrode 43 and the wiring member 60 together.
  • the bonding material 100 interposed between the emitter electrode 42 and the conductive spacer 70 is a sintered member 101 as described later.
  • the other bonding material 100 may be a sintered member, or may be a bonding material different from the sintered member, such as solder.
  • the semiconductor element 40 constituting one arm is sealed by the sealing body 30.
  • the sealing body 30 integrally seals the semiconductor element 40, a portion of the wiring member 50, a portion of the wiring member 60, a conductive spacer 70, and a portion of each of the external connection terminals 80.
  • the semiconductor element 40 is arranged between the wiring members 50 and 60 in the Z direction.
  • the semiconductor element 40 is sandwiched between wiring members 50 and 60 that are arranged opposite to each other. Thereby, the heat of the semiconductor element 40 can be radiated to both sides in the Z direction.
  • the semiconductor device 20 has a double-sided heat dissipation structure.
  • the back surface 50b of the wiring member 50 is substantially flush with the one surface 30a of the sealing body 30.
  • the back surface 60b of the wiring member 60 is substantially flush with the back surface 30b of the sealing body 30. Since the back surfaces 50b and 60b are exposed surfaces, heat dissipation can be improved.
  • FIG. 6 is a sectional view taken along line VI-VI in FIG. 5.
  • a gate wiring 46 which will be described later, is shown by a broken line.
  • the semiconductor substrate 41 has a substantially rectangular planar shape. As shown in FIGS. 5 and 6, the semiconductor substrate 41 has an active region 411 and an outer peripheral region 412. The two-dot chain line shown in FIGS. 5 and 6 indicates the boundary between the active region 411 and the outer peripheral region 412.
  • the active region 411 is a region where vertical elements are formed.
  • the active region 411 is sometimes referred to as a main region, a main cell region, a cell region, an element region, an element formation region, or the like.
  • the active region 411 has, for example, a substantially rectangular planar shape.
  • the active region 411 is aligned with the pad 44 in the Y direction.
  • the active region 411 is provided with a plurality of cells (unit structures). A plurality of cells are connected in parallel to form an RC-IGBT.
  • the outer peripheral region 412 surrounds the active region 411 in plan view.
  • a pressure-resistant structure is formed in the outer peripheral region 412.
  • a guard ring 413 is formed.
  • the guard ring 413 has an annular shape in a plan view so as to surround the active region 411 .
  • the semiconductor element 40 has a protective film 45 disposed on one surface 41a of the semiconductor substrate 41.
  • the protective film 45 is an insulating film provided on one surface 41a of the semiconductor substrate 41 so as to cover the peripheral portion of the emitter electrode 42, specifically the base electrode 422 described below.
  • polyimide, silicon nitride film, etc. can be used as the material for the protective film 45.
  • the protective film 45 has an opening 451.
  • the opening 451 defines a joining area between the emitter electrode 42 and the sintered member 101.
  • the opening 451 is a through hole that penetrates the protective film 45 in the Z direction.
  • the opening 451 is provided so as to overlap the emitter electrode 42 in plan view.
  • the opening 451 substantially coincides with the active region 411 in plan view.
  • the planar shape of the opening 451, that is, the inner circumferential surface of the protective film 45 that defines the opening 451 has a substantially rectangular planar shape.
  • the protective film 45 has an opening 452 that defines the bonding area in the pad 44 .
  • the emitter electrode 42 has an exposed portion 421 that is exposed from the opening 451 of the protective film 45 and provides a bonding region.
  • the exposed portion 421 forms a joint with the sintered member 101.
  • the external contour of the exposed portion 421 matches the external contour of the opening 451 in a plan view.
  • the exposed portion 421 is arranged on the active region 411 of the semiconductor substrate 41.
  • the emitter electrode 42 has a multilayer structure.
  • the emitter electrode 42 has a base electrode 422 and a connection electrode 423.
  • the pad 44 also has the same configuration as the emitter electrode 42.
  • the base electrode 422 is a metal layer placed on the semiconductor substrate 41 side in the multilayered emitter electrode 42.
  • the base electrode 422 is formed using, for example, a material whose main component is Al (aluminum).
  • the base electrode 422 of this embodiment is formed using an Al alloy such as AlSi or AlSiCu.
  • the base electrode 422 is sometimes referred to as a wiring electrode, a base layer, a first metal layer, or the like.
  • the base electrode 422 in plan view, includes the active region 411 and extends onto the outer peripheral region 412.
  • the base electrode 422 is connected to the emitter and anode of the vertical element.
  • the base electrode 422 has a peripheral portion that surrounds the exposed portion 421 in plan view.
  • the peripheral portion is a portion of the base electrode 422 that overlaps with the protective film 45.
  • the protective film 45 is disposed on one surface 41a of the semiconductor substrate 41 so as to cover the peripheral portion of the base electrode 422.
  • connection electrode 423 is stacked on the base electrode 422.
  • the connection electrode 423 is also referred to as a top electrode, an upper electrode, an upper layer electrode, a top layer, or a second metal layer.
  • the connection electrode 423 contains at least a noble metal such as Au (gold), Ag (silver), Pt (platinum), or Pd (palladium) for bonding with the sintered member 101.
  • the connection electrode 423 may contain a base metal as well as a noble metal.
  • connection electrode 423 of this embodiment contains Ni (nickel). Ni is harder than the Al alloy that constitutes the base electrode 422.
  • Connection electrode 423 includes Ni and a noble metal, such as Au or Ag.
  • the connection electrode 423 is formed in multiple layers by, for example, a plating method. At least a portion of the noble metal of the connection electrode 423 diffuses into the sintered member 101 during bonding.
  • connection electrode 423 is stacked on the base electrode 422 in the opening 451 of the protective film 45 .
  • the outer peripheral end of the connection electrode 423 is in contact with the inner peripheral surface of the protective film 45 that defines the opening 451.
  • the bonding surface of the exposed portion 421 of the emitter electrode 42 is flush with at least the surrounding portion of the opening 451 of the upper surface 45a of the protective film 45.
  • the peripheral portion of the opening 451 is a predetermined range from the opening end.
  • the peripheral portion is a portion within a tolerance range in which the sintered member 101 may be misaligned with respect to the bonding surface of the exposed portion 421.
  • substantially the entire upper surface 45a of the protective film 45 is substantially flush with the bonding surface of the exposed portion 421.
  • flush refers to a state in which the positions in the Z direction are the same.
  • the protective film 45 is arranged on the guard ring 413 in plan view.
  • the protective film 45 is arranged on one surface 41a so as to cover the guard ring 413.
  • the protective film 45 covers a wiring portion located at a position that does not overlap the emitter electrode 42 and the pad 44 in plan view.
  • the semiconductor element 40 includes a gate wiring 46 as a wiring part.
  • the gate wiring 46 electrically connects the gate electrode of the IGBT 11 formed on the semiconductor substrate 41 and the gate pad 44G.
  • the gate wiring 46 is a metal wiring formed using a material whose main component is Al (aluminum), for example.
  • the gate wiring 46 is electrically connected to the gate electrode via a polysilicon wiring (not shown) formed by introducing impurities into polysilicon.
  • the polysilicon wiring is arranged between the emitter electrode 42 and the semiconductor substrate 41.
  • the entire length of the gate wiring 46 in this embodiment is arranged on the outer peripheral region 412.
  • the gate wiring 46 is provided in a ring shape so as to surround the active region 411 . At least a portion of the gate wiring 46 is arranged around the opening 451 described above.
  • FIG. 7 corresponds to FIG. 6.
  • FIG. 7 shows an ideal bonding structure between the semiconductor element 40 and the conductive spacer 70.
  • the sintered member 101 is interposed between the emitter electrode 42 of the semiconductor element 40 and the conductive spacer 70.
  • the sintered member 101 joins the emitter electrode 42 and the conductive spacer 70.
  • the sintered member 101 is made of Ag or Cu.
  • the sintered member 101 is a sintered body made of Ag particles or Cu particles.
  • the sintered member 101 can be joined at a lower temperature than solder.
  • the sintered member 101 is arranged so as to substantially match the bonding surface of the exposed portion 421 of the emitter electrode 42 in plan view.
  • the sintered member 101 is arranged so that its outer peripheral end substantially coincides with the inner peripheral surface of the protective film 45 that defines the opening 451.
  • the protective film 45 ideally includes the sintered member 101 in plan view.
  • the conductive spacer 70 has a metal film (not shown) on the joint surface with the sintered member 101.
  • the metal film contains at least a precious metal, like the connection electrode 423.
  • the metal film is a plating film containing Ni and a precious metal, such as Au or Ag.
  • the conductive spacer 70 has, for example, a substantially rectangular shape in plan view.
  • the outer periphery of the conductive spacer 70 is positioned outside or substantially coincident with the outer periphery of the sintered member 101 in plan view.
  • FIG. 8 is a cross-sectional view showing the joining method.
  • FIG. 8 corresponds to FIG. 7.
  • a sintered sheet 101S is used in order to form the sintered member 101.
  • the sintered sheet 101S is sometimes referred to as a sintered film.
  • the sintered sheet 101S contains Ag or Cu.
  • the sintered sheet 101S is placed on the exposed portion 421 of the emitter electrode 42 of the semiconductor element 40.
  • the sintered sheet 101S has a predetermined size smaller than the opening 451 of the protective film 45 in plan view before being pressurized.
  • conductive spacers 70 are placed on the sintered sheet 101S to form a laminate. Then, while heating, the laminate is pressurized from the conductive spacer 70 side using a pressurizing device (not shown). As a result, the sintered sheet 101S is expanded between the facing surfaces of the exposed portion 421 of the emitter electrode 42 and the conductive spacer 70, becomes thinner, and is sintered to become the sintered member 101.
  • the size of the sintered sheet 101S of the sintered member 101 is determined so that the above-described predetermined positional relationship is achieved in the joined state.
  • Sintered members are formed by heating below the melting point. Sintered members do not become molten like solder during bonding. Sintered members have lower wettability with respect to main electrodes and conductive members than solder. The sintered member does not wet and spread on the surface of the main electrode or the surface of the conductive member during bonding, unlike solder. A sintered member may be placed on the protective film.
  • 9 and 10 show reference examples. 9 and 10 both show the joining method. 9 and 10 correspond to FIG. 8.
  • the reference numeral of each element is such that r is added to the end of the reference numeral of the related element of the semiconductor device 20.
  • the upper surface 45ar of the protective film 45r is located above the bonding surface of the exposed portion 421r of the emitter electrode 42r in the Z direction. As a result, a step is formed between the upper surface 45a and the bonding surface of the exposed portion 421r, with the protective film 45r side being convex.
  • the size of the sintered sheet 101Sr is determined so that at least a portion of the sintered member in the circumferential direction contacts the inner circumferential surface of the protective film in the bonded state.
  • the sintered sheet 101Sr is misaligned within the manufacturing tolerance and placed so as to rest on the upper surface 45ar of the protective film 45r, stress will be concentrated on the protective film 45r due to the pressure applied during sinter bonding. This may result in damage to the protective film 45r, wiring parts such as the gate wiring 46r covered by the protective film 45r, and even the substrate part directly below the protective film 45r. Note that a similar problem may occur if a configuration is used in which a portion of the sintered sheet 101Sr is placed on the upper surface 45ar of the protective film 45r due to misalignment.
  • the size of the sintered sheet 101Sr is determined so that even if the sintered sheet 101Sr is misaligned within manufacturing tolerances, it will not be placed on the upper surface 45ar of the protective film 45r. In other words, the size of the sintered sheet 101Sr is small. For this reason, after sintering and joining, the cross-sectional area of the sintered member (not shown) becomes smaller, resulting in increased thermal resistance and current density.
  • the upper surface 45a of the protective film 45 is flush with the bonding surface of the exposed portion 421 of the emitter electrode 42 in the Z direction. In other words, the position of the upper surface 45a in the Z direction is approximately equal to the position of the bonding surface of the exposed portion 421.
  • the semiconductor element 40 of this embodiment has a gate wiring 46 as a wiring portion that is arranged at a position that does not overlap the emitter electrode 42 in a plan view and is covered by a protective film 45.
  • the semiconductor element 40 also has a guard ring 413 as a pressure-resistant structure portion formed in the peripheral region 412.
  • a guard ring 413 as a pressure-resistant structure portion formed in the peripheral region 412.
  • the upper surface 45a of the protective film 45 is flush with the bonding surface of the exposed portion 421 of the emitter electrode 42, at least in the peripheral portion of the opening 451.
  • the peripheral portion of the upper surface 45a of the protective film 45 around the opening 451 may be flush with the bonding surface of the exposed portion 421, and the other portion may be located above the bonding surface of the exposed portion 421.
  • This embodiment is a modification based on the previous embodiment, and the description of the previous embodiment can be used.
  • the upper surface 45a of the protective film 45 was positioned flush with the upper surface of the emitter electrode 42.
  • the upper surface 45a of the protective film 45 may be positioned not flush with the upper surface of the emitter electrode 42.
  • FIG. 12 is a cross-sectional view showing the semiconductor element 40 in the semiconductor device 20 according to this embodiment.
  • FIG. 12 corresponds to FIG. 6.
  • the portion of the upper surface 45a of the protective film 45 surrounding the opening 451 is located closer to the surface 41a than the bonding surface of the exposed portion 421 of the emitter electrode 42 in the Z direction.
  • the other portions of the upper surface 45a are also located closer to the surface 41a than the bonding surface of the exposed portion 421 of the emitter electrode 42.
  • the entire upper surface 45a of the protective film 45 is closer to the surface 41a than the bonding surface of the exposed portion 421 of the emitter electrode 42.
  • the height of the protective film 45 to the top surface with respect to the one surface 41 a is lower than that of the emitter electrode 42 .
  • the upper surface 45a of the protective film 45 is located below the upper surface of the emitter electrode 42.
  • the upper surface 45a of the protective film 45 is located closer to the one surface 41a of the semiconductor substrate 41 than the bonding surface of the exposed portion 421 of the emitter electrode 42 in the Z direction. Due to this positional relationship, even if the sintered sheet 101S is displaced, it does not come into contact with the periphery of the opening of the upper surface 45a, or even if it does, the stress acting on the protective film 45 becomes smaller. Therefore, the reliability of the semiconductor device 20 can be further improved.
  • At least a portion of the upper surface 45a of the protective film 45 surrounding the opening 451 may be located below the bonding surface of the exposed portion 421 of the emitter electrode 42.
  • a portion of the upper surface 45a of the protective film 45 around the opening 451 may be placed below the bonding surface of the exposed portion 421, and the other portion may be placed above the bonding surface of the exposed portion 421.
  • a portion of the upper surface 45a of the protective film 45 around the opening 451 is located below the bonding surface of the exposed portion 421, and the other portion is flush with or less than the bonding surface of the exposed portion 421.
  • the above-described positional relationship may be satisfied while the surface has irregularities.
  • FIG. 13 is a plan view showing the semiconductor element 40 in the semiconductor device 20 according to this embodiment.
  • FIG. 13 corresponds to FIG. 5.
  • FIG. 14 is a sectional view taken along the line XIV-XIV in FIG. 13.
  • FIG. 14 shows a bonding structure between the semiconductor element 40 and the conductive spacer 70.
  • FIG. 14 corresponds to FIG. 7.
  • the protective film 45 has an outer peripheral portion 453 and a partition portion 454.
  • the outer peripheral portion 453 is arranged to substantially coincide with the outer peripheral region 412 in a plan view.
  • the division section 454 divides the emitter electrode 42 into a plurality of sections.
  • the partition section 454 of this embodiment is provided so as to substantially divide the emitter electrode 42 into two in the X direction.
  • the dividing portion 454 divides the opening 451 into two.
  • the partition portion 454 passes through the center of the semiconductor element 40 and extends in the Y direction. One of the ends of the partition 454 is connected to the outer peripheral part 453 on the pad 44 side, and the other end is connected to the outer peripheral part 453 on the opposite side from the pad 44.
  • the gate wiring 46 has an outer wiring part 461 and a partition wiring part 462.
  • the outer circumferential wiring portion 461 is arranged at a position overlapping the outer circumferential portion 453 in a plan view.
  • the outer peripheral wiring portion 461 corresponds to the gate wiring 46 shown in the preceding embodiment.
  • the outer peripheral wiring portion 461 has a rectangular ring shape.
  • the partition wiring section 462 is arranged at a position overlapping with the partition section 454 in plan view.
  • the partition wiring section 462 passes through the center of the semiconductor element 40 and extends in the Y direction. One end of the divided wiring section 462 is connected to the outer peripheral wiring section 461 on the pad 44 side, and the other end is connected to the outer peripheral wiring section 461 on the opposite side from the pad 44.
  • the divided wiring section 462 is arranged between the two divided emitter electrodes 42. In the direction in which the divided exposed portions 421 and the divided wiring portions 462 are lined up, that is, in the X direction, the width of the divided wiring portions 462 is narrower than the width of each of the exposed portions 421 . In the X direction, the width of the partition section 454 is narrower than the width of each of the exposed sections 421.
  • the sintered member 101 is arranged across a plurality of partitioned exposed parts 421.
  • the sintered member 101 is arranged not only at a position overlapping each of the exposed parts 421 in a plan view but also at a position overlapping with the partition part 454.
  • the sintered member 101 is located above the upper surface 45a of the partition 454.
  • the area around the opening 451 of the protective film 45 includes a partition 454 .
  • at least a portion of the upper surface 45 a of the protective film 45 around the opening 451 is flush with or less than the bonding surface of the exposed portion 421 .
  • the upper surface 45a of the peripheral portion including the partition portion 454 is located below the joint surface of the exposed portion 421.
  • the other configurations of the semiconductor device 20 are similar to those described in the preceding embodiments.
  • the semiconductor device 20 of the present embodiment not only the upper surface 45a of the peripheral portion of the opening 451 in the outer peripheral region 412 but also the upper surface 45a of the partitioned portion 454 covering the partitioned wiring portion 462 is connected to the bonding surface of the exposed portion 421. It is located at less than the same level.
  • the sintered sheet 101S sintered member 101
  • the width of the divided wiring section 462 is narrower than the width of each of the exposed sections 421.
  • the wiring section covered by the partition section 454 is not limited to the partition wiring section 462 which is the gate wiring 46 . Any wiring may be used as long as it does not overlap the emitter electrode 42 and overlaps the partition 454 in plan view.
  • the arrangement of the partition portions 454 is not limited to the above example.
  • the exposed portion 421 may be divided into four sections by three partition sections 454.
  • the partition portion 454 divides the exposed portion 421 into approximately four equal parts in the X direction.
  • FIG. 15 corresponds to FIG. 13.
  • the partition portions 454 may be arranged in a substantially cross shape in plan, for example, so as to divide the exposed portion 421 into approximately four equal parts.
  • the partition 454 includes a portion extending in the X direction and a portion extending in the Y direction.
  • Spatial relative terms such as “in”, “out”, “behind”, “below”, “low”, “above”, “high” etc. refer to a single element or feature as illustrated. It is used herein to facilitate description that describes relationships to other elements or features. Spatially relative terms may be intended to encompass different orientations of the device during use or operation in addition to the orientation depicted in the figures. For example, when the device in the figures is turned over, elements described as being “below” or “beneath” other elements or features are oriented “above” the other elements or features. Thus, the term “bottom” can encompass both orientations, top and bottom. The device may be oriented in other directions (rotated 90 degrees or other orientations) and the spatially relative descriptors used in this specification shall be interpreted accordingly. .
  • the vehicle drive system 1 is not limited to the above configuration.
  • one motor generator 3 is provided, the present invention is not limited to this.
  • a plurality of motor generators may be provided.
  • the power conversion device 4 includes the inverter 6 as a power conversion section, the present invention is not limited to this.
  • a configuration may include a plurality of inverters.
  • the configuration may include at least one inverter and a converter. It may also include only a converter.
  • the configuration of the semiconductor device 20 is not limited to the above example.
  • the semiconductor device 20 may include at least a semiconductor element having dissimilar electrodes on both sides, a conductive member, and a sintered member that bonds the first main electrode exposed from the protective film to the conductive member.
  • the switching element is not limited to the IGBT 11.
  • a MOSFET may be used.
  • MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor.
  • a protrusion may be provided on the wiring member 50.
  • the wiring member 50 corresponds to a conductive member.
  • the present invention is not limited to this. It can also be applied to a single-sided heat dissipation structure.
  • the collector electrode 43 is connected to a heat sink or a metal body of a substrate, and the emitter electrode 42 is connected to a lead.
  • the lead corresponds to the conductive member.
  • the semiconductor device 20 may include a plurality of semiconductor elements 40 forming one arm. That is, a plurality of semiconductor elements 40 may be connected in parallel to each other to form one arm. Furthermore, the semiconductor device 20 may include a plurality of semiconductor elements 40 that constitute the upper and lower arm circuits 9 for one phase. A plurality of semiconductor elements 40 forming a multi-phase upper and lower arm circuit 9 may be provided.
  • the present invention is not limited to this. At least one of the back surfaces 50b and 60b may be covered with the sealing body 30. At least one of the back surfaces 50b and 60b may be covered with an insulating member (not shown) that is separate from the sealing body 30.
  • the semiconductor device 20 may be configured without the sealing body 30.
  • the configuration of the emitter electrode 42 which is the first main electrode, is not limited to the above example.
  • the emitter electrode 42 may have an intermediate electrode 424.
  • the intermediate electrode 424 is arranged between the base electrode 422 whose main component is Al and the connection electrode 423.
  • the intermediate electrode 424 is formed using a material containing Cu as a main component.
  • the emitter electrode 42 is connected to the semiconductor substrate 41 through a contact hole provided in an insulating film 47 such as a silicon oxide film.
  • the base electrode 422A and the gate wiring 46A are formed using a material containing Cu as a main component.
  • a connection electrode 423 is laminated on a base electrode 422A whose main component is Cu.
  • the gate wiring 46A whose main component is Cu is covered with a protective film 45.
  • 16 and 17 show an example in which the upper surface 45a of the protective film 45 is flush with the bonding surface of the exposed portion 421. However, it goes without saying that the upper surface 45a of the protective film 45 may be located below the bonding surface of the exposed portion 421.
  • the semiconductor element has a wiring portion (46, 46A) that is disposed on the one surface at a position that does not overlap with the first main electrode in a plan view in the thickness direction, and is covered with the protective film.
  • the semiconductor device according to Technical Idea 1 or Technical Idea 2.
  • the protective film has a division part (454) that divides the exposed part (421) of the first main electrode into a plurality of parts,
  • the sintered member is arranged across the plurality of exposed parts,
  • the wiring portion includes a partitioned wiring portion (462) arranged at a position overlapping with the partitioned portion in a plan view in the thickness direction,
  • the semiconductor device according to technical idea 3 wherein the width of the divided wiring portion is narrower than the width of the exposed portion.
  • the semiconductor substrate includes an active region (411) that is an element formation region, an outer peripheral region (412) surrounding the active region in plan view in the thickness direction, and a voltage-resistant structure (413) provided in the outer peripheral region. and, The semiconductor device according to any one of technical ideas 1 to 4, wherein the protective film covers the voltage-resistant structure.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

L'invention concerne un élément semi-conducteur (40) comprenant : une électrode d'émetteur (42) disposée sur une surface d'un substrat semi-conducteur (41) ; et une électrode de collecteur (43) disposée sur la surface inverse. La surface du substrat semi-conducteur (41) est pourvue d'un film de protection (45) ayant une ouverture (451) qui expose l'électrode d'émetteur (42) pour permettre une connexion. Un élément fritté (101) est interposé entre l'électrode d'émetteur (42) et un espaceur conducteur (70), et connecte l'électrode d'émetteur (42) et l'espaceur conducteur (70). Au moins la partie périphérique de l'ouverture (451) parmi la surface supérieure (45a) du film de protection (45) est positionnée de manière affleurante ou inférieure à la surface de connexion de l'électrode d'émetteur (42) dans la direction Z.
PCT/JP2023/030949 2022-09-21 2023-08-28 Dispositif à semi-conducteur WO2024062845A1 (fr)

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JP2022-150584 2022-09-21
JP2022150584A JP2024044822A (ja) 2022-09-21 2022-09-21 半導体装置

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004111885A (ja) * 2002-07-23 2004-04-08 Toshiba Corp 半導体装置
WO2016189643A1 (fr) * 2015-05-26 2016-12-01 三菱電機株式会社 Procédé de fabrication de dispositif à semi-conducteur
JP2018117054A (ja) * 2017-01-19 2018-07-26 株式会社 日立パワーデバイス 半導体装置および電力変換装置
WO2019103028A1 (fr) * 2017-11-22 2019-05-31 三菱電機株式会社 Dispositif à semiconducteur et procédé de fabrication de dispositif à semiconducteur
JP2020035812A (ja) * 2018-08-28 2020-03-05 株式会社 日立パワーデバイス 半導体装置および電力変換装置
JP2021009869A (ja) * 2019-06-28 2021-01-28 日立オートモティブシステムズ株式会社 半導体装置およびその製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004111885A (ja) * 2002-07-23 2004-04-08 Toshiba Corp 半導体装置
WO2016189643A1 (fr) * 2015-05-26 2016-12-01 三菱電機株式会社 Procédé de fabrication de dispositif à semi-conducteur
JP2018117054A (ja) * 2017-01-19 2018-07-26 株式会社 日立パワーデバイス 半導体装置および電力変換装置
WO2019103028A1 (fr) * 2017-11-22 2019-05-31 三菱電機株式会社 Dispositif à semiconducteur et procédé de fabrication de dispositif à semiconducteur
JP2020035812A (ja) * 2018-08-28 2020-03-05 株式会社 日立パワーデバイス 半導体装置および電力変換装置
JP2021009869A (ja) * 2019-06-28 2021-01-28 日立オートモティブシステムズ株式会社 半導体装置およびその製造方法

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