JP2014175511A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Semiconductor device and semiconductor device manufacturing method Download PDF

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JP2014175511A
JP2014175511A JP2013047594A JP2013047594A JP2014175511A JP 2014175511 A JP2014175511 A JP 2014175511A JP 2013047594 A JP2013047594 A JP 2013047594A JP 2013047594 A JP2013047594 A JP 2013047594A JP 2014175511 A JP2014175511 A JP 2014175511A
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brazing material
material layer
semiconductor device
substrate
connection terminal
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Junji Tsuruoka
純司 鶴岡
Seiji Yasui
誠二 安井
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Aisin AW Co Ltd
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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device including brazing material layer thickness maintaining means which can reduce manufacturing cost while maintaining a thickness of a brazing material layer.SOLUTION: A semiconductor device comprises: a substrate; a first brazing material layer formed on the substrate; a semiconductor element joined on the substrate via the first brazing material layer; a second brazing material layer formed on a surface electrode of the semiconductor element on the side opposite to the first brazing material layer side; a connection terminal which includes a connection part joined to the surface electrode of the semiconductor element via the second brazing material layer and a leg part which stands from an end of the connection part on a first side in a predetermined direction in a bent manner; and brazing material layer thickness maintaining means provided only on a second side in the first brazing material layer among the first side in the predetermined direction in the first brazing material layer and the second side in the first brazing material layer, which is opposite to the first side.

Description

本開示は、半導体装置及び半導体装置の製造方法に関する。   The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.

従来から、両面に導電パターンが形成され、その表面側パターンに半導体素子が実装されると共に、裏面側パターンにベース板が接合部を介して接合される絶縁基板を備え、上記裏面側パターン又は上記ベース板に上記接合部の厚さを規制する複数個の突起が設けられる半導体装置が知られている（例えば、特許文献１参照）。この半導体装置では、突起は、接合部の四方の各角に設けられている。   Conventionally, a conductive pattern is formed on both sides, a semiconductor element is mounted on the front side pattern, and an insulating substrate is provided on the back side pattern to which a base plate is joined via a joint portion. A semiconductor device is known in which a base plate is provided with a plurality of protrusions that regulate the thickness of the joint (see, for example, Patent Document 1). In this semiconductor device, the protrusions are provided at the four corners of the joint.

特開２００１−３５８２６７号公報JP 2001-358267 A

ところで、上記の特許文献１に記載されるような突起は、接合部（半田層のような鑞材層）の厚みを維持（確保）し、接合部上に載置される物体の傾斜を防止することができるので、有用である。しかしながら、かかる効果を維持しつつ、突起の数を低減することができれば、製造コスト等を低減することができる。   By the way, the protrusions described in the above-mentioned Patent Document 1 maintain (ensure) the thickness of the joint (a solder layer such as a solder layer) to prevent the object placed on the joint from being inclined. It is useful because it can. However, if the number of protrusions can be reduced while maintaining this effect, the manufacturing cost and the like can be reduced.

そこで、本開示は、鑞材層の厚みを維持しつつ、製造コストを低減することができる鑞材層厚維持手段を備えた半導体装置及び半導体装置の製造方法の提供を目的とする。   Therefore, an object of the present disclosure is to provide a semiconductor device including a brazing material layer thickness maintaining means capable of reducing the manufacturing cost while maintaining the thickness of the brazing material layer, and a method for manufacturing the semiconductor device.

本開示の一局面によれば、基板と、
前記基板上に形成される第１鑞材層と、
前記基板上に前記第１鑞材層を介して接合される半導体素子と、
前記半導体素子における前記第１鑞材層側とは逆側の表面電極上に形成される第２鑞材層と、
前記半導体素子の表面電極に前記第２鑞材層を介して接合される接続部、及び、前記接続部における所定方向の第１側の端部から屈曲して立ち上がる脚部を備える接続端子と、
前記第１鑞材層内における前記所定方向の第１側及びその反対側である第２側のうちの、前記第２側のみに設けられる鑞材層厚維持手段とを含む、半導体装置が提供される。 According to one aspect of the present disclosure, a substrate;
A first brazing material layer formed on the substrate;
A semiconductor element bonded to the substrate via the first brazing material layer;
A second brazing material layer formed on the surface electrode opposite to the first brazing material layer side in the semiconductor element;
A connection terminal having a connection portion joined to the surface electrode of the semiconductor element via the second brazing material layer, and a leg portion that bends and rises from an end portion on the first side in a predetermined direction in the connection portion;
A semiconductor device comprising: a first layer in the first brazing layer and a brazing layer thickness maintaining means provided only on the second side of the first side in the predetermined direction and the second side opposite to the first side. Is done.

本開示によれば、鑞材層の厚みを維持しつつ、製造コストを低減することができる鑞材層厚維持手段を備えた半導体装置及び半導体装置の製造方法が得られる。   According to the present disclosure, it is possible to obtain a semiconductor device including a brazing material layer thickness maintaining unit capable of reducing the manufacturing cost while maintaining the thickness of the brazing material layer, and a method for manufacturing the semiconductor device.

一実施例による半導体装置１を概略的に示す上面図である。1 is a top view schematically showing a semiconductor device 1 according to an embodiment. 図１に示す半導体装置１のラインＡ−Ａに沿った概略断面図であるFIG. 2 is a schematic cross-sectional view along the line AA of the semiconductor device 1 shown in FIG. 1. ヒートスプレッダ２０上に設けられるＷＢバンプ７０Ａ、７０Ｂを概略的に示す上面図である。3 is a top view schematically showing WB bumps 70A and 70B provided on a heat spreader 20. FIG. ヒートスプレッダ２０上に接合されたＷＢバンプ７０Ａの状態を模式的に示す図である。It is a figure which shows typically the state of WB bump 70A joined on the heat spreader 20. FIG. 比較例による半導体装置１’の概略断面図である。It is a schematic sectional drawing of semiconductor device 1 'by a comparative example. 半導体装置１の製造方法の流れの概略の一例を示す図である。2 is a diagram showing an example of a schematic flow of a manufacturing method of the semiconductor device 1. FIG. 他の例による半導体装置２の概略断面図である。It is a schematic sectional drawing of the semiconductor device 2 by another example. 更なる他の例による半導体装置３の概略断面図である。It is a schematic sectional drawing of the semiconductor device 3 by another example.

以下、添付図面を参照しながら各実施例について詳細に説明する。   Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

図１は、一実施例による半導体装置１を概略的に示す上面図である。図２は、図１に示す半導体装置１の概略断面図である。尚、図１においては、半田層５０（はみ出す部分）の図示が省略されている。また、図２においては、図１には図示が省略されているバスバー８０が図示されている。尚、半導体装置１の上下方向は、半導体装置１の搭載状態に応じて上下方向が異なるが、以下では、便宜上、半導体装置１のヒートスプレッダ２０に対して半導体チップ１００，２００が存在する側を上方とする。半導体装置１は、例えば、ハイブリッド車又は電気自動車で使用されるモータ駆動用のインバータを構成するものであってよい。   FIG. 1 is a top view schematically showing a semiconductor device 1 according to an embodiment. FIG. 2 is a schematic cross-sectional view of the semiconductor device 1 shown in FIG. In FIG. 1, illustration of the solder layer 50 (protruding portion) is omitted. 2 shows a bus bar 80 which is not shown in FIG. Although the vertical direction of the semiconductor device 1 differs depending on the mounting state of the semiconductor device 1, below, for convenience, the side where the semiconductor chips 100, 200 are present is located above the heat spreader 20 of the semiconductor device 1. And The semiconductor device 1 may constitute an inverter for driving a motor used in, for example, a hybrid vehicle or an electric vehicle.

半導体装置１は、図1及び図２に示すように、接続端子１２と、下半田層５０Ａ，５０Ｂと、上半田層５１Ａ，５１Ｂと、ヒートスプレッダ２０と、半導体チップ１００，２００と、ワイヤボンドバンプ（以下、ＷＢバンプという）７０Ａ，７０Ｂとを含む。   As shown in FIGS. 1 and 2, the semiconductor device 1 includes a connection terminal 12, lower solder layers 50A and 50B, upper solder layers 51A and 51B, a heat spreader 20, semiconductor chips 100 and 200, and wire bond bumps. (Hereinafter referred to as WB bumps) 70A and 70B.

半導体チップ１００は、任意の半導体素子であるが、本例ではＩＧＢＴ（Insulated Gate Bipolar Transistor）である。半導体チップ１００は、矩形の平板状の形態を有し、上面に表面電極（エミッタ電極）１０２を備え、下面にコレクタ電極を備える。また、半導体チップ１００は、基板（図示せず）にワイヤボンディング等で接続される端子部１０３を端部に含む。尚、端子部１０３は、ゲート電極等を含んでよい。半導体チップ１００は、ＩＧＢＴに代えて、ＭＯＳＦＥＴ（Metal Oxide Semiconductor Field‐Effect Transistor)のような他のスイッチング素子であってもよいし、スイッチング素子以外の素子であってもよい。   The semiconductor chip 100 is an arbitrary semiconductor element, but in this example, is an IGBT (Insulated Gate Bipolar Transistor). The semiconductor chip 100 has a rectangular flat plate shape, and includes a surface electrode (emitter electrode) 102 on the upper surface and a collector electrode on the lower surface. Further, the semiconductor chip 100 includes a terminal portion 103 connected to a substrate (not shown) by wire bonding or the like at an end portion. Note that the terminal portion 103 may include a gate electrode or the like. The semiconductor chip 100 may be another switching element such as a MOSFET (Metal Oxide Semiconductor Field-Effect Transistor) instead of the IGBT, or may be an element other than the switching element.

半導体チップ１００は、下半田層５０Ａを介してヒートスプレッダ２０の上面に接合される。下半田層５０Ａには、ＷＢバンプ７０Ａが含まれる。ＷＢバンプ７０Ａは、図２に示すように、下半田層５０Ａ内の一方の端部側のみに設けられる。即ち、ＷＢバンプ７０Ａは、図２に示すように、下半田層５０Ａ内におけるＸ方向の第２側（Ｘ２側）のみに設けられる。この構成の技術的意義については後述する。   The semiconductor chip 100 is bonded to the upper surface of the heat spreader 20 via the lower solder layer 50A. The lower solder layer 50A includes a WB bump 70A. As shown in FIG. 2, the WB bump 70A is provided only on one end side in the lower solder layer 50A. That is, as shown in FIG. 2, the WB bump 70A is provided only on the second side (X2 side) in the X direction in the lower solder layer 50A. The technical significance of this configuration will be described later.

ＷＢバンプ７０Ａは、ワイヤボンディングによりヒートスプレッダ２０の上面に接合される突起体である。ＷＢバンプ７０Ａは、好ましくは、下半田層５０Ａにおける熱応力を低減する観点から、下半田層５０Ａの材料に対して熱膨張係数の差が所定基準以内の材料により形成される。所定基準は、使用条件（発熱量）等に応じて異なり、下半田層５０Ａ内のクラック等が生じないような観点から設定されてよい。例えば、ＷＢバンプ７０Ａは、一般的な半田（Ｓｎ−Ｐｂや、Ｓｎ−Ｚｎ−Ａｌ）に対して熱膨張係数の差が小さいアルミにより形成されてもよい。尚、アルミは、典型的には、２４ｐｐｍ／℃の熱膨張係数を有し、Ｓｎ−ＰｂやＳｎ−Ｚｎ−Ａｌの熱膨張係数と略同一である。   The WB bump 70A is a protrusion that is bonded to the upper surface of the heat spreader 20 by wire bonding. The WB bump 70A is preferably formed of a material having a difference in thermal expansion coefficient within a predetermined standard with respect to the material of the lower solder layer 50A from the viewpoint of reducing thermal stress in the lower solder layer 50A. The predetermined standard differs depending on the use condition (heat generation amount) and the like, and may be set from the viewpoint that a crack or the like in the lower solder layer 50A does not occur. For example, the WB bump 70A may be formed of aluminum having a small difference in thermal expansion coefficient with respect to general solder (Sn—Pb or Sn—Zn—Al). Aluminum typically has a thermal expansion coefficient of 24 ppm / ° C., and is substantially the same as that of Sn—Pb or Sn—Zn—Al.

半導体チップ２００は、任意の半導体素子であるが、本例ではフリーホイールダイオード（ＦＷＤ：Free Wheeling Diode）である。半導体チップ２００は、矩形の平板状の形態を有し、上面に表面電極（アノード電極）２０２を備え、下面にカソード電極を備える。   The semiconductor chip 200 is an arbitrary semiconductor element. In this example, the semiconductor chip 200 is a free wheeling diode (FWD). The semiconductor chip 200 has a rectangular flat plate shape, and includes a surface electrode (anode electrode) 202 on the upper surface and a cathode electrode on the lower surface.

半導体チップ２００は、下半田層５０Ｂを介してヒートスプレッダ２０の上面に接合される。下半田層５０Ｂには、ＷＢバンプ７０Ｂが含まれる。ＷＢバンプ７０Ｂは、図２に示すように、下半田層５０Ｂ内の一方の端部側のみに設けられる。即ち、ＷＢバンプ７０Ｂは、図２に示すように、下半田層５０Ｂ内におけるＸ方向の第１側（Ｘ１側）のみに設けられる。この構成の技術的意義については後述する。   The semiconductor chip 200 is bonded to the upper surface of the heat spreader 20 via the lower solder layer 50B. The lower solder layer 50B includes a WB bump 70B. As shown in FIG. 2, the WB bump 70B is provided only on one end side in the lower solder layer 50B. That is, as shown in FIG. 2, the WB bump 70B is provided only on the first side (X1 side) in the X direction in the lower solder layer 50B. The technical significance of this configuration will be described later.

ＷＢバンプ７０Ｂは、ワイヤボンディングによりヒートスプレッダ２０の上面に接合される突起体である。同様に、ＷＢバンプ７０Ｂは、好ましくは、下半田層５０Ｂにおける熱応力を低減する観点から、下半田層５０Ｂの材料に対して熱膨張係数の差が所定基準以内の材料により形成される。   The WB bump 70B is a protrusion that is bonded to the upper surface of the heat spreader 20 by wire bonding. Similarly, from the viewpoint of reducing thermal stress in the lower solder layer 50B, the WB bump 70B is preferably made of a material whose difference in thermal expansion coefficient is within a predetermined standard with respect to the material of the lower solder layer 50B.

接続端子１２は、側面視で、図２に示すように、上向きに凸形状をなす形状を有し、ヒートスプレッダ２０の上面から上方に離間した上部１２１と、ヒートスプレッダ２０の上面に平行に延在する２つの接続部１２２と、上部１２１及び２つの接続部１２２を繋ぐ上下方向の脚部１２３とから形成される。２つの接続部１２２は、上面視で、対応する半導体チップ１００、２００の表面電極１０２，２０２の矩形形状よりも僅かに小さい矩形形状を有してよい。半導体チップ１００側の接続部１２２は、半導体チップ１００の端子部１０３側（Ｘ方向のＸ２側）が自由端となり、他の側（Ｘ方向のＸ１側）で脚部１２３と連続する。半導体チップ２００側の接続部１２２は、半導体チップ２００のＸ方向のＸ１側が自由端となり、他の側（Ｘ方向のＸ２側）で脚部１２３と連続する。半導体チップ１００側の脚部１２３は、半導体チップ１００側の接続部１２２のＸ方向の第１側（Ｘ１側）の端部から屈曲して上部１２１へと立ち上がる。半導体チップ２００側の脚部１２３は、半導体チップ２００側の接続部１２２のＸ方向の第２側（Ｘ２側）の端部から屈曲して上部１２１へと立ち上がる。接続部１２２から脚部１２３への屈曲部の曲げ方向外側には角Ｒ部１２５が形成される。   As shown in FIG. 2, the connection terminal 12 has a shape that protrudes upward as viewed from the side, and extends in parallel to the upper surface 121 spaced upward from the upper surface of the heat spreader 20 and the upper surface of the heat spreader 20. It is formed of two connecting portions 122 and an upper leg 121 and a vertical leg portion 123 connecting the two connecting portions 122. The two connection parts 122 may have a rectangular shape slightly smaller than the rectangular shape of the surface electrodes 102 and 202 of the corresponding semiconductor chips 100 and 200 when viewed from above. The connection part 122 on the semiconductor chip 100 side is a free end on the terminal part 103 side (X2 side in the X direction) of the semiconductor chip 100 and continues to the leg part 123 on the other side (X1 side in the X direction). The connection part 122 on the semiconductor chip 200 side is a free end on the X1 side in the X direction of the semiconductor chip 200 and is continuous with the leg part 123 on the other side (X2 side in the X direction). The leg portion 123 on the semiconductor chip 100 side is bent from the end portion on the first side (X1 side) in the X direction of the connection portion 122 on the semiconductor chip 100 side and rises to the upper portion 121. The leg portion 123 on the semiconductor chip 200 side is bent from the end portion on the second side (X2 side) in the X direction of the connection portion 122 on the semiconductor chip 200 side and rises to the upper portion 121. A corner R portion 125 is formed on the outer side in the bending direction of the bent portion from the connecting portion 122 to the leg portion 123.

接続端子１２は、半導体チップ１００、２００の表面電極１０２，２０２に上半田層５１Ａ、５１Ｂを介してそれぞれ固着（接合）される。図示の例では、接続端子１２は、ＩＧＢＴのエミッタ電極と、ＦＷＤのアノード電極に上半田層５１Ａ、５１Ｂにより接合される。即ち、接続端子１２の２つの接続部１２２は、それぞれ、ＩＧＢＴのエミッタ電極と、ＦＷＤのアノード電極に接合される。また、接続端子１２の上部１２１には、図１及び図２に示すように、バスバー８０が、例えばレーザ溶接により、接合される。   The connection terminal 12 is fixed (bonded) to the surface electrodes 102 and 202 of the semiconductor chips 100 and 200 via the upper solder layers 51A and 51B, respectively. In the illustrated example, the connection terminal 12 is joined to the IGBT emitter electrode and the FWD anode electrode by upper solder layers 51A and 51B. That is, the two connection portions 122 of the connection terminal 12 are respectively joined to the IGBT emitter electrode and the FWD anode electrode. Moreover, as shown in FIG.1 and FIG.2, the bus-bar 80 is joined to the upper part 121 of the connecting terminal 12 by laser welding, for example.

ヒートスプレッダ２０は、半導体チップ１００，２００で発生する熱を吸収し拡散する部材である。ヒートスプレッダ２０は、例えば銅、アルミなどの熱拡散性の優れた金属から形成される。本例では、一例として、ヒートスプレッダ２０は、銅により形成される。銅としては、伝導率が銅材の中で最も高い無酸素銅(C1020)が好適である。   The heat spreader 20 is a member that absorbs and diffuses heat generated in the semiconductor chips 100 and 200. The heat spreader 20 is formed from a metal having excellent thermal diffusibility, such as copper or aluminum. In this example, as an example, the heat spreader 20 is made of copper. As copper, oxygen-free copper (C1020) having the highest conductivity among copper materials is suitable.

尚、ヒートスプレッダ２０は、図示を省略するが、絶縁層を介してヒートシンクに接合されてよい。絶縁層は、樹脂接着剤や樹脂シートから構成されてよい。絶縁層は、例えばアルミナをフィラーとした樹脂で形成されてもよい。絶縁層は、ヒートスプレッダ２０とヒートシンクの間に設けられ、ヒートスプレッダ２０とヒートシンクに接合する。絶縁層は、ヒートスプレッダ２０とヒートシンクとの間の電気的な絶縁性を確保しつつ、ヒートスプレッダ２０からヒートシンクへの高い熱伝導性を確保する。ヒートシンクは、熱伝導性の良い材料から形成され、例えば、アルミなどの金属により形成されてもよい。ヒートシンクは、下面側にフィンを備える。フィンの数や配列態様は任意である。フィンは、ストレートフィンであってもよいし、その他、ピンフィンの千鳥配置等で実現されてもよい。半導体装置１の実装状態では、フィンは、冷却水や冷却空気のような冷却媒体と接触する。このようにして、半導体装置１の駆動時に生じる半導体チップ１００，２００からの熱は、ヒートスプレッダ２０、絶縁層を介して、ヒートシンクのフィンから冷却媒体へと伝達され、半導体装置１の冷却が実現される。   Although not shown, the heat spreader 20 may be joined to the heat sink via an insulating layer. The insulating layer may be composed of a resin adhesive or a resin sheet. The insulating layer may be formed of a resin using alumina as a filler, for example. The insulating layer is provided between the heat spreader 20 and the heat sink, and is bonded to the heat spreader 20 and the heat sink. The insulating layer ensures high thermal conductivity from the heat spreader 20 to the heat sink while ensuring electrical insulation between the heat spreader 20 and the heat sink. The heat sink is formed of a material having good thermal conductivity, and may be formed of a metal such as aluminum, for example. The heat sink includes fins on the lower surface side. The number and arrangement of the fins are arbitrary. The fins may be straight fins, or may be realized by staggered arrangement of pin fins. In the mounted state of the semiconductor device 1, the fin comes into contact with a cooling medium such as cooling water or cooling air. In this way, heat from the semiconductor chips 100 and 200 generated when the semiconductor device 1 is driven is transmitted from the fins of the heat sink to the cooling medium via the heat spreader 20 and the insulating layer, and cooling of the semiconductor device 1 is realized. The

尚、ヒートスプレッダ２０上には、他の半導体チップや接続端子等が更に設けられてもよい。例えば、ヒートスプレッダ２０上には、第２接続端子（図示せず）が半田により接合されてもよい。この場合、第２接続端子は、ＩＧＢＴのコレクタ電極の取り出し部を構成する。   Note that other semiconductor chips, connection terminals, and the like may be further provided on the heat spreader 20. For example, a second connection terminal (not shown) may be joined on the heat spreader 20 by solder. In this case, the second connection terminal constitutes an extraction portion for the IGBT collector electrode.

図３は、ヒートスプレッダ２０上に設けられるＷＢバンプ７０Ａ、７０Ｂを概略的に示す上面図である。図３には、半導体チップ１００、２００の載置範囲Ｐ１，Ｐ２が点線範囲にてそれぞれ示されている。   FIG. 3 is a top view schematically showing the WB bumps 70A and 70B provided on the heat spreader 20. As shown in FIG. In FIG. 3, the mounting ranges P1 and P2 of the semiconductor chips 100 and 200 are shown by dotted line ranges, respectively.

半導体チップ１００側のＷＢバンプ７０Ａは、上述の如く、半導体チップ１００の載置範囲Ｐ１のＸ方向の第２側（Ｘ２側）のみに設けられる。図３に示す例では、ＷＢバンプ７０Ａは、Ｘ方向に垂直なＹ方向で互いに離間して２つ設けられる。２つのＷＢバンプ７０Ａは、線状の形態であり、Ｘ方向のＸ２側の方が間隔が広くなるハの字状に配設される。即ち、ＷＢバンプ７０Ａは、線状の形態であり、半導体チップ１００の載置範囲Ｐ１の中心Ｃ１から見て放射状に配置される。これにより、半導体チップ１００の載置範囲Ｐ１の中心Ｃ１付近に付与される溶融状態の半田は、放射状に広がる際、ＷＢバンプ７０Ａに阻害されることがなく、半導体チップ１００の載置範囲Ｐ１の全体に広がることができる。但し、ＷＢバンプ７０Ａの向きは任意であり、例えばＷＢバンプ７０Ａは、Ｙ方向に平行に配置されてもよいし、Ｘ方向に平行に配置されてもよい。また、ＷＢバンプ７０Ａの数も任意である。例えば、ＷＢバンプ７０Ａは、１つだけ配置されてもよいし、３つ以上配置されてもよい。尚、１つだけ配置される場合は、ＷＢバンプ７０Ａは、好ましくは、半導体チップ１００の載置範囲Ｐ１のＹ方向の中心付近に配置される。この際、ＷＢバンプ７０Ａは、好ましくは、載置範囲Ｐ１のＹ方向の略全幅に亘って延在する。   As described above, the WB bump 70A on the semiconductor chip 100 side is provided only on the second side (X2 side) in the X direction of the mounting range P1 of the semiconductor chip 100. In the example shown in FIG. 3, two WB bumps 70A are provided apart from each other in the Y direction perpendicular to the X direction. The two WB bumps 70A have a linear shape, and are arranged in a square shape with a wider interval on the X2 side in the X direction. That is, the WB bumps 70 </ b> A have a linear shape and are arranged radially when viewed from the center C <b> 1 of the mounting range P <b> 1 of the semiconductor chip 100. Thereby, the molten solder applied near the center C1 of the mounting range P1 of the semiconductor chip 100 is not obstructed by the WB bumps 70A when spreading radially, and the solder of the mounting range P1 of the semiconductor chip 100 is not disturbed. Can spread throughout. However, the direction of the WB bump 70A is arbitrary. For example, the WB bump 70A may be arranged in parallel to the Y direction or may be arranged in parallel to the X direction. The number of WB bumps 70A is also arbitrary. For example, only one WB bump 70A may be disposed, or three or more WB bumps 70A may be disposed. When only one is disposed, the WB bump 70A is preferably disposed near the center in the Y direction of the mounting range P1 of the semiconductor chip 100. At this time, the WB bump 70A preferably extends over substantially the entire width in the Y direction of the placement range P1.

半導体チップ２００側のＷＢバンプ７０Ｂは、上述の如く、半導体チップ２００の載置範囲Ｐ２のＸ方向の第１側（Ｘ１側）のみに設けられる。図３に示す例では、ＷＢバンプ７０Ｂは、Ｘ方向に垂直なＹ方向で互いに離間して２つ設けられる。２つのＷＢバンプ７０Ｂは、線状の形態であり、Ｘ方向のＸ１側の方が間隔が広くなるハの字状に配設される。これにより、半導体チップ２００の載置範囲Ｐ２の中心Ｃ２付近に付与される溶融状態の半田は、放射状に広がる際、ＷＢバンプ７０Ｂに阻害されることがなく、半導体チップ２００の載置範囲Ｐ２の全体に広がることができる。但し、ＷＢバンプ７０Ｂの向きは任意であり、例えばＷＢバンプ７０Ｂは、Ｙ方向に平行に配置されてもよいし、Ｘ方向に平行に配置されてもよい。また、ＷＢバンプ７０Ｂの数も任意である。例えば、ＷＢバンプ７０Ｂは、１つだけ配置されてもよいし、３つ以上配置されてもよい。尚、１つだけ配置される場合は、ＷＢバンプ７０Ｂは、好ましくは、半導体チップ２００の載置範囲Ｐ２のＹ方向の中心付近に配置される。この際、ＷＢバンプ７０Ｂは、好ましくは、載置範囲Ｐ２のＹ方向の略全幅に亘って延在する。   As described above, the WB bump 70B on the semiconductor chip 200 side is provided only on the first side (X1 side) in the X direction of the mounting range P2 of the semiconductor chip 200. In the example shown in FIG. 3, two WB bumps 70B are provided apart from each other in the Y direction perpendicular to the X direction. The two WB bumps 70B have a linear shape, and are arranged in a square shape with a wider interval on the X1 side in the X direction. As a result, the molten solder applied to the vicinity of the center C2 of the mounting range P2 of the semiconductor chip 200 is not obstructed by the WB bump 70B when spreading radially, and the solder of the mounting range P2 of the semiconductor chip 200 is not disturbed. Can spread throughout. However, the direction of the WB bump 70B is arbitrary. For example, the WB bump 70B may be arranged in parallel to the Y direction or may be arranged in parallel to the X direction. The number of WB bumps 70B is also arbitrary. For example, only one WB bump 70B may be arranged, or three or more WB bumps 70B may be arranged. When only one is disposed, the WB bump 70B is preferably disposed near the center in the Y direction of the mounting range P2 of the semiconductor chip 200. At this time, the WB bump 70B preferably extends over substantially the entire width of the placement range P2 in the Y direction.

図４は、ヒートスプレッダ２０上に接合されたＷＢバンプ７０Ａの状態を模式的に示す図である。尚、ここでは、ＷＢバンプ７０Ａについてのみ説明するが、ＷＢバンプ７０Ｂについても同様であってよい。   FIG. 4 is a diagram schematically showing a state of the WB bump 70 </ b> A bonded on the heat spreader 20. Although only the WB bump 70A will be described here, the same applies to the WB bump 70B.

ＷＢバンプ７０Ａは、典型的には、図４（Ａ）に示すように、２箇所７２，７４でヒートスプレッダ２０上に接合される。尚、この接合は、熱、超音波、圧力等により実現されてよい。但し、ＷＢバンプ７０Ａは、好ましくは、熱膨張による下半田層５０Ａのクラック等を防止する観点から、熱膨張量が小さくなるように短い長さで形成される。このため、ＷＢバンプ７０Ａは、図４（Ｂ）に示すように、１箇所７２だけでヒートスプレッダ２０上に接合されてもよい。これにより、ＷＢバンプ７０Ａの長さを短くすることができ、熱膨張量が低減されるので、下半田層５０Ａのクラック等を効果的に防止することができる。   Typically, the WB bump 70A is bonded onto the heat spreader 20 at two locations 72 and 74 as shown in FIG. This bonding may be realized by heat, ultrasonic waves, pressure, or the like. However, the WB bump 70A is preferably formed with a short length so as to reduce the amount of thermal expansion from the viewpoint of preventing cracks and the like of the lower solder layer 50A due to thermal expansion. For this reason, the WB bump 70A may be bonded onto the heat spreader 20 only at one location 72 as shown in FIG. As a result, the length of the WB bump 70A can be shortened and the amount of thermal expansion is reduced, so that cracks and the like of the lower solder layer 50A can be effectively prevented.

図５は、比較例による半導体装置１’の概略断面図である。比較例による半導体装置１’は、ＷＢバンプ７０Ａ，７０Ｂを備えていない点が、上述した本実施例による半導体装置１と異なる。   FIG. 5 is a schematic cross-sectional view of a semiconductor device 1 ′ according to a comparative example. The semiconductor device 1 ′ according to the comparative example is different from the semiconductor device 1 according to the present embodiment described above in that the WB bumps 70 </ b> A and 70 </ b> B are not provided.

比較例による半導体装置１’では、図５に模式的に矢印Ｑ１で示すように、製造工程中、上半田層５１Ａ，５１Ｂを形成する半田（溶融状態の半田）であって、接続端子１２の角Ｒ部１２５の半田が、表面張力で半導体チップ１００，２００を上方に引っ張り上げる。このため、図５に模式的に矢印Ｑ１及びＱ２で示すように、溶融状態の下半田層５０Ａ，５０Ｂの上に載置されている半導体チップ１００，２００が傾き（角Ｒ部１２５側が上になる態様で傾き）、接続端子１２の自由端側における下半田層５０Ａ，５０Ｂの厚みが薄くなる。この場合、下半田層５０Ａ，５０Ｂの接続端子１２の自由端側において熱応力に起因したクラックが発生しやすくなる。   In the semiconductor device 1 ′ according to the comparative example, as schematically shown by an arrow Q1 in FIG. 5, the solder (molten solder) that forms the upper solder layers 51A and 51B during the manufacturing process, The solder of the corner R portion 125 pulls the semiconductor chips 100 and 200 upward by surface tension. Therefore, as schematically indicated by arrows Q1 and Q2 in FIG. 5, the semiconductor chips 100, 200 placed on the lower solder layers 50A, 50B in the molten state are inclined (the corner R portion 125 side is on the upper side). The thickness of the lower solder layers 50A and 50B on the free end side of the connection terminal 12 is reduced. In this case, cracks due to thermal stress are likely to occur on the free ends of the connection terminals 12 of the lower solder layers 50A and 50B.

これに対して、本実施例によれば、図２に示すように、下半田層５０Ａ，５０Ｂ内における接続端子１２の自由端側（角Ｒ部１２５側とは反対側）には、ＷＢバンプ７０Ａ，７０Ｂが設けられる。ＷＢバンプ７０Ａ，７０Ｂは、溶融状態の下半田層５０Ａ，５０Ｂ内においても溶融せず、半導体チップ１００，２００の下面を支持する。従って、接続端子１２の角Ｒ部１２５の半田が、表面張力で半導体チップ１００，２００を上方に引っ張り上げようとしても、半導体チップ１００，２００は傾くことが無い。これにより、接続端子１２の自由端側における下半田層５０Ａ，５０Ｂの厚みが薄くなることが防止されるので、下半田層５０Ａ，５０Ｂの接続端子１２の自由端側における熱応力に起因したクラックの発生を低減することができる。   On the other hand, according to this embodiment, as shown in FIG. 2, the WB bumps are formed on the free end side (the opposite side to the corner R portion 125 side) of the connection terminal 12 in the lower solder layers 50A and 50B. 70A and 70B are provided. The WB bumps 70A and 70B are not melted in the molten lower solder layers 50A and 50B, and support the lower surfaces of the semiconductor chips 100 and 200. Therefore, even if the solder at the corner R portion 125 of the connection terminal 12 tries to pull the semiconductor chips 100 and 200 upward by surface tension, the semiconductor chips 100 and 200 do not tilt. This prevents the thickness of the lower solder layers 50A and 50B on the free end side of the connection terminal 12 from being reduced, so cracks caused by thermal stress on the free end side of the connection terminal 12 of the lower solder layers 50A and 50B. Can be reduced.

また、本実施例によれば、図２等に示すように、ＷＢバンプ７０Ａ，７０Ｂは、半導体チップ１００，２００の載置範囲Ｐ１、Ｐ２のＸ方向の両側（例えば４隅）に設けられるのではなく、半導体チップ１００，２００の載置範囲Ｐ１、Ｐ２の一端側のみ（接続端子１２の自由端側のみ）に設けられる。従って、ＷＢバンプ７０Ａ，７０Ｂの数を低減して、製造コストを低減することができる。   Further, according to the present embodiment, as shown in FIG. 2 and the like, the WB bumps 70A and 70B are provided on both sides (for example, four corners) of the mounting ranges P1 and P2 of the semiconductor chips 100 and 200 in the X direction. Instead, it is provided only on one end side of the mounting ranges P1, P2 of the semiconductor chips 100, 200 (only on the free end side of the connection terminal 12). Therefore, the number of WB bumps 70A and 70B can be reduced, and the manufacturing cost can be reduced.

次に、半導体装置１の製造方法について説明する。   Next, a method for manufacturing the semiconductor device 1 will be described.

図６は、半導体装置１の製造方法の流れの概略の一例を示す図である。   FIG. 6 is a diagram illustrating an example of a schematic flow of a manufacturing method of the semiconductor device 1.

ステップ６００では、ヒートスプレッダ２０上の所定位置にＷＢバンプ７０Ａ，７０Ｂを接合する（図３及び図４参照）。   In step 600, the WB bumps 70A and 70B are bonded to predetermined positions on the heat spreader 20 (see FIGS. 3 and 4).

ステップ６０２では、ヒートスプレッダ２０上の半導体チップ１００、２００の載置範囲Ｐ１，Ｐ２内に溶融状態の半田を付与する。例えば、半田は、半導体チップ１００、２００の載置範囲Ｐ１，Ｐ２の中心Ｃ１，Ｃ２付近に付与されてもよい。尚、このようにして付与された半田は、下半田層５０Ａ，５０Ｂを形成することになる。   In step 602, molten solder is applied to the placement ranges P 1 and P 2 of the semiconductor chips 100 and 200 on the heat spreader 20. For example, the solder may be applied near the centers C1 and C2 of the mounting ranges P1 and P2 of the semiconductor chips 100 and 200. The solder applied in this way forms the lower solder layers 50A and 50B.

ステップ６０４では、ヒートスプレッダ２０上の半導体チップ１００、２００の載置範囲Ｐ１，Ｐ２内の半田の上に、半導体チップ１００、２００を載置する。この際、半導体チップ１００、２００は、溶融状態にある半田が載置範囲Ｐ１，Ｐ２の全体に行き渡るように、揺動されてもよい（即ちスクラブ工程が実行されてもよい）。   In step 604, the semiconductor chips 100, 200 are placed on the solder in the placement ranges P1, P2 of the semiconductor chips 100, 200 on the heat spreader 20. At this time, the semiconductor chips 100 and 200 may be swung so that the solder in a molten state reaches the entire placement ranges P1 and P2 (that is, a scrub process may be performed).

ステップ６０６では、半導体チップ１００、２００の表面電極１０２，２０２上に、溶融状態の半田を付与する。例えば、半田は、表面電極１０２，２０２の中心付近に付与されてもよい。尚、このようにして付与された半田は、上半田層５１Ａ，５１Ｂを形成することになる。   In step 606, molten solder is applied on the surface electrodes 102 and 202 of the semiconductor chips 100 and 200. For example, the solder may be applied near the center of the surface electrodes 102 and 202. The solder applied in this way forms upper solder layers 51A and 51B.

ステップ６０８では、半導体チップ１００、２００の表面電極１０２，２０２上の半田の上に、接続端子１２を載置する。この際、接続端子１２は、図２に示すように、２つの接続部１２２が表面電極１０２，２０２に接合される向きで載置される。この作業は、ステップ６０２で付与された半田が依然として溶融状態にある間、実行されてよい。かかる場合でも、上述の如く、半導体チップ１００，２００が傾くことが無いためである。これにより、ステップ６０２で付与された半田が固化した後に、ステップ６０６及びステップ６０８の作業を行う必要が無いので、製造時間を短縮することができる。   In step 608, the connection terminals 12 are placed on the solder on the surface electrodes 102 and 202 of the semiconductor chips 100 and 200. At this time, the connection terminal 12 is placed in a direction in which the two connection portions 122 are joined to the surface electrodes 102 and 202 as shown in FIG. This operation may be performed while the solder applied in step 602 is still in a molten state. Even in such a case, the semiconductor chips 100 and 200 do not tilt as described above. As a result, it is not necessary to perform the operations of Step 606 and Step 608 after the solder applied in Step 602 is solidified, so that the manufacturing time can be shortened.

図７は、他の例による半導体装置２の概略断面図である。   FIG. 7 is a schematic cross-sectional view of a semiconductor device 2 according to another example.

図７に示す半導体装置２は、図１等に示した半導体装置１に対して、接続端子１２０の構成と、ＷＢバンプ７０Ａ，７０Ｂの位置とが主に異なる。他の構成については、同様であってよい。   The semiconductor device 2 shown in FIG. 7 differs from the semiconductor device 1 shown in FIG. 1 and the like mainly in the configuration of the connection terminals 120 and the positions of the WB bumps 70A and 70B. Other configurations may be the same.

接続端子１２０は、側面視で下側が開口するＣ字型の断面を有し、従って、図１等に示した半導体装置１の接続端子１２に対して、脚部１２３の位置が異なる。具体的には、半導体チップ１００側の脚部１２３は、半導体チップ１００のＸ方向のＸ２側に設けられ、半導体チップ２００側の脚部１２３は、半導体チップ２００のＸ方向のＸ１側に設けられる。従って、かかる構成の場合、半導体チップ１００側の角Ｒ部１２５は、半導体チップ１００のＸ方向のＸ２側に設けられるので、製造工程中、半導体チップ１００は、上半田層５１Ａに係る溶解状態の半田の表面張力によりＸ方向のＸ２側が引っ張り上げられようとする。このため、ＷＢバンプ７０Ａは、図７に示すように、下半田層５０Ａ内におけるＸ方向の第１側（Ｘ１側）のみに設けられる。同様に、半導体チップ２００側の角Ｒ部１２５は、半導体チップ２００のＸ方向のＸ１側に設けられるので、製造工程中、半導体チップ２００は、上半田層５１Ｂの溶解状態の半田の表面張力によりＸ方向のＸ１側が引っ張り上げられようとする。このため、ＷＢバンプ７０Ｂは、図７に示すように、下半田層５０Ｂ内におけるＸ方向の第２側（Ｘ２側）のみに設けられる。   The connection terminal 120 has a C-shaped cross section that is open on the lower side in a side view, and therefore the position of the leg 123 is different from the connection terminal 12 of the semiconductor device 1 shown in FIG. Specifically, the leg 123 on the semiconductor chip 100 side is provided on the X2 side in the X direction of the semiconductor chip 100, and the leg 123 on the semiconductor chip 200 side is provided on the X1 side in the X direction of the semiconductor chip 200. . Therefore, in such a configuration, the corner R portion 125 on the semiconductor chip 100 side is provided on the X2 side in the X direction of the semiconductor chip 100, so that the semiconductor chip 100 is in a dissolved state related to the upper solder layer 51A during the manufacturing process. The X2 side in the X direction tends to be pulled up by the surface tension of the solder. Therefore, as shown in FIG. 7, the WB bump 70A is provided only on the first side (X1 side) in the X direction in the lower solder layer 50A. Similarly, since the corner R portion 125 on the semiconductor chip 200 side is provided on the X1 side in the X direction of the semiconductor chip 200, the semiconductor chip 200 is subjected to the surface tension of the solder in the dissolved state of the upper solder layer 51B during the manufacturing process. The X1 side in the X direction tends to be pulled up. Therefore, as shown in FIG. 7, the WB bump 70B is provided only on the second side (X2 side) in the X direction in the lower solder layer 50B.

図７に示す半導体装置２によっても、図１等に示した半導体装置１と同様の効果を得ることができる。即ち、下半田層５０Ａ，５０Ｂにおける接続端子１２０の角Ｒ部１２５側とは反対側において、下半田層５０Ａ，５０Ｂの厚みが薄くなることがＷＢバンプ７０Ａ，７０Ｂによって防止されるので、下半田層５０Ａ，５０Ｂにおける熱応力に起因したクラックの発生を低減することができる。ＷＢバンプ７０Ａ，７０Ｂは、半導体チップ１００，２００の載置範囲Ｐ１、Ｐ２の一端側のみ（接続端子１２０の角Ｒ部１２５側とは反対側のみ）に設けられる。従って、ＷＢバンプ７０Ａ，７０Ｂの数を低減して、製造コストを低減することができる。   The semiconductor device 2 shown in FIG. 7 can also obtain the same effects as those of the semiconductor device 1 shown in FIG. That is, since the lower solder layers 50A and 50B are prevented from being thinned by the WB bumps 70A and 70B on the side opposite to the corner R portion 125 side of the connection terminal 120 in the lower solder layers 50A and 50B, the lower solder layers 50A and 50B The generation of cracks due to thermal stress in the layers 50A and 50B can be reduced. The WB bumps 70A and 70B are provided only on one end side of the mounting ranges P1 and P2 of the semiconductor chips 100 and 200 (only on the side opposite to the corner R portion 125 side of the connection terminal 120). Therefore, the number of WB bumps 70A and 70B can be reduced, and the manufacturing cost can be reduced.

図８は、更なる他の例による半導体装置３の概略断面図である。   FIG. 8 is a schematic cross-sectional view of a semiconductor device 3 according to still another example.

図８に示す半導体装置３は、図１等に示した半導体装置１に対して、接続端子１２が別体の２つの接続端子１２Ａ，１２Ｂで代替されている点が主に異なる。他の構成については、同様であってよい。   The semiconductor device 3 shown in FIG. 8 is mainly different from the semiconductor device 1 shown in FIG. 1 and the like in that the connection terminal 12 is replaced with two separate connection terminals 12A and 12B. Other configurations may be the same.

図８に示す例では、接続端子１２Ａは、側面視でＸ方向のＸ２側が開口するＣ字断面を有し、接続端子１２Ｂは、側面視でＸ方向のＸ１側が開口するＣ字断面を有する。但し、向きは任意であり、例えば、接続端子１２Ｂは、Ｘ方向のＸ２側が開口する向きで配置されてもよい。図８に示す例では、図１等に示した半導体装置１と同様に、半導体チップ１００側の接続端子１２Ａの脚部１２３Ａは、半導体チップ１００のＸ方向のＸ１側に設けられ、半導体チップ２００側の脚部１２３Ｂは、半導体チップ２００のＸ方向のＸ２側に設けられる。従って、図１等に示した半導体装置１と同様に、半導体チップ１００側の角Ｒ部１２５は、半導体チップ１００のＸ方向のＸ１側に設けられるので、製造工程中、半導体チップ１００は、上半田層５１Ａに係る溶解状態の半田の表面張力によりＸ方向のＸ１側が引っ張り上げられようとする。このため、ＷＢバンプ７０Ａは、図８に示すように、下半田層５０Ａ内におけるＸ方向の第２側（Ｘ２側）のみに設けられる。同様に、半導体チップ２００側の角Ｒ部１２５は、半導体チップ２００のＸ方向のＸ２側に設けられるので、製造工程中、半導体チップ２００は、上半田層５１Ｂの溶解状態の半田の表面張力によりＸ方向のＸ２側が引っ張り上げられようとする。このため、ＷＢバンプ７０Ｂは、図８に示すように、下半田層５０Ｂ内におけるＸ方向の第１側（Ｘ１側）のみに設けられる。   In the example shown in FIG. 8, the connection terminal 12A has a C-shaped cross section that opens on the X2 side in the X direction when viewed from the side, and the connection terminal 12B has a C-shaped cross section that opens on the X1 side in the X direction when viewed from the side. However, the orientation is arbitrary, and for example, the connection terminal 12B may be arranged in an orientation in which the X2 side in the X direction opens. In the example shown in FIG. 8, like the semiconductor device 1 shown in FIG. 1 and the like, the leg portion 123A of the connection terminal 12A on the semiconductor chip 100 side is provided on the X1 side of the semiconductor chip 100 in the X direction. The side leg portion 123B is provided on the X2 side of the semiconductor chip 200 in the X direction. Accordingly, similarly to the semiconductor device 1 shown in FIG. 1 and the like, the corner R portion 125 on the semiconductor chip 100 side is provided on the X1 side in the X direction of the semiconductor chip 100. The X1 side in the X direction tends to be pulled up by the surface tension of the melted solder related to the solder layer 51A. Therefore, as shown in FIG. 8, the WB bump 70A is provided only on the second side (X2 side) in the X direction in the lower solder layer 50A. Similarly, since the corner R portion 125 on the semiconductor chip 200 side is provided on the X2 side in the X direction of the semiconductor chip 200, during the manufacturing process, the semiconductor chip 200 is caused by the surface tension of the molten solder in the upper solder layer 51B. The X2 side in the X direction tends to be pulled up. For this reason, as shown in FIG. 8, the WB bump 70B is provided only on the first side (X1 side) in the X direction in the lower solder layer 50B.

図８に示す半導体装置３によっても、図１等に示した半導体装置１と同様の効果を得ることができる。即ち、下半田層５０Ａ，５０Ｂにおける接続端子１２Ａ，１２Ｂの角Ｒ部１２５側とは反対側において、下半田層５０Ａ，５０Ｂの厚みが薄くなることがＷＢバンプ７０Ａ，７０Ｂによって防止されるので、下半田層５０Ａ，５０Ｂにおける熱応力に起因したクラックの発生を低減することができる。ＷＢバンプ７０Ａ，７０Ｂは、半導体チップ１００，２００の載置範囲Ｐ１、Ｐ２の一端側のみ（接続端子１２Ａ，１２Ｂの角Ｒ部１２５側とは反対側のみ）に設けられる。従って、ＷＢバンプ７０Ａ，７０Ｂの数を低減して、製造コストを低減することができる。   Also by the semiconductor device 3 shown in FIG. 8, the same effect as the semiconductor device 1 shown in FIG. That is, since the lower solder layers 50A and 50B are prevented from being thinned by the WB bumps 70A and 70B on the side opposite to the corner R portion 125 side of the connection terminals 12A and 12B in the lower solder layers 50A and 50B, Generation of cracks due to thermal stress in the lower solder layers 50A and 50B can be reduced. The WB bumps 70A and 70B are provided only on one end side of the mounting ranges P1 and P2 of the semiconductor chips 100 and 200 (only on the side opposite to the corner R portion 125 side of the connection terminals 12A and 12B). Therefore, the number of WB bumps 70A and 70B can be reduced, and the manufacturing cost can be reduced.

以上、各実施例について詳述したが、特定の実施例に限定されるものではなく、特許請求の範囲に記載された範囲内において、種々の変形及び変更が可能である。また、前述した実施例の構成要素を全部又は複数を組み合わせることも可能である。   Although each embodiment has been described in detail above, it is not limited to a specific embodiment, and various modifications and changes can be made within the scope described in the claims. It is also possible to combine all or a plurality of the components of the above-described embodiments.

例えば、上述した実施例では、ＷＢバンプ７０Ａ，７０Ｂが、下半田層５０Ａ，５０Ｂの必要な厚みを維持する手段として設けられているが、ＷＢバンプ７０Ａ，７０Ｂ以外の構成が使用されてもよい。例えば、球状の突起（ニッケル等の金属材料から形成されるボール状の突起）等が使用されてもよい。また、ヒートスプレッダ２０に一体的に形成される突起が、ＷＢバンプ７０Ａ，７０Ｂに代えて使用されてもよい。   For example, in the above-described embodiment, the WB bumps 70A and 70B are provided as means for maintaining the necessary thickness of the lower solder layers 50A and 50B, but a configuration other than the WB bumps 70A and 70B may be used. . For example, spherical protrusions (ball-shaped protrusions formed from a metal material such as nickel) may be used. Further, protrusions formed integrally with the heat spreader 20 may be used in place of the WB bumps 70A and 70B.

また、上述した実施例では、下半田層５０Ａ，５０Ｂの形成前の状態で、ＷＢバンプ７０Ａ，７０Ｂは、ヒートスプレッダ２０側に接合されているが、半導体チップ１００，２００の下面側に接合されていてもよい。   In the above-described embodiment, the WB bumps 70A and 70B are bonded to the heat spreader 20 side before the lower solder layers 50A and 50B are formed, but are bonded to the lower surfaces of the semiconductor chips 100 and 200. May be.

また、上述した実施例では、好ましい実施例として、ＷＢバンプ７０Ａ，７０Ｂの双方が設けられているが、いずれか一方が省略されてもよい。   In the embodiment described above, both WB bumps 70A and 70B are provided as a preferred embodiment, but either one may be omitted.

また、上述の実施例では、半導体チップ１００，２００が下半田層５０Ａ，５０Ｂを介して接合される基板は、ヒートスプレッダ２０であったが、半導体チップ１００，２００は、他の任意の基板に配置されてもよい。例えば、半導体チップ１００，２００が下半田層５０Ａ，５０Ｂを介して接合される基板は、セラミック基板の両面にアルミ板を備えたＤＢＡ（Direct Brazed Aluminum）基板や、セラミック基板の両面に銅板を備えたＤＢＣ（Direct Brazed Copper）基板であってもよい。   In the above-described embodiment, the substrate to which the semiconductor chips 100, 200 are bonded via the lower solder layers 50A, 50B is the heat spreader 20, but the semiconductor chips 100, 200 are arranged on any other substrate. May be. For example, a substrate to which the semiconductor chips 100 and 200 are bonded via the lower solder layers 50A and 50B includes a DBA (Direct Brazed Aluminum) substrate having an aluminum plate on both sides of the ceramic substrate, and a copper plate on both sides of the ceramic substrate. A DBC (Direct Brazed Copper) substrate may also be used.

また、上述の実施例では、接続端子１２は、Ｙ方向で一定の幅を有しているが、接続端子１２の幅は変化してもよい。また、上述の実施例では、脚部１２３は、ヒートスプレッダ２０の上面に対して垂直に延在するが、垂直以外の角度であってもよい。   Moreover, in the above-mentioned Example, although the connection terminal 12 has a fixed width | variety in a Y direction, the width | variety of the connection terminal 12 may change. In the above-described embodiment, the leg portion 123 extends perpendicularly to the upper surface of the heat spreader 20, but may have an angle other than vertical.

また、上述の実施例では、鑞材として半田が用いられているが、半田に代えて種々の鑞材（例えば、金、銀、銅等を含むもの。硬鑞であるか軟鑞であるかを問わない）を採用することが可能である。さらに、鑞材は、合金からなる材料に限られるものではなく、加熱により液化し冷却（自然冷却を含む）により固化して接合を実現するあらゆる導電性材料を鑞材として採用することが可能である。また、半田としては、主成分として含まれる金属の種類（例えば、錫等）によらず種々の半田を採用することができる。   In the above-described embodiments, solder is used as the brazing material, but various brazing materials (for example, those containing gold, silver, copper, etc.) are used instead of solder. Can be employed). Furthermore, the brazing material is not limited to an alloy material, and any conductive material that can be liquefied by heating and solidified by cooling (including natural cooling) to achieve bonding can be used as the brazing material. is there. As the solder, various solders can be employed regardless of the type of metal (for example, tin) contained as the main component.

また、図示の例では、ヒートスプレッダ２０単位で構成を説明したが、半導体装置１（半導体装置２、３についても同様、以下同じ）に含まれるヒートスプレッダ２０の数は任意である。例えば、半導体装置１に含まれるヒートスプレッダ２０の数は、６であってもよい。この場合、６つのヒートスプレッダ２０上の各半導体チップ１００、２００は、モータ駆動用のインバータのＵ相、Ｖ相、Ｗ相の各上アーム及び各下アームを構成するものであってよい。   In the illustrated example, the configuration is described in units of the heat spreader 20, but the number of the heat spreaders 20 included in the semiconductor device 1 (the same applies to the semiconductor devices 2 and 3 below) is arbitrary. For example, the number of heat spreaders 20 included in the semiconductor device 1 may be six. In this case, the semiconductor chips 100 and 200 on the six heat spreaders 20 may constitute the U-phase, V-phase, and W-phase upper and lower arms of the motor drive inverter.

また、上述の実施例では、半導体チップ１００、２００が１対でモータ駆動用のインバータのＵ相、Ｖ相、Ｗ相の各上アーム及び各下アームのうちの１つのアームを形成しているが、半導体チップ１００、２００が２対以上で１つのアームを形成してもよい。即ち、半導体チップ１００、２００は、２対以上で並列に接続されてもよい。この場合、例えば、図１及び図２等に示す半導体装置１においては、半導体チップ１００、２００はＹ方向で並設されてよく、これに伴い、接続端子１２がＹ方向で並設されてよい。この際、Ｙ方向で並設される２つの接続端子１２は、一体の１つの接続端子により実現されてもよい。   In the above-described embodiment, the semiconductor chips 100 and 200 form a pair of U-phase, V-phase, and W-phase upper arms and lower arms of the motor driving inverter. However, two arms or more of the semiconductor chips 100 and 200 may form one arm. That is, the semiconductor chips 100 and 200 may be connected in parallel in two or more pairs. In this case, for example, in the semiconductor device 1 shown in FIGS. 1 and 2, the semiconductor chips 100 and 200 may be arranged in the Y direction, and accordingly, the connection terminals 12 may be arranged in the Y direction. . At this time, the two connection terminals 12 arranged in parallel in the Y direction may be realized by an integral connection terminal.

また、上述の実施例では、接続端子１２（接続端子１２Ａ，１２Ｂ，１２０も同様）は、バスバー８０に直接接続されているが、ワイヤボンディング等を介して接続されてもよい。   In the above-described embodiment, the connection terminal 12 (the same applies to the connection terminals 12A, 12B, and 120) is directly connected to the bus bar 80, but may be connected via wire bonding or the like.

また、上述の実施例では、半導体装置１は、車両用のインバータに適用されるものであったが、半導体装置１は、他の用途（鉄道、エアコン、エレベータ、冷蔵庫等）で使用されるインバータに使用されてもよい。更に、半導体装置１は、インバータ以外の装置、例えば、コンバータや、無線通信機の送信部の電力増幅回路に使用される高周波パワーモジュールに使用されてもよい。   In the above-described embodiment, the semiconductor device 1 is applied to a vehicle inverter. However, the semiconductor device 1 is an inverter used for other purposes (railway, air conditioner, elevator, refrigerator, etc.). May be used. Furthermore, the semiconductor device 1 may be used in a device other than an inverter, for example, a converter or a high-frequency power module used in a power amplification circuit of a transmission unit of a wireless communication device.

１，２，３ 半導体装置
１２，１２Ａ，１２Ｂ，１２０ 接続端子
２０ ヒートスプレッダ
５０Ａ，５０Ｂ 下半田層
５１Ａ，５１Ｂ 上半田層
７０Ａ，７０Ｂ ＷＢバンプ
８０ バスバー
１００，２００ 半導体チップ
１０２，２０２ 表面電極
１２１ 上部
１２２ 接続部
１２３，１２３Ａ，１２３Ｂ 脚部
１２５ 角Ｒ部 1, 2, 3 Semiconductor device 12, 12A, 12B, 120 Connection terminal 20 Heat spreader 50A, 50B Lower solder layer 51A, 51B Upper solder layer 70A, 70B WB bump 80 Bus bar 100, 200 Semiconductor chip 102, 202 Surface electrode 121 Upper 122 Connection part 123, 123A, 123B Leg part 125 Angle R part

Claims (6)

基板と、
前記基板上に形成される第１鑞材層と、
前記基板上に前記第１鑞材層を介して接合される半導体素子と、
前記半導体素子における前記第１鑞材層側とは逆側の表面電極上に形成される第２鑞材層と、
前記半導体素子の表面電極に前記第２鑞材層を介して接合される接続部、及び、前記接続部における所定方向の第１側の端部から屈曲して立ち上がる脚部を備える接続端子と、
前記第１鑞材層内における前記所定方向の第１側及びその反対側である第２側のうちの、前記第２側のみに設けられる鑞材層厚維持手段とを含む、半導体装置。 A substrate,
A first brazing material layer formed on the substrate;
A semiconductor element bonded to the substrate via the first brazing material layer;
A second brazing material layer formed on the surface electrode opposite to the first brazing material layer side in the semiconductor element;
A connection terminal having a connection portion joined to the surface electrode of the semiconductor element via the second brazing material layer, and a leg portion that bends and rises from an end portion on the first side in a predetermined direction in the connection portion;
A semiconductor device comprising: a first material layer thickness maintaining means provided only on the second side of the first side in the first direction and the second side opposite to the first side in the predetermined direction. 前記接続端子に直接接続されるバスバーを備える、請求項１に記載の半導体装置。   The semiconductor device according to claim 1, further comprising a bus bar directly connected to the connection terminal. 前記半導体素子は、スイッチング素子であり、
前記基板上に形成される第３鑞材層と、
前記基板上に前記第３鑞材層を介して接合されるフリーホイールダイオードであって、前記スイッチング素子と電気的に接続されるフリーホイールダイオードと、
前記フリーホイールダイオードにおける前記第３鑞材層側とは逆側の表面電極上に形成される第４鑞材層と、
前記接続端子と一体に形成され、前記フリーホイールダイオードの表面電極に前記第４鑞材層を介して接合される第２接続部と、
前記接続端子と一体に形成され、前記第２接続部における前記所定方向の第２側の端部から屈曲して立ち上がる第２脚部と、
前記第３鑞材層内における前記所定方向の第１側及び第２側のうちの、前記第１側のみに設けられる第２鑞材層厚維持手段とを更に含む、請求項１又は２に記載の半導体装置。 The semiconductor element is a switching element,
A third brazing material layer formed on the substrate;
A freewheeling diode joined to the substrate via the third brazing material layer, the freewheeling diode electrically connected to the switching element;
A fourth brazing material layer formed on the surface electrode opposite to the third brazing material layer side in the freewheel diode;
A second connection part formed integrally with the connection terminal and joined to the surface electrode of the freewheel diode via the fourth brazing material layer;
A second leg formed integrally with the connection terminal, and bent and raised from an end of the second connection portion on the second side in the predetermined direction;
The second brazing material layer thickness maintaining means provided only on the first side of the first side and the second side in the predetermined direction in the third brazing material layer, further comprising: The semiconductor device described. 前記鑞材層厚維持手段は、前記基板上にワイヤボンディングにより形成される突起であり、前記突起は、前記第１鑞材層の材料に対する熱膨張係数の差が所定基準よりも小さい材料から形成される、請求項１〜３のうちのいずれか１項に記載の半導体装置。   The brazing material layer thickness maintaining means is a protrusion formed on the substrate by wire bonding, and the protrusion is formed of a material having a difference in thermal expansion coefficient with respect to the material of the first brazing material layer being smaller than a predetermined reference. The semiconductor device according to any one of claims 1 to 3. 前記鑞材層厚維持手段は、前記第２側に２箇所設けられ、２つの前記鑞材層厚維持手段は、前記第２側の方が間隔が広くなる態様でハの字状に延在する、請求項１〜４のうちのいずれか１項に記載の半導体装置。   The brazing material layer thickness maintaining means is provided at two locations on the second side, and the two brazing material layer thickness maintaining means extend in a letter C shape in such a manner that the interval on the second side is wider. The semiconductor device according to any one of claims 1 to 4. 基板上に鑞材層厚維持手段を接合し、
前記鑞材層厚維持手段を所定方向の第２側のみに内包する態様で前記基板上に溶融状態の第１鑞材を付与し、
前記溶融状態の第１鑞材上に半導体素子を載置し、
前記半導体素子における前記第１鑞材側とは逆側の表面電極に溶融状態の第２鑞材を付与し、
前記第１鑞材が溶融状態にある間に、前記溶融状態の第２鑞材上に接続端子であって、接続部、及び、前記接続部における前記所定方向の第１側の端部から屈曲して立ち上がる脚部を備える接続端子を、前記接続部が前記第２鑞材上に来る態様で載置することを含む、半導体装置の製造方法。 Join the brazing material layer thickness maintenance means on the substrate,
Providing the first brazing material in a molten state on the substrate in a mode of including the brazing material layer thickness maintaining means only on the second side in a predetermined direction;
A semiconductor element is placed on the first brazing material in the molten state,
Providing a second brazing material in a molten state on the surface electrode opposite to the first brazing material side in the semiconductor element;
While the first brazing material is in a molten state, a connection terminal is provided on the second brazing material in the molten state, and is bent from the connection portion and an end portion on the first side in the predetermined direction in the connection portion. And mounting a connection terminal having a leg portion that rises in such a manner that the connection portion comes on the second saddle member.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107572080A (en) * 2017-09-12 2018-01-12 宿州德源服装有限公司 A kind of clothes case and bag logo indicates installation equipment
CN107649614A (en) * 2017-09-12 2018-02-02 宿州德源服装有限公司 A kind of case and bag logo indicates installation operation platform
JPWO2020235056A1 (en) * 2019-05-22 2020-11-26

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107572080A (en) * 2017-09-12 2018-01-12 宿州德源服装有限公司 A kind of clothes case and bag logo indicates installation equipment
CN107649614A (en) * 2017-09-12 2018-02-02 宿州德源服装有限公司 A kind of case and bag logo indicates installation operation platform
JPWO2020235056A1 (en) * 2019-05-22 2020-11-26
WO2020235056A1 (en) * 2019-05-22 2020-11-26 三菱電機株式会社 Semiconductor device, power conversion device, and method for manufacturing semiconductor device
JP7101882B2 (en) 2019-05-22 2022-07-15 三菱電機株式会社 Manufacturing method of semiconductor device, power conversion device and semiconductor device

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