JP3377553B2 - Semiconductor laser device - Google Patents
Semiconductor laser deviceInfo
- Publication number
- JP3377553B2 JP3377553B2 JP11146693A JP11146693A JP3377553B2 JP 3377553 B2 JP3377553 B2 JP 3377553B2 JP 11146693 A JP11146693 A JP 11146693A JP 11146693 A JP11146693 A JP 11146693A JP 3377553 B2 JP3377553 B2 JP 3377553B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- solder
- submount
- semiconductor laser
- barrier metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83194—Lateral distribution of the layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Lasers (AREA)
- Die Bonding (AREA)
- Led Device Packages (AREA)
Abstract
Description
【発明の詳細な説明】
【0001】
【産業上の利用分野】この発明は、半導体レーザ装置に
関し、特に、光半導体素子の実装に使用する光半導体用
サブマウントを備えたものに関するものである。
【0002】
【従来の技術】図3は従来の半導体レーザ素子のダイボ
ンドしたサブマウントの断面図である。図において、1
はレーザチップ、2はレーザチップ1の接着面に設けら
れた表面メタライズ、3はレーザチップ1のレーザ光の
発せられる発光点、4は上記レーザチップ1を実装する
ためのサブマウント、5は上記サブマウント4を搭載す
る金属ブロック、6は上記レーザチップ1をサブマウン
ト4に接着するための半田である。
【0003】次に組立方法について説明する。図3にお
いて、レーザチップ1はレーザチップの表面メタライズ
2の上に図示しない接着用の半田メタライズを有してお
り、レーザの組立では、一般的に放熱の良い金属ブロッ
ク5にサブマウント4を介して半田6を用いてチップ1
が接着される。さらにODD(光磁気ディスクドライ
バ)やプリンタに使用する場合には、低熱抵抗や低熱特
性を得るために、発光点3をサブマウント4に近づけて
組立てを行なうJ/D(ジャンクションダウン)組立が
必要不可欠である。この場合、ダイボンド中の半田6が
チップ1とサブマウント4との間で溶融し、チップ1の
周辺部まで広がって最終的に固着するが、発光点3が接
着面(ダイボンド面)から約数μmの位置にあるため、
固着した半田6がチップ1のサイドに露出したP−Nジ
ャンクションに接触することがある。
【0004】
【発明が解決しようとする課題】従来の光半導体素子用
サブマウントを備えた半導体レーザ装置は以上のように
構成されているので、ダイボンドの際にサブマウントの
表面にはみ出した半田が発光点近傍のチップサイドに露
出したジャンクション部に接触し、初期ショート不良と
なって歩留低下が発生したり、また初期不良となること
を避けられたとしてもユーザの使用中に、マイクロ放電
現象によって半田がジャンクション部に間欠的に接触す
るショート不具合となることがあるという問題点があっ
た。
【0005】この発明は上記のような問題点を解消する
ためになされたもので、ダイボンド時の半田が、チップ
サイドに露出したジャンクション部に接触してショート
不良となるのを防止し、歩留が高く、かつ耐環境性試験
においても特性変動が少なく、信頼性の高い半導体レー
ザ装置を得ることを目的とする。
【0006】
【課題を解決するための手段】この発明に係る半導体レ
ーザ装置は、放熱用金属ブロック上にはんだ層を介して
配設されたサブマウントと、このサブマウント上に配設
され、上記サブマウント側から順に、第1層のTi層、
第2層のNi層またはPt層、第3層のAu層より形成
されたバリヤメタル層と、このバリヤメタル層上に配設
されるとともに、活性層を挟んで互いに対向する主面を
有し、この主面のうち活性層に近接した一主面を上記バ
リヤメタル層に対向した半導体レーザチップと、この半
導体レーザチップと上記バリヤメタル層との間に介在
し、上記半導体レーザチップに対応した広さに配設され
るとともに上記半導体レーザチップ側面から上記バリヤ
メタル層に向かって膜厚が滑らかに減少した、Snの純
度が99.9999%以上の材料を用いて蒸着又はスパ
ッタにより形成されたAuSnからなる共晶はんだ層と
を備えたものである。
【0007】
【作用】この発明においては、サブマウントのレーザチ
ップと接触する側に形成された共晶半田がチップサイズ
相当の大きさに限定されて形成されているために、ダイ
ボンドした際の半田がチップサイドに大きくはみ出して
ジャンクション部に接触することが抑制されるととも
に、はみ出したとしても共晶半田により形成されている
ため、バリヤ層と十分に馴染んで、表面状態の良好な半
田フィレットが形成され、ジャンクション部と接触する
ことは殆どなくなる。
【0008】
【実施例】実施例1.
以下、この発明の実施例による半導体レーザ装置の光半
導体素子用サブマウントを図について説明する。図1に
おいて、40はシリコン、又はシリコンカーバイト、又
は窒化アルミニウムより構成されたサブマウントを示
し、該サブマウント40を構成するサブマウント基体1
0の両面にそれぞれ、第1層Ti層71,第2層Ni層
又はPt層72,第3層Au層73よりなるバリヤメタ
ル7a,7bが形成され、さらに一方のバリヤメタル7
aの表面にレーザチップ1のサイズに相当する大きさの
AuSn半田層(Sn wt%=20〜40%)8が設
けられ、他方のバリヤメタル7bの表面にAuSn半田
層9が形成されている。また、図2は上記サブマウント
40を用いてレーザチップをダイボンドしたときの様子
を示す断面図であり、図3と同一符号は同一または相当
部分を示す。
【0009】次に作用,効果について説明する。サブマ
ウント基体10のバリヤメタル7aが形成された面には
レーザチップ1のサイズに相当するAuSn半田層8が
蒸着又はスパッタにより形成され、サブマウント基体1
0のバリヤメタル7bが形成された面には全面にAuS
n半田層9が蒸着又はスパッタにより形成されている。
この場合、蒸着源又はスパッタ源としてSnの純度が6
N(99.9999%)以上のものを使用することで、
ダイボンド時の半田溶融において、下地のバリヤ層7a
の最表面層であるAu層73と十分に馴染むようにな
り、表面形状が滑らかなAuSn共晶半田層が形成され
るようになる。このようなサブマウント40を用いて図
2に示すように、J/D(ジャンクションダウン)組立
を行なった場合、レーザチップ1のサイドへはみ出す半
田8は十分に抑えられ、はみ出した場合においても、ジ
ャンクション部への半田ショートは殆どなくなる。ま
た、ヒートサイクル,高温保存等の環境試験において
も、レーザの特性変動の少ない信頼性の高いレーザ装置
が得られる。
【0010】
【発明の効果】以上のように、この発明に係る半導体レ
ーザ装置によれば、サブマウント基体の両面にバリヤ層
を設け、さらにその上に前記基体の主面側にレーザチッ
プのサイズ相当の大きさの、Snの純度が99.999
9%以上の材料を用いて蒸着又はスパッタにより形成さ
れたAuSnからなる共晶半田層を設け、かつ上記基体
の裏面側全面に共晶半田層を形成したので、ダイボンド
の際にチップサイドにはみ出す半田の量を十分に抑制で
き、チップサイドへ露出したジャンクション部への半田
ショートを十分に抑えて歩留を向上させることができる
とともに、ヒートサイクル,高温保存等の環境試験にお
いても、半田の影響を殆ど受けず、特性変動の少ない信
頼性の高い半導体レーザ装置が得られるという効果があ
る。Description: BACKGROUND OF THE INVENTION The present invention relates to a semiconductor laser device.
Relates, in particular, those which relate to those with sub-mount for an optical semiconductor used to implement the optical semiconductor element. FIG. 3 is a cross-sectional view of a die-bonded submount of a conventional semiconductor laser device. In the figure, 1
Is a laser chip, 2 is a surface metallization provided on the bonding surface of the laser chip 1, 3 is a light emitting point of the laser chip 1 at which laser light is emitted, 4 is a submount for mounting the laser chip 1, and 5 is the above. A metal block 6 on which the submount 4 is mounted is a solder for bonding the laser chip 1 to the submount 4. Next, an assembling method will be described. In FIG. 3, a laser chip 1 has a solder metallization for bonding (not shown) on a surface metallization 2 of the laser chip. In assembling a laser, generally, a metal block 5 having good heat radiation is provided via a submount 4. Chip 1 using solder 6
Are adhered. Further, when used in an ODD (magneto-optical disk driver) or a printer, a J / D (junction down) assembly is required in which the light emitting point 3 is assembled close to the submount 4 in order to obtain low thermal resistance and low thermal characteristics. It is essential. In this case, the solder 6 in the die bond melts between the chip 1 and the submount 4 and spreads to the peripheral portion of the chip 1 to be finally fixed. μm
The fixed solder 6 may come into contact with the PN junction exposed on the side of the chip 1. [0004] Since the conventional semiconductor laser device having the submount for an optical semiconductor element is configured as described above, the solder that has protruded to the surface of the submount during die bonding is removed. Contact with the junction exposed on the chip side near the light emitting point, causing an initial short-circuit failure and a reduction in yield, and even if the initial failure can be avoided, the micro-discharge phenomenon occurs during user use. Therefore, there is a problem that a short circuit may occur in which the solder intermittently contacts the junction. SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and prevents a solder at the time of die bonding from coming into contact with a junction exposed on the chip side to cause a short-circuit failure, thereby reducing the yield. is high and the characteristics vary in environmental resistance test is small, and an object that you obtain a highly reliable semiconductor laser device. [0006] A semiconductor laser device according to the present invention includes a submount provided on a heat-dissipating metal block via a solder layer, and a submount provided on the submount. In order from the submount side, a first Ti layer,
A barrier metal layer formed of a second layer of Ni or Pt and a third layer of Au, and a main surface disposed on the barrier metal layer and opposed to each other across the active layer; One main surface of the main surface close to the active layer is interposed between the semiconductor laser chip facing the barrier metal layer and the semiconductor laser chip and the barrier metal layer, and is arranged in a width corresponding to the semiconductor laser chip. The thickness of the Sn laser chip is reduced smoothly from the side of the semiconductor laser chip toward the barrier metal layer.
Deposition or spa using a material with a degree of 99.9999% or more
And a eutectic solder layer made of AuSn formed by a cutter . In the present invention, since the eutectic solder formed on the side of the submount that contacts the laser chip is limited to a size corresponding to the chip size, the solder at the time of die bonding is formed. , Which protrudes greatly to the chip side and comes into contact with the junction part, and even if it does, it is formed of eutectic solder, so it fits well with the barrier layer and forms a solder fillet with good surface condition And almost no contact with the junction. [0008] [Embodiment 1]. Hereinafter, a submount for an optical semiconductor element of a semiconductor laser device according to an embodiment of the present invention will be described with reference to the drawings. In FIG. 1, reference numeral 40 denotes a submount made of silicon, silicon carbide, or aluminum nitride, and a submount base 1 constituting the submount 40.
The barrier metal layers 7a and 7b each including a first layer Ti layer 71, a second layer Ni layer or a Pt layer 72, and a third layer Au layer 73 are formed on both surfaces of the first barrier metal layer 7, respectively.
An AuSn solder layer (Sn wt% = 20 to 40%) 8 having a size corresponding to the size of the laser chip 1 is provided on the surface of a, and an AuSn solder layer 9 is formed on the surface of the other barrier metal 7b. FIG. 2 is a cross-sectional view showing a state where a laser chip is die-bonded using the submount 40. The same reference numerals as those in FIG. 3 denote the same or corresponding parts. Next, the operation and effect will be described. An AuSn solder layer 8 corresponding to the size of the laser chip 1 is formed on the surface of the submount substrate 10 on which the barrier metal 7a is formed by vapor deposition or sputtering.
AuS is entirely formed on the surface on which the barrier metal 7b is formed.
The n solder layer 9 is formed by vapor deposition or sputtering.
In this case, the purity of Sn is 6 as an evaporation source or a sputtering source.
By using more than N (99.9999%),
In solder melting at the time of die bonding, the underlying barrier layer 7a
And the AuSn eutectic solder layer having a smooth surface shape is formed. As shown in FIG. 2, when the J / D (junction down) assembly is performed using such a submount 40, the solder 8 protruding to the side of the laser chip 1 is sufficiently suppressed. There is almost no solder short to the junction. Further, even in an environmental test such as a heat cycle or high-temperature storage, a highly reliable laser device with little fluctuation in laser characteristics can be obtained. As described above, according to the semiconductor laser device of the present invention, the barrier layers are provided on both surfaces of the submount substrate, and the size of the laser chip is further provided on the main surface side of the substrate. Considerable size, the purity of Sn is 99.999.
Formed by vapor deposition or sputtering using a material of 9% or more
Since the eutectic solder layer made of AuSn is provided and the eutectic solder layer is formed on the entire back surface of the substrate, the amount of solder that protrudes to the chip side during die bonding can be sufficiently suppressed, and the exposure to the chip side can be achieved. In addition to being able to improve the yield by sufficiently suppressing the short-circuit of the solder to the junction, the solder is hardly affected by environmental tests such as heat cycle and high-temperature storage, and has high reliability with little characteristic fluctuation. There is an effect that a semiconductor laser device can be obtained.
【図面の簡単な説明】
【図1】この発明の実施例による半導体レーザ装置の光
半導体素子用サブマウントの断面図。
【図2】上記サブマウントを用いて半導体レーザ素子を
実装した場合の装置断面図。
【図3】従来の半導体レーザ素子をダイボンドしたとき
の様子を示す装置断面図。
【符号の説明】
1 レーザチップ
2 表面メタライズ
3 発光点
4 サブマウント
5 金属ブロック
7a バリヤメタル
7b バリヤメタル
8 部分AuSn半田層
9 全面AuSn半田層
10 サブマウント基体BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view of a submount for an optical semiconductor element of a semiconductor laser device according to an embodiment of the present invention. FIG. 2 is an apparatus cross-sectional view when a semiconductor laser element is mounted using the submount. FIG. 3 is an apparatus cross-sectional view showing a state when a conventional semiconductor laser device is die-bonded. [Description of Signs] 1 Laser chip 2 Surface metallization 3 Light emitting point 4 Submount 5 Metal block 7a Barrier metal 7b Barrier metal 8 Partial AuSn solder layer 9 Full AuSn solder layer 10 Submount base
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01L 23/12 H01L 21/52 H01L 33/00 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 23/12 H01L 21/52 H01L 33/00
Claims (1)
て配設されたサブマウントと、 このサブマウント上に配設され、上記サブマウント側か
ら順に、第1層のTi層、第2層のNi層またはPt
層、第3層のAu層より形成されたバリヤメタル層と、 このバリヤメタル層上に配設されるとともに、活性層を
挟んで互いに対向する主面を有し、この主面のうち活性
層に近接した一主面を上記バリヤメタル層に対向した半
導体レーザチップと、 この半導体レーザチップと上記バリヤメタル層との間に
介在し、上記半導体レーザチップに対応した広さに配設
されるとともに上記半導体レーザチップ側面から上記バ
リヤメタル層に向かって膜厚が滑らかに減少した、Sn
の純度が99.9999%以上の材料を用いて蒸着又は
スパッタにより形成されたAuSnからなる共晶はんだ
層と、 を備えたことを特徴とする半導体レーザ装置。(57) [Claims] [Claim 1] A submount disposed on a heat-dissipating metal block via a solder layer, and a submount disposed on the submount and arranged in order from the submount side. One Ti layer, second Ni layer or Pt
A barrier metal layer formed of an Au layer as a third layer, and a main surface disposed on the barrier metal layer and facing each other with the active layer interposed therebetween. A semiconductor laser chip having one main surface facing the barrier metal layer, a semiconductor laser chip interposed between the semiconductor laser chip and the barrier metal layer, arranged in a width corresponding to the semiconductor laser chip, and The film thickness decreased smoothly from the side toward the barrier metal layer, Sn
Using a material having a purity of 99.9999% or more
And a eutectic solder layer made of AuSn formed by sputtering .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11146693A JP3377553B2 (en) | 1993-05-13 | 1993-05-13 | Semiconductor laser device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11146693A JP3377553B2 (en) | 1993-05-13 | 1993-05-13 | Semiconductor laser device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH06326210A JPH06326210A (en) | 1994-11-25 |
JP3377553B2 true JP3377553B2 (en) | 2003-02-17 |
Family
ID=14561963
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11146693A Expired - Fee Related JP3377553B2 (en) | 1993-05-13 | 1993-05-13 | Semiconductor laser device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3377553B2 (en) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19730118B4 (en) | 1997-07-14 | 2006-01-12 | Infineon Technologies Ag | Method and device for producing a chip-substrate connection |
JP2001156379A (en) | 1999-11-29 | 2001-06-08 | Canon Inc | Semiconductor laser array and optical scanner |
JP3509809B2 (en) * | 2002-04-30 | 2004-03-22 | 住友電気工業株式会社 | Submount and semiconductor device |
KR20040023451A (en) * | 2002-09-11 | 2004-03-18 | (주)솔로스세미콘 | The LED chip structure for applying Porous Silicone Wafer And the manufacturing method |
KR20040025181A (en) * | 2002-09-18 | 2004-03-24 | 엘지이노텍 주식회사 | Dielectric submount for laser diode |
US7745832B2 (en) * | 2004-09-24 | 2010-06-29 | Epistar Corporation | Semiconductor light-emitting element assembly with a composite substrate |
US7795732B2 (en) | 2005-02-07 | 2010-09-14 | Kabushiki Kaisha Toshiba | Ceramic wiring board and process for producing the same, and semiconductor device using the same |
JP2006332435A (en) * | 2005-05-27 | 2006-12-07 | Sharp Corp | Sub-mount, semiconductor laser device, manufacturing method thereof, hologram laser device, and optical pickup device |
KR20060131327A (en) | 2005-06-16 | 2006-12-20 | 엘지전자 주식회사 | Method of manufacturing light emitting diode |
JP4804190B2 (en) * | 2006-03-29 | 2011-11-02 | 京セラ株式会社 | Wiring board |
-
1993
- 1993-05-13 JP JP11146693A patent/JP3377553B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH06326210A (en) | 1994-11-25 |
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