CN110867432A - Chip packaging structure and packaging method - Google Patents
Chip packaging structure and packaging method Download PDFInfo
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- CN110867432A CN110867432A CN201911195017.6A CN201911195017A CN110867432A CN 110867432 A CN110867432 A CN 110867432A CN 201911195017 A CN201911195017 A CN 201911195017A CN 110867432 A CN110867432 A CN 110867432A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
Abstract
The embodiment of the invention discloses a chip packaging structure and a packaging method, wherein the packaging structure comprises the following components: the wafer is provided with a first surface and a second surface opposite to the first surface, the wafer comprises a plurality of chip units, the first surface is provided with a plurality of metal gaskets, and the metal gaskets are electrically connected with the chip units; the wafer comprises at least one Y-shaped through hole, the Y-shaped through hole comprises a T-shaped hole and a straight hole which are communicated, and part or all of the metal gasket is exposed out of the straight hole. According to the technical scheme provided by the embodiment of the invention, the gradient of the side wall of the T-shaped hole is more gentle, and the insulating layer with the preset thickness is easier to form on the Y-shaped through hole subsequently, so that the electric signal of the chip unit of the chip packaging structure can be transmitted to the metal welding ball through the wiring layer.
Description
Technical Field
The embodiment of the invention relates to the technical field of semiconductor manufacturing, in particular to a chip packaging structure and a chip packaging method.
Background
When a chip is packaged by the existing wafer level packaging technology, a technology is generally used for circuit interconnection, that is, a hole is formed on one surface of a wafer and a wiring process is performed, so that an electric signal of a chip unit is transmitted to a metal solder ball through a wiring layer.
However, in the chip packaging structure completed by the technology, the electric signals of the chip units of the chip packaging structure cannot be well transmitted to the metal solder balls through the wiring layer.
Disclosure of Invention
In view of this, embodiments of the present invention provide a chip packaging structure and a packaging method, which solve the technical problem in the prior art that electrical signals of chip units of the chip packaging structure cannot be well transmitted to metal solder balls through a wiring layer.
In a first aspect, an embodiment of the present invention provides a chip packaging structure, including:
the wafer is provided with a first surface and a second surface opposite to the first surface, the wafer contains a plurality of chip units, the first surface is provided with a plurality of metal gaskets, and the metal gaskets are electrically connected with the chip units;
the wafer comprises at least one Y-shaped through hole, the Y-shaped through hole comprises a T-shaped hole and a straight hole which are communicated, and part or all of the metal gasket is exposed by the straight hole.
Optionally, the slope of the sidewall of the T-shaped hole is greater than or equal to 58 degrees.
Optionally, the slope of the sidewall of the T-shaped hole is less than or equal to 61 degrees.
Optionally, the depth of the straight hole is greater than or equal to 35 microns.
Optionally, the depth of the straight holes is less than or equal to 55 microns.
Optionally, the wafer connects the surfaces of two adjacent Y-shaped through holes to be parallel to the first surface, and the minimum distance between any two adjacent Y-shaped through holes is greater than or equal to 16 micrometers.
Optionally, the distance between the central axes of any two adjacent straight holes is greater than or equal to 117 micrometers.
Optionally, the device further comprises a first insulating layer covering the sidewall of the Y-shaped via and the second surface.
Optionally, the wafer further comprises a wiring layer, located on a surface of the first insulating layer on a side away from the wafer, and electrically connected to the metal pad.
Optionally, the wafer further includes at least one metal solder ball, which is located on the surface of the wiring layer away from the first insulating layer and covering the second surface of the wafer, and is electrically connected to the wiring layer.
Optionally, the semiconductor device further includes a second insulating layer, where the second insulating layer includes at least one opening structure, the second insulating layer covers the wiring layer, and each opening structure exposes one of the metal solder balls.
Optionally, the thickness of the first insulating layer is greater than or equal to 3 microns.
Optionally, the first insulating layer comprises an organic insulating material.
Optionally, the second insulating layer comprises a solder resist layer.
In a second aspect, an embodiment of the present invention provides a chip packaging method, including:
providing a wafer, wherein the wafer is provided with a first surface and a second surface opposite to the first surface, a plurality of chip units are contained in the wafer, a plurality of metal gaskets are arranged on the second surface, and the metal gaskets are electrically connected with the chip units;
and forming at least one Y-shaped through hole on the wafer, wherein the Y-shaped through hole comprises a T-shaped hole and a straight hole which are communicated, and part or all of the metal gasket is exposed by the straight hole.
Optionally, forming at least one Y-shaped via in the wafer, where the Y-shaped via includes a T-shaped hole and a straight hole that are communicated with each other, and the straight hole exposes part or all of the metal pad and includes:
forming a T-shaped hole on the wafer by adopting a dry etching process;
and forming a straight hole communicated with the T-shaped hole by adopting a dry etching process, wherein part or all of the metal gasket is exposed by the straight hole.
Optionally, after the wafer forms at least one Y-shaped via, the method further includes:
and forming a first insulating layer on the side wall of the Y-shaped through hole and the second surface.
Optionally, after forming the first insulating layer on the sidewall of the Y-shaped via and the second surface, the method further includes:
and a wiring layer is formed on the surface of one side, away from the wafer, of the first insulating layer and is electrically connected with the metal gasket.
Optionally, a wiring layer is formed on a surface of the first insulating layer on a side away from the wafer, and after being electrically connected to the metal pad, the method further includes:
and forming at least one metal solder ball on the surface of the wiring layer, which is far away from the first insulating layer and covers the second surface of the wafer, and electrically connecting the metal solder ball with the wiring layer.
Optionally, at least one metal solder ball is formed on a surface of the wiring layer away from the first insulating layer, the surface covering the second surface of the wafer, and before the metal solder ball is electrically connected to the wiring layer, the method further includes:
forming a second insulating layer on the surface of the wiring layer, which is far away from one side of the first insulating layer, wherein the second insulating layer comprises an opening structure;
and forming a metal solder ball in the opening structure.
In the technical scheme provided by the embodiment, the wafer comprises at least one Y-shaped through hole, the Y-shaped through hole comprises a T-shaped hole and a straight hole which are communicated, part or all of the metal gasket is exposed in the straight hole, the metal gasket electrically connected with the chip units is equivalent to the leading-out electrode of each chip unit, the metal gasket is connected with the circuit structure in the chip units, the electric signals of the chip units are led out through the wiring layer formed subsequently, compared with the V-shaped through hole in the prior art, the gradient of the side wall of the T-shaped hole is more gentle, and the first insulating layer with the preset thickness is formed on the Y-shaped through hole subsequently more easily, so that the electric signals of the chip units of the chip packaging structure can be transmitted to the metal solder balls through. And under the condition that the thickness of the wafer is variable, the preparation of the packaging structure can be completed under the condition that the original opening and the side wall gradient of the T-shaped hole are kept by changing the depth of the straight hole.
Drawings
Fig. 1 is a schematic structural diagram of a chip package according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of another chip package according to an embodiment of the present invention;
fig. 3 is a schematic flow chart illustrating a chip packaging method according to an embodiment of the present invention;
fig. 4-5 are cross-sectional views corresponding to steps of a chip packaging method according to an embodiment of the invention;
fig. 6 is a schematic flowchart of another chip packaging method according to an embodiment of the present invention;
fig. 7 is a schematic flowchart of another chip packaging method according to an embodiment of the present invention;
fig. 8-10 are cross-sectional views corresponding to steps of another chip packaging method according to an embodiment of the invention;
fig. 11 is a flowchart illustrating a further chip packaging method according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Fig. 1 is a schematic structural diagram of a chip package according to an embodiment of the present invention. Referring to fig. 1, the chip package structure includes: the wafer 10 comprises a wafer 10, wherein the wafer 10 is provided with a first surface 100 and a second surface 101 opposite to the first surface 100, a plurality of chip units 11 are contained in the wafer 10, a plurality of metal pads 12 are arranged on the first surface 100, and the metal pads 12 are electrically connected with the chip units 11; the wafer 10 includes at least one Y-shaped via 13, and the Y-shaped via 13 includes a T-shaped hole 130 and a straight hole 131 communicating with each other, and the straight hole 131 exposes a part or all of the metal pad 12.
In the present embodiment, the wafer 10 may be silicon, germanium or other semiconductor substrate material. The chip unit is a circuit structure formed by multiple layers of electronic elements with specific functions formed on the first surface of the wafer through processes such as multiple times of photoetching, ion implantation, etching, evaporation and the like. The metal pads 12 electrically connected to the chip units 11 correspond to the lead electrodes of each chip unit, and the metal pads 12 are connected to the circuit structures in the chip units. The Y-shaped via 13 may be formed by, for example, a sequential etching process.
When a chip is packaged by the existing wafer level packaging technology, a through silicon via technology is generally used for circuit interconnection, that is, a hole and wiring process is formed on one surface of a wafer, and an electrical signal of a chip unit is transmitted to a metal solder ball through a wiring layer. However, the through-silicon via is generally a V-shaped via, and since the slope of the sidewall of the V-shaped via is steep, the first insulating layer with a predetermined thickness is formed on the V-shaped via, especially at the corner of the V-shaped via, and when the first insulating layer is an organic material, such a problem is more likely to occur. If the first insulating layer does not reach a predetermined thickness, the wiring layer formed on the first insulating layer may not be well insulated from the wafer, resulting in a problem that electrical signals of the chip unit of the chip package structure may not be well transmitted to the metal solder balls through the wiring layer.
In the technical solution provided in this embodiment, the wafer 10 includes at least one Y-shaped through hole 13, the Y-shaped through hole 13 includes a T-shaped hole 130 and a straight hole 131 that are communicated with each other, the straight hole 131 exposes a part or all of the metal pad 12, the metal pad 12 electrically connected to the chip unit 11 is equivalent to a lead-out electrode of each chip unit 11, the metal pad 12 is connected to a circuit structure in the chip unit 11, an electrical signal of the chip unit is led out with a subsequently formed wiring layer, compared with a V-shaped through hole in the prior art, the slope of a sidewall of the T-shaped through hole is gentler, and a first insulating layer with a preset thickness is easier to be formed on the Y-shaped through hole 13 subsequently, so that an electrical signal of the chip unit of the chip package structure can be transmitted to a metal solder. And under the condition that the thickness of the wafer is variable, the preparation of the packaging structure can be completed under the condition that the original opening and the side wall gradient of the T-shaped hole 130 are kept by changing the depth of the straight hole 131.
Optionally, on the basis of the above technical solution, referring to fig. 1, the slope ∠ 1 of the sidewall of the T-shaped hole 130 is greater than or equal to 58 degrees, in this embodiment, the smaller the slope of the sidewall of the T-shaped hole 130 is, the easier it is to form a first insulating layer with a predetermined thickness on the sidewall of the T-shaped hole 130 subsequently, when the slope of the sidewall of the T-shaped hole 130 is less than 58 degrees, the larger the opening of the T-shaped hole 130 is, the more etching materials are, the more etching time is, and the etching cost is higher.
Optionally, on the basis of the above technical solution, referring to fig. 1, the slope ∠ 1 of the sidewall of the T-shaped hole is less than or equal to 61 degrees, in this embodiment, the greater the slope of the sidewall of the T-shaped hole, specifically, when the slope ∠ 1 of the sidewall of the T-shaped hole is greater than 61 degrees, the less easily the first insulating layer with a preset thickness is formed on the sidewall of the T-shaped hole 130 in the following step.
In the case of a variable wafer thickness, the depth of the straight hole 131 may be changed to complete the fabrication of the package structure while maintaining the original opening and sidewall slope of the T-shaped hole 130.
Optionally, on the basis of the above technical solution, referring to fig. 1, the depth L1 of the straight hole 131 is greater than or equal to 35 μm. The smaller the depth of the straight hole 131, the thinner the wafer 10 may be selected while maintaining the original opening and sidewall slope of the T-shaped hole 130, but when the depth L1 of the straight hole 131 is less than 35 μm, the thickness of the wafer 10 is too thin, which may affect the mechanical strength of the package structure.
Optionally, on the basis of the above technical solution, referring to fig. 1, the depth L1 of the straight hole 131 is less than or equal to 55 micrometers. The larger the depth of the straight hole 131 is while maintaining the original opening and sidewall slope of the T-shaped hole 130, the thicker the wafer 10 can be selected, but when the depth L1 of the straight hole 131 is greater than 55 μm, the wafer 10 is too thick, which increases the manufacturing cost.
Optionally, on the basis of the above technical solution, referring to fig. 1, the surface 102 of the wafer 10, which communicates with two adjacent Y-shaped through holes 13, is parallel to the first surface 100, and the minimum distance L2 between any two adjacent Y-shaped through holes 13 is greater than or equal to 16 micrometers. The depth of the straight hole 131 is changed to complete the preparation of the package structure while maintaining the original opening and sidewall slope of the T-shaped hole 130. The minimum distance L2 between any two adjacent Y-shaped through holes 13 can be kept within a preset range while maintaining the original opening and sidewall slope of the T-shaped hole 130. The smaller the minimum distance L2 between any two adjacent Y-shaped through holes 13 is, the less easily it is to form a first insulating layer with a predetermined thickness on the surface 102 of the wafer 10 communicating with two adjacent Y-shaped through holes 13. When the minimum distance L2 between any two adjacent Y-shaped through holes 13 is greater than or equal to 16 μm, a first insulating layer with a predetermined thickness can be easily formed on the surface 102 of the wafer 10 communicating with two adjacent Y-shaped through holes 13.
Optionally, on the basis of the above technical solution, referring to fig. 1, a distance L3 between central axes of any two adjacent straight holes 131 is greater than or equal to 117 micrometers. The distance L3 between the central axes of any two adjacent straight holes 131 is too small, the distance between two adjacent metal pads 12 is too close, crosstalk of electrical signals is easily formed, and the distance L3 between the central axes of any two adjacent straight holes 131 is too large, which increases the manufacturing cost.
Optionally, on the basis of the above technical solution, referring to fig. 2, the structure of the chip package further includes a first insulating layer 20 covering the sidewall of the Y-shaped through hole 13 and the second surface 101. The first insulating layer 20 may be an inorganic material SiO2And may be formed by a thermal growth or deposition process. The thermal growth process is to form an oxide layer, i.e. the first insulating layer 20, on the surface of a wafer (e.g. a silicon wafer) by externally supplying high-purity oxygen to react with the wafer. The silicon source and oxygen gas are supplied from the outside and react in the chamber to form an oxide layer film, i.e., the first insulating layer 20, on the surface of the silicon wafer. The first insulating layer 20 may also be an organic material, and may be formed by spraying or otherwise. The first insulating layer 20 may be formed by, for example, a spray coating or spin coating process. Illustratively, the first insulating layer 20 may be a photoresist of photosensitive resin, and since the first insulating layer 20 is a photosensitive material, exposure may be performed through a mask having an exposure pattern. The exposure may be performed by ultraviolet light, which is irradiated onto the first insulating layer 20 through the exposure pattern of the mask and reacts therewith. After exposure, development is performed, and the developer reacts with the first insulating layer 20 irradiated by the ultraviolet light to dissolve and remove the first insulating layer 20, so that the bottom surface and the side wall of the straight hole 131 are exposed, and the first insulating layer 20 which is not irradiated by the ultraviolet light is left. Furthermore, by means of photolithographyThe first insulating layer 20 except the bottom surface and the side wall of the straight hole 131 does not damage the metal substrate 12, and compared with the dry etching or wet etching method for removing the first insulating layer 20 except the bottom surface and the side wall of the straight hole 131, the subsequent etching process can be saved, the process procedure is reduced, and the production efficiency is improved.
Optionally, on the basis of the above technical solution, referring to fig. 2, the structure of the chip package further includes a wiring layer 30, located on a surface of the first insulating layer 20 on a side away from the wafer 10, and electrically connected to the metal pad 12. The wiring layer 30 may include one or more layers of metal. The manufacturing process of the wiring layer 30 may be, for example, a magnetron sputtering process. The wiring layer 30 leads out an electrical signal of the metal pad 12 to the second surface 101 of the wafer 10. It should be noted that the multi-layer metal-formed wiring layer 30 can be better electrically connected to the metal pad 12 than the one-layer metal-formed wiring layer 30. Illustratively, metal titanium is sputtered on the surface of the first insulating layer 20 on the side away from the wafer 10, and then a layer of metal copper is sputtered on the surface of the metal titanium by magnetron sputtering, thereby completing the fabrication of the wiring layer 30.
Optionally, on the basis of the above technical solution, referring to fig. 2, the structure of the chip package further includes at least one metal solder ball 40, which is located on a surface of the wiring layer 30 away from the first insulating layer 20, on the side covering the second surface 101 of the wafer 10, and is electrically connected to the wiring layer 30. The metal solder balls 40 are electrically connected to the wiring layer 30, and can lead out electrical signals of the chip units to the second surface 101 of the wafer 10.
Optionally, on the basis of the above technical solution, referring to fig. 2, the structure of the chip package further includes a second insulating layer 50, the second insulating layer includes at least one opening structure 51, the second insulating layer 50 covers the wiring layer 30, and each opening structure 51 exposes one metal solder ball 40. The second insulating layer 50 functions to protect the wiring layer 30.
Optionally, on the basis of the above technical solution, the thickness of the first insulating layer 20 is greater than or equal to 3 micrometers. In the present embodiment, the wafer 10 includes at least one Y-shaped via 13, the Y-shaped via 13 includes a T-shaped hole 130 and a straight hole 131 that are communicated with each other, the straight hole 131 exposes part or all of the metal pad 12, the metal pad 12 electrically connected to the chip unit 11 is equivalent to an extraction electrode of each chip unit, the metal pad 12 is connected to a circuit structure in the chip unit, an electrical signal of the chip unit is extracted with a subsequently formed wiring layer, the slope of a sidewall of the T-shaped hole is gentler than that of the V-shaped via 13 in the prior art, and the first insulating layer 20 with a predetermined thickness is easier to be subsequently formed on the Y-shaped via 13, so that the electrical signal of the chip unit of the chip package structure can be transmitted to the metal solder ball through the wiring layer. The predetermined thickness of the first insulating layer 20 is greater than or equal to 3 micrometers, and if the thickness of the first insulating layer 20 is less than 3 micrometers, the wiring layer 30 formed on the first insulating layer 20 cannot be well insulated from the wafer 10, resulting in a problem that the electrical signals of the chip unit 11 of the chip package structure cannot be well transmitted to the metal solder balls 40 through the wiring layer 30.
Optionally, on the basis of the above technical solution, the first insulating layer 20 includes an organic insulating material. The organic insulating material may be formed by spray coating or spin coating. Illustratively, the organic insulating material may be a photosensitive resin resist, which is a kind of resist having good photosensitive characteristics. The photosensitive resin photoresist has good insulation, and the residual part after photoetching is not required to be stripped, so that the photosensitive resin photoresist is used as an insulating material for isolating the wafer from a subsequent metal wiring layer, and the performance of a device is not influenced.
Optionally, on the basis of the above technical solution, the second insulating layer 50 includes a solder resist layer. The solder resist layer functions to protect the wiring layer 30.
Based on the same inventive concept, an embodiment of the present invention further provides a chip packaging method, and fig. 3 shows a preparation flowchart of the chip packaging method provided by the embodiment of the present invention, and referring to fig. 3, the method includes the following steps:
Referring to fig. 4, a wafer 10 is provided, the wafer 10 has a first surface 100 and a second surface 101 opposite to the first surface 100, the wafer 10 includes a plurality of chip units 11, the second surface 101 is provided with a plurality of metal pads 12, and the metal pads 12 are electrically connected to the chip units 11. The chip unit 11 is a circuit structure formed by multiple layers of electronic components with specific functions formed on the first surface 100 of the wafer 10 through multiple processes such as photolithography, ion implantation, etching, and evaporation. The metal pad 12 corresponds to a lead-out electrode of each chip unit 11, and the metal pad 12 is connected to a circuit structure in the chip unit 11. The wafer 10 may be silicon, germanium, or other semiconductor substrate material.
And 120, forming at least one Y-shaped through hole on the wafer, wherein the Y-shaped through hole comprises a T-shaped hole and a straight hole which are communicated, and part or all of the metal gasket is exposed by the straight hole.
Referring to fig. 5, at least one Y-shaped via 13 is formed in the wafer 10, the Y-shaped via 13 includes a T-shaped hole 130 and a straight hole 131 that are connected, and the straight hole 131 exposes a part or all of the metal pad 12. The Y-shaped via 13 may be formed by, for example, a sequential etching process.
When a chip is packaged by the existing wafer level packaging technology, a through silicon via technology is generally used for circuit interconnection, that is, a hole and wiring process is formed on one surface of a wafer, and an electrical signal of a chip unit is transmitted to a metal solder ball through a wiring layer. However, the through-silicon via is generally a V-shaped via, and since the slope of the sidewall of the V-shaped via is steep, the first insulating layer with a predetermined thickness is formed on the V-shaped via, especially at the corner of the V-shaped via, and when the first insulating layer is an organic material, such a problem is more likely to occur. If the first insulating layer does not reach a predetermined thickness, the wiring layer formed on the first insulating layer may not be well insulated from the wafer, resulting in a problem that electrical signals of the chip unit of the chip package structure may not be well transmitted to the metal solder balls through the wiring layer.
In the technical solution provided in this embodiment, the wafer 10 includes at least one Y-shaped through hole 13, the Y-shaped through hole 13 includes a T-shaped hole 130 and a straight hole 131 that are communicated with each other, the straight hole 131 exposes a part or all of the metal pad 12, the metal pad 12 electrically connected to the chip unit 11 is equivalent to a lead-out electrode of each chip unit, the metal pad 12 is connected to a circuit structure in the chip unit, an electrical signal of the chip unit is led out with a subsequently formed wiring layer, compared with a V-shaped through hole in the prior art, the slope of a sidewall of the T-shaped through hole is gentler, and a first insulating layer with a preset thickness is easier to be formed on the Y-shaped through hole 13 subsequently, so that an electrical signal of the chip unit of the chip package structure can be transmitted to a metal solder. And under the condition that the thickness of the wafer is variable, the preparation of the packaging structure can be completed under the condition that the original opening and the side wall gradient of the T-shaped hole 130 are kept by changing the depth of the straight hole 131.
Optionally, on the basis of the foregoing technical solution, referring to fig. 6, in step 120, at least one Y-shaped via is formed in the wafer, where the Y-shaped via includes a T-shaped hole and a straight hole that are communicated with each other, and the straight hole exposes a part or all of the metal pad, and includes:
Taking fig. 5 as an example, a dry etching process is used to form T-shaped holes 130 in the wafer. The T-shaped holes 130 may be formed in the wafer, for example, by photolithography and deep reactive ion etching processes.
Taking fig. 5 as an example, a dry etching process is used to form a straight hole 131 communicating with the T-shaped hole 130, and the straight hole 131 exposes part or all of the metal pad 12. The straight hole 131 communicating with the T-shaped hole 130 may be formed by, for example, photolithography and a deep reactive ion etching process.
In the above technical scheme, the dry etching process may utilize an electron cyclotron oscillation reactor, a reactive ion etching reactor, a magnetically enhanced reactive ion etching reactor, or an inductively coupled plasma reactor to perform etching, and the etching gas used in the dry etching process is an etching gas containing halogen elements such as fluorine, chlorine, bromine, and iodine, or oxygen or sulfur.
Optionally, on the basis of the above technical solution, referring to fig. 7, step 120 further includes, after the wafer forms at least one Y-shaped via:
Referring to fig. 8, a first insulating layer 20 is formed on the sidewalls of the Y-shaped via 13 and the second surface 101. The first insulating layer 20 may be an inorganic material SiO2And may be formed by a thermal growth or deposition process. The thermal growth process is to form an oxide layer, i.e. the first insulating layer 20, on the surface of a wafer (e.g. a silicon wafer) by externally supplying high-purity oxygen to react with the wafer. The silicon source and oxygen gas are supplied from the outside and react in the chamber to form an oxide layer film, i.e., the first insulating layer 20, on the surface of the silicon wafer. The first insulating layer 20 may also be an organic paste, and may be formed by spraying or spin coating. The first insulating layer 20 may be formed by, for example, a spray coating or spin coating process. Illustratively, the first insulating layer 20 may be a photoresist of photosensitive resin, which is a kind of photoresist having good photosensitive characteristics. The photosensitive resin photoresist has good insulation, and the residual part after photoetching is not required to be stripped, so that the photosensitive resin photoresist is used as an insulating material for isolating the wafer from a subsequent metal wiring layer, and the performance of a device is not influenced. The photosensitive material can thus be exposed through a reticle having an exposure pattern. The exposure may be performed by ultraviolet light, which is irradiated onto the first insulating layer 20 through the exposure pattern of the mask and reacts therewith. After exposure, development is performed, and the developer reacts with the first insulating layer 20 irradiated by the ultraviolet light to dissolve and remove the first insulating layer 20, so that the bottom surface and the side wall of the straight hole 131 are exposed, and the first insulating layer 20 which is not irradiated by the ultraviolet light is left. In addition, the first insulating layer 20 on the bottom surface and the side wall of the straight hole 131 is removed by photolithography, so that the metal substrate 12 is not damaged, and compared with the first insulating layer 20 on the bottom surface and the side wall of the straight hole 131 which is removed by dry etching or wet etching, the subsequent etching process can be saved, the process is reduced, and the production efficiency is improved.
Optionally, on the basis of the foregoing technical solution, referring to fig. 7, the step 130 further includes, after forming the first insulating layer on the sidewall and the second surface of the Y-shaped via:
in step 140, a wiring layer is formed on the surface of the first insulating layer away from the wafer and electrically connected to the metal pad.
Referring to fig. 9, a wiring layer 30 is formed on the surface of the first insulating layer 20 on the side away from the wafer 10, and is electrically connected to the metal pad 12. The wiring layer 30 may include one or more layers of metal. The manufacturing process of the wiring layer 30 may be, for example, a magnetron sputtering process. The wiring layer 30 leads out an electrical signal of the metal pad 12 to the second surface 101 of the wafer 10. It should be noted that the multi-layer metal-formed wiring layer 30 can be better electrically connected to the metal pad 12 than the one-layer metal-formed wiring layer 30. Illustratively, metal titanium is sputtered on the surface of the first insulating layer 20 on the side away from the wafer 10, and then a layer of metal copper is sputtered on the surface of the metal titanium by magnetron sputtering, thereby completing the fabrication of the wiring layer 30.
Optionally, on the basis of the above technical solution, referring to fig. 7, the step 140 of forming a wiring layer on a surface of the first insulating layer on a side away from the wafer further includes, after electrically connecting with the metal pad:
Referring to fig. 10, at least one metal solder ball 40 is formed on a surface of the wiring layer 30 away from the first insulating layer 20 on the side covering the second surface 101 of the wafer 10, and is electrically connected to the wiring layer 30. The metal solder balls 40 are electrically connected to the wiring layer 30, and can lead out electrical signals of the chip units to the second surface 101 of the wafer 10.
Optionally, on the basis of the foregoing technical solution, referring to fig. 11, step 150 forms at least one metal solder ball on a surface of the wiring layer away from the first insulating layer, the surface covering the second surface of the wafer, and before electrically connecting with the wiring layer, the method further includes:
Taking fig. 2 as an example for explanation, a second insulating layer 50 is formed on a surface of the wiring layer 30 on a side away from the first insulating layer 20, and the second insulating layer 50 includes an opening structure (not shown).
As illustrated in fig. 2, a metal solder ball 40 is formed in an opening structure. The metal solder balls 40 are electrically connected to the wiring layer 30, and can lead out electrical signals of the chip units to the second surface 101 of the wafer 10.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious modifications, rearrangements, combinations and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (20)
1. A chip package structure, comprising:
the wafer is provided with a first surface and a second surface opposite to the first surface, the wafer contains a plurality of chip units, the first surface is provided with a plurality of metal gaskets, and the metal gaskets are electrically connected with the chip units;
the wafer comprises at least one Y-shaped through hole, the Y-shaped through hole comprises a T-shaped hole and a straight hole which are communicated, and part or all of the metal gasket is exposed by the straight hole.
2. The chip package structure according to claim 1, wherein a slope of a sidewall of the T-shaped hole is greater than or equal to 58 degrees.
3. The chip package structure according to claim 2, wherein a slope of a sidewall of the T-shaped hole is less than or equal to 61 degrees.
4. The chip package structure according to claim 1, wherein the depth of the straight hole is greater than or equal to 35 μm.
5. The chip package structure according to claim 4, wherein the depth of the straight hole is less than or equal to 55 μm.
6. The chip package structure according to claim 1, wherein the wafer connects two adjacent surfaces of the Y-shaped through holes to be parallel to the first surface, and a minimum distance between any two adjacent Y-shaped through holes is greater than or equal to 16 μm.
7. The chip package structure according to claim 6, wherein a distance between central axes of any two adjacent straight holes is greater than or equal to 117 μm.
8. The chip packaging structure according to claim 1, further comprising a first insulating layer covering sidewalls of the Y-shaped via and the second surface.
9. The chip package structure according to claim 8, further comprising a wiring layer on a surface of the first insulating layer on a side away from the wafer, the wiring layer being electrically connected to the metal pad.
10. The chip package structure according to claim 9, further comprising at least one metal solder ball located on a surface of the wiring layer away from the first insulating layer covering the second surface of the wafer and electrically connected to the wiring layer.
11. The chip package structure according to claim 10, further comprising a second insulating layer, wherein the second insulating layer comprises at least one opening structure, the second insulating layer covers the wiring layer, and each opening structure exposes one of the metal solder balls.
12. The chip packaging structure according to claim 8, wherein a thickness of the first insulating layer is greater than or equal to 3 μm.
13. The chip packaging structure according to claim 8, wherein the first insulating layer comprises an organic insulating material.
14. The chip packaging structure according to claim 11, wherein the second insulating layer comprises a solder resist layer.
15. A method of chip packaging, comprising:
providing a wafer, wherein the wafer is provided with a first surface and a second surface opposite to the first surface, a plurality of chip units are contained in the wafer, a plurality of metal gaskets are arranged on the second surface, and the metal gaskets are electrically connected with the chip units;
and forming at least one Y-shaped through hole on the wafer, wherein the Y-shaped through hole comprises a T-shaped hole and a straight hole which are communicated, and part or all of the metal gasket is exposed by the straight hole.
16. The method of claim 15, wherein forming at least one Y-via in the wafer, the Y-via comprising a T-via and a straight via that are connected to each other, the straight via exposing part or all of the metal pad comprises:
forming a T-shaped hole on the wafer by adopting a dry etching process;
and forming a straight hole communicated with the T-shaped hole by adopting a dry etching process, wherein part or all of the metal gasket is exposed by the straight hole.
17. The chip packaging method according to claim 15, further comprising, after the wafer forms at least one Y-via:
and forming a first insulating layer on the side wall of the Y-shaped through hole and the second surface.
18. The chip packaging method according to claim 17, further comprising, after forming a first insulating layer on the sidewalls of the Y-shaped via and the second surface:
and a wiring layer is formed on the surface of one side, away from the wafer, of the first insulating layer and is electrically connected with the metal gasket.
19. The chip packaging method according to claim 17, wherein a wiring layer is formed on a surface of the first insulating layer on a side away from the wafer, and after electrically connecting the wiring layer to the metal pad, the method further comprises:
and forming at least one metal solder ball on the surface of the wiring layer, which is far away from the first insulating layer and covers the second surface of the wafer, and electrically connecting the metal solder ball with the wiring layer.
20. The chip packaging method according to claim 19, wherein at least one metal solder ball is formed on a surface of the wiring layer away from the first insulating layer on a side covering the second surface of the wafer, and before electrically connecting with the wiring layer, the method further comprises:
forming a second insulating layer on the surface of the wiring layer, which is far away from one side of the first insulating layer, wherein the second insulating layer comprises an opening structure;
and forming a metal solder ball in the opening structure.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911195017.6A CN110867432A (en) | 2019-11-28 | 2019-11-28 | Chip packaging structure and packaging method |
| PCT/CN2019/123634 WO2021103110A1 (en) | 2019-11-28 | 2019-12-06 | Chip package structure and packaging method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201911195017.6A CN110867432A (en) | 2019-11-28 | 2019-11-28 | Chip packaging structure and packaging method |
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| CN110867432A true CN110867432A (en) | 2020-03-06 |
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| CN201911195017.6A Pending CN110867432A (en) | 2019-11-28 | 2019-11-28 | Chip packaging structure and packaging method |
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| WO (1) | WO2021103110A1 (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104617036A (en) * | 2015-01-14 | 2015-05-13 | 华天科技（昆山）电子有限公司 | Manufacturing method for interconnected through holes in wafer level chip size packaging |
| CN105304557A (en) * | 2015-08-20 | 2016-02-03 | 苏州科阳光电科技有限公司 | Wafer-level image senor |
| CN106229272A (en) * | 2016-08-23 | 2016-12-14 | 苏州科阳光电科技有限公司 | Wafer stage chip encapsulation method and structure |
| CN107068629A (en) * | 2017-04-24 | 2017-08-18 | 华天科技（昆山）电子有限公司 | Wafer stage chip encapsulating structure and preparation method thereof |
| CN108022898A (en) * | 2017-12-29 | 2018-05-11 | 苏州晶方半导体科技股份有限公司 | A kind of semiconductor devices and preparation method thereof |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005101268A (en) * | 2003-09-25 | 2005-04-14 | Sanyo Electric Co Ltd | Method for manufacturing semiconductor device |
| CN101800207B (en) * | 2010-03-12 | 2011-10-26 | 苏州晶方半导体科技股份有限公司 | Packaging structure of semiconductor element and manufacture method thereof |
| CN104377180B (en) * | 2014-11-24 | 2018-09-28 | 苏州晶方半导体科技股份有限公司 | Through-silicon via structure and forming method thereof |
| CN107342234A (en) * | 2017-07-07 | 2017-11-10 | 苏州晶方半导体科技股份有限公司 | The method for packing and structure of fingerprint recognition chip and driving chip |
-
2019
- 2019-11-28 CN CN201911195017.6A patent/CN110867432A/en active Pending
- 2019-12-06 WO PCT/CN2019/123634 patent/WO2021103110A1/en active Application Filing
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104617036A (en) * | 2015-01-14 | 2015-05-13 | 华天科技（昆山）电子有限公司 | Manufacturing method for interconnected through holes in wafer level chip size packaging |
| CN105304557A (en) * | 2015-08-20 | 2016-02-03 | 苏州科阳光电科技有限公司 | Wafer-level image senor |
| CN106229272A (en) * | 2016-08-23 | 2016-12-14 | 苏州科阳光电科技有限公司 | Wafer stage chip encapsulation method and structure |
| CN107068629A (en) * | 2017-04-24 | 2017-08-18 | 华天科技（昆山）电子有限公司 | Wafer stage chip encapsulating structure and preparation method thereof |
| CN108022898A (en) * | 2017-12-29 | 2018-05-11 | 苏州晶方半导体科技股份有限公司 | A kind of semiconductor devices and preparation method thereof |
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| WO2021103110A1 (en) | 2021-06-03 |
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