CN104377180B - Through-silicon via structure and forming method thereof - Google Patents
Through-silicon via structure and forming method thereof Download PDFInfo
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- CN104377180B CN104377180B CN201410683126.3A CN201410683126A CN104377180B CN 104377180 B CN104377180 B CN 104377180B CN 201410683126 A CN201410683126 A CN 201410683126A CN 104377180 B CN104377180 B CN 104377180B
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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Abstract
A kind of through-silicon via structure and forming method thereof, through-silicon via structure includes：Substrate；Through-hole in the substrate；Buffering opening in the substrate, the buffering opening are located at the via top, and the side wall of the buffering opening is tilted relative to substrate surface, and the top dimension of the buffering opening is more than bottom size；Positioned at the buffering opening sidewalls surface and the side wall of the through-hole and the first insulating layer of bottom surface；Positioned at the conductive layer of first surface of insulating layer.The performance improvement of the through-silicon via structure, reliability enhancing.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of through-silicon via structure and forming method thereof.
Background technology
With the continuous development of semiconductor fabrication, the characteristic size of semiconductor devices constantly reduces, and the collection of chip
It is higher and higher at spending.However, current two-dimensional package structure has been difficult to meet growing chip integration demand, therefore three
Tieing up encapsulation technology becomes the key technology for crossing over integrated chip bottleneck.
Three-dimensional stacked technology based on silicon hole (Through Silicon Via, TSV) is existing three-dimensional packaging technology
In one kind, the three-dimensional stacked technology based on silicon hole be improve chip integration one of main method.
The three-dimensional stacked technology based on silicon hole has the following advantages：High Density Integration；Significantly shorten and is electrically interconnected
Length, so as to well solve the problems such as appearing in the signal delay in two-dimentional system grade chip technology；It can be tool
There is the chip (such as radio frequency, memory, logic, MEMS) of different function to integrate, to realize the multi-functional of encapsulation chip.
The forming process of existing through-silicon via structure is as shown in Figure 1 to Figure 3.
Referring to FIG. 1, providing substrate 100, the substrate 100 has opposite first surface 110 and second surface 120；
Through-hole 103 is formed in the substrate 100,103 top of the through-hole is located at the first surface 110 of the substrate 100.
Referring to FIG. 2, at the first surface 110 of the substrate 100 and side wall and the bottom of through-hole 103 (as shown in Figure 1)
Portion surface forms insulating film 104；Conductive film 105 is formed on 104 surface of the insulating film.
Referring to FIG. 3, being chemically-mechanicapolish polished to the conductive film 105 and insulating film 104, until exposing the lining
Until the first surface 110 at bottom 100, conductive structure 105a is formed in the substrate 100.
Later, the second surface 120 of the substrate 100 can be thinned, is until exposing conductive plunger 104
Only, the conductive plunger 104 is made to run through the substrate 100.It can make partly leading for various substrates surface by the conductive plunger
It realizes and is electrically connected between body device, to realize the integrated of chip.
However, existing through-silicon via structure reliability is poor, electrical property is unstable.
Invention content
Problems solved by the invention is to provide a kind of through-silicon via structure and forming method thereof, the performance of the through-silicon via structure
Improve, reliability enhancing.
To solve the above problems, the present invention provides a kind of forming method of silicon hole, including：Substrate is provided；In the lining
Form that through-hole is gentle to wash mouth open in bottom, the buffering opening is located at the via top, the side wall that the buffering is open relative to
Substrate surface tilts, and the top dimension of the buffering opening is more than bottom size；On the buffering opening sidewalls surface and
The side wall and bottom surface of the through-hole form the first insulating layer；Conductive layer is formed in first surface of insulating layer.
Optionally, there is the substrate opposite first surface and second surface, the top of the buffering opening to be located at institute
State the first surface of substrate.
Optionally, further include：After forming the conductive layer, the first surface of the substrate is thinned, until
Until exposing the conductive layer surface.
Optionally, the gentle forming method for washing mouth open of the through-hole includes：Mask layer is formed in the substrate surface, it is described
Mask open in mask layer is projected on the shape and position consistency of the figure and the default via top of substrate surface；With institute
It is mask to state mask layer, etches the substrate, is formed in the substrate and presets through-hole, and forms mask in the substrate surface
Layer, the side wall of the default through-hole has in the substrate surface, the mask layer exposes the default through-hole
Mask open, the side wall of the mask open are flushed with the side wall of the default through-hole；Remove the portion around the default through-hole
Divide mask layer, exposes the section substrate surface around the default through-hole, the mask open is made to be projected on substrate surface
Dimension of picture increases；After removing the part mask layer around the default through-hole, using the mask layer as mask, institute is etched
Substrate is stated, forms buffering opening in the substrate, the default through-hole positioned at the buffering open bottom forms the through-hole.
Optionally, the mask layer includes photoresist layer.
Optionally, the technique of the part mask layer around the removal default through-hole is isotropic dry etching
Technique or isotropic wet-etching technology.
Optionally, the technique for forming the buffering opening is anisotropic dry etch process.
Optionally, the formation process of first insulating layer and conductive layer includes：In the substrate surface, buffering open side
The sidewall surfaces of wall surface and the through-hole form the first insulating layer；In the bottom of first surface of insulating layer and through-hole
Surface forms conductive film；Technique is patterned to the conductive film, and exposes the first insulating layer positioned at substrate surface, shape
At the conductive layer, and the conductive layer forms wiring.
Optionally, the completely described buffering opening and through-hole are filled or be not filled by the conductive film；Figure is carried out to the conductive film
After shape chemical industry skill, soldermask layer is formed in the conductive layer and the first surface of insulating layer.
Correspondingly, the present invention also provides a kind of silicon holes, including：Substrate；Through-hole in the substrate；Positioned at described
Buffering opening in substrate, the buffering opening are located at the via top, and the side wall of the buffering opening is relative to substrate table
Face tilts, and the top dimension of the buffering opening is more than bottom size；Positioned at the buffering opening sidewalls surface and described
The side wall of through-hole and the first insulating layer of bottom surface；Positioned at the conductive layer of first surface of insulating layer.
Optionally, there is the substrate opposite first surface and second surface, the top of the buffering opening to be located at institute
State the first surface of substrate.
Optionally, the second surface of the substrate exposes the conductive layer surface.
Optionally, the substrate includes semiconductor base.
Optionally, the substrate further includes：The device layer for including positioned at semiconductor base, the second surface of the substrate are
Device layer surface, the interior device layer includes device architecture, conductive structure and the encirclement device architecture and conductive structure
Dielectric layer.
Optionally, the side wall of the buffering opening is 30 °~70 ° relative to the inclined angle of substrate surface；The buffering
The depth of opening is 5 microns~50 microns.
Optionally, the completely described buffering opening is filled or be not filled by the conductive layer and through-hole, the conductive layer surface also have
There is soldermask layer.
Compared with prior art, technical scheme of the present invention has the following advantages：
In the method for the present invention, formation through-hole is gentle in substrate washes mouth open, and the buffering opening is located at the through-hole top
Portion, and the side wall of the buffering opening is tilted relative to substrate surface, the top dimension of the buffering opening is more than bottom size.
When subsequently it is described buffering opening sidewalls surface and the through-hole side wall and bottom surface formed the first insulating layer, and
First surface of insulating layer is formed after conductive layer, since the substrate surface is described slow to having between the through-hole side wall
The side wall for washing mouth open carries out excessively, and the side wall of the buffering opening is tilted relative to the substrate surface, therefore, is formed in institute
Stating buffering opening sidewalls surface makes stress be disperseed, and occurs to tire out between substrate surface and through-hole side wall so as to avoid stress
Product, then avoid first insulating layer from being broken due to by excessive stresses so that between the conductive layer and substrate electricity every
From effect stability.Performance stabilization, the reliability for being formed by through-silicon via structure improve.
Further, it is formed in the substrate and presets through-hole, and the substrate surface has mask layer, in the mask layer
With mask open, and the mask open be projected on substrate surface shape and position it is consistent with the through-hole；Pass through removal
Part mask layer around the through-hole can expose the section substrate surface around the default through-hole, then by with
The mask layer is substrate described in mask etching, and buffering opening can be formed in substrate.Also, by etched substrate
Technological parameter is regulated and controled, such as the parameters such as the component ratio of etching gas, flow, air pressure, can be controlled and is formed by buffering
Angle of inclination of the side wall of opening relative to substrate surface enables to be formed by buffering opening sidewalls effectively dispersive stress.
Have through-hole is gentle to wash mouth open in the structure of the present invention, in the substrate, the buffering opening is located at the through-hole
Top, and the side wall of the buffering opening is tilted relative to substrate surface, the top dimension of the buffering opening is more than bottom ruler
It is very little.The side wall and bottom surface of the buffering opening sidewalls surface and the through-hole have the first insulating layer and conductive layer,
Since the substrate surface is excessive to having the side wall of the buffering opening to carry out between the through-hole side wall, and the buffering is opened
The side wall of mouth is tilted relative to the substrate surface, and therefore, the buffering opening sidewalls surface makes stress be disperseed, to avoid
Stress is accumulated between substrate surface and through-hole side wall, then avoids first insulating layer due to by excessive stresses
Fracture so that the electric isolating effect between the conductive layer and substrate is stablized.Performance stabilization, the reliability of the through-silicon via structure
It improves.
Description of the drawings
Fig. 1 to Fig. 3 is the cross-sectional view of the forming process of existing through-silicon via structure；
Fig. 4 to Figure 11 is the section knot schematic diagram of the forming process of the through-silicon via structure of the embodiment of the present invention.
Specific implementation mode
As stated in the background art, existing through-silicon via structure reliability is poor, electrical property is unstable.
By the study found that with continued reference to FIG. 2, the insulating film 104 and conductive film 105 are formed in the substrate 100
First surface 110 and through-hole 103 (please referring to Fig.1) side wall and bottom surface.Due to being formed by 103 side wall of through-hole
Perpendicular to the first surface 110 of the substrate 100, i.e. the side wall of the through-hole 103 being capable of structure with 100 first surface 110 of substrate
At the apex angle at 103 top of the through-hole, and the apex angle is rectangular, and the stress in manufacturing process is easy in the through-hole
103 vertex are accumulated.And the insulating film 104 and conductive film 105 are covered in the surface of the apex angle, and therefore, institute's rheme
Insulating film 104 in the apex angle surface at 103 top of through-hole is easy to be stressed influence and fracture (crack) occurs, and is then easy
Cause to be subsequently formed and directly be in contact with substrate 100 in the conductive film 105 on 104 surface of the insulating film, makes to be formed by conduction
Short circuit occurs between film 105 and substrate 100, that is, is formed by conductive structure 105a and is easy that short circuit occurs between substrate 100.
To solve the above-mentioned problems, a kind of through-silicon via structure of present invention proposition and forming method thereof.In the silicon hole
In forming method, formation through-hole is gentle in substrate washes mouth open, and the buffering opening is located at the via top, and the buffering
The side wall of opening is tilted relative to substrate surface, and the top dimension of the buffering opening is more than bottom size.When subsequently described
The side wall and bottom surface for buffering opening sidewalls surface and the through-hole form the first insulating layer, and in first insulation
Layer surface is formed after conductive layer, due to the substrate surface to the side wall between the through-hole side wall with the buffering opening
It carries out excessively, and the side wall of the buffering opening is tilted relative to the substrate surface, therefore, is formed in the buffering open side
Wall makes stress be disperseed, and is accumulated between substrate surface and through-hole side wall so as to avoid stress, then avoids described
One insulating layer is broken due to by excessive stresses so that the electric isolating effect between the conductive layer and substrate is stablized.It is formed
Through-silicon via structure performance is stable, reliability improves.
To make the above purposes, features and advantages of the invention more obvious and understandable, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Fig. 4 to Figure 11 is the cross-sectional view of the forming process of the through-silicon via structure of the embodiment of the present invention.
Referring to FIG. 4, providing substrate 200.
The substrate 200 has opposite first surface 210 and second surface 220, is subsequently formed by be used to form and lead
The open top of electric layer is located at the first surface 210 of the substrate 200.
The substrate 200 includes semiconductor base.In the present embodiment, the substrate 200 further includes positioned at semiconductor-based
The device layer that bottom includes, the surface of the device layer are the second surface 220 of substrate 200；It include device junction in the device layer
Structure, conductive structure and the dielectric layer for surrounding the device architecture and conductive structure.In other embodiments, the substrate 200
It can also be only the semiconductor base.
The semiconductor base include silicon substrate, silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator substrate, on insulator
Germanium substrate, glass substrate or III-V compound substrate (such as gallium nitride substrate or gallium arsenide substrate etc.).
The device architecture includes gate structure, fuse-wires structure, electric resistance structure, capacitance structure, the induction structure of transistor
In it is one or more.The dielectric layer is located at the semiconductor substrate surface, and the dielectric layer covers the device architecture,
For making to be electrically isolated from each other between the device architecture and conductive structure；The material of the dielectric layer is silica, silicon nitride, nitrogen
It is one or more in silica, low-K dielectric material, ultralow K dielectric materials.The conductive structure is used to make between device architecture
Realize and be electrically interconnected, the material of the conductive structure includes metal or metallic compound, such as copper, tungsten, aluminium, titanium, nickel, titanium nitride and
One or more combinations in tantalum nitride.The conductive structure includes：It is formed in semiconductor substrate surface or device architecture surface
Conductive plunger and the electrical interconnection line that is formed at the top of conductive plunger, the electrical interconnection line it is real between conductive plunger for making
Now it is electrically connected.And it is subsequently formed in the gentle conductive layer needs washed open in mouth of through-hole and is connected with the conductive structure.
In one embodiment, second insulating layer is formed between the second surface and weld pad of the substrate, described second absolutely
The material of edge layer is insulating materials, and the second insulating layer is for making to be electrically isolated between the weld pad and substrate；Moreover, described
Two insulating layers can also be during subsequent etching substrate be to form default through-hole, as etching stop layer, for protecting
Weld pad surface is stated from damage；In order to make the conductive layer being subsequently formed be in contact with the weld pad, need be subsequently formed buffering
After opening and through-hole, the second insulating layer that removal via bottoms are exposed, and expose the weld pad surface.
In another embodiment, it is being subsequently formed buffering opening and through-hole, and is being formed in buffering opening and through-hole
The conductive layer and then the second surface of the substrate is thinned, until exposing the conductive layer surface.
After the second surface of the substrate is thinned, additionally it is possible in the conductive layer surface shape that the substrate second surface exposes
At weld pad；Passivation layer is formed in the substrate and weld pad surface.
In the present embodiment, before the default through-hole continued after its formation, the first surface 210 of the substrate 200 is carried out
It is thinned；The reduction process is CMP process, after the substrate 200 is thinned, the thickness of the substrate 200
Degree is subsequently formed by the depth of default through-hole, that is, the buffering opening and through-hole being subsequently formed can run through the substrate 200,
To form through-silicon via structure.
In one embodiment, after the first surface 210 to the substrate 200 is thinned, also in the substrate 200
Second surface 220 formed weld pad 221；The material of the weld pad 221 includes in copper, tungsten, aluminium, titanium, nickel, titanium nitride and tantalum nitride
One or more combinations；The formation process of the weld pad 221 includes：Weld pad film is formed in the second surface 220 of substrate 200；
The weld pad film is performed etching, and exposes the second surface 220 of substrate 200, to form the weld pad 221；It is formed by
The position of weld pad 221 is corresponding with the position for the default through-hole being subsequently formed so that the default via bottoms being subsequently formed can
Exposing the weld pad 221, the weld pad 221 is used to be electrically connected in the conductive layer in buffering opening and through-hole with being subsequently formed,
For in the subsequent process as the electrical contact position of the conductive layer.
After forming the weld pad 221, additionally it is possible in the 221 surface shape of second surface 220 and weld pad of the substrate 200
At passivation layer 222, the passivation layer 222 for protecting the second surface 220 of the substrate 200 and the weldering in the subsequent process
Pad 221；The material of the passivation layer 222 is inorganic insulating material or insulating material of polymer；The inorganic insulating material includes
It is one or more in silica, silicon nitride, silicon oxynitride.
Through-hole 201 is preset referring to FIG. 5, being formed in the substrate 200, and mask is formed on 200 surface of the substrate
Layer 202, the side wall of the default through-hole 201 has in 200 surface of the substrate, the mask layer 202 exposes institute
The mask open 203 of default through-hole 201 is stated, the side wall of the mask open 203 is flushed with the side wall of the default through-hole 201.
In the present embodiment, the first surface 210 of the substrate 200 is non-device layer surface, the default through-hole 201
Top is located at the first surface 210 of the substrate 200, and the mask layer 202 is located at the first surface 210 of the substrate 200, after
After the continuous size for expanding the mask open 203, the mask layer 202 forms the mask of buffering opening as etching.
In the present embodiment, before forming default through-hole 201, mask layer 202, institute are formed on 200 surface of the substrate
It states mask layer 202 to be additionally operable to form the mask for presetting through-hole 201 as etching, the mask open 203 in the mask layer 202 is thrown
Shadow is in the shape and position consistency of the figure and 201 top of the default through-hole on 200 surface of substrate；It is with the mask layer 202
Mask etches the substrate 200, forms the default through-hole 201.Wherein, mask layer 202 includes photoresist layer, the photoetching
Glue-line is patterned by photoetching process.
The side wall of default through-hole 201 is formed by perpendicular to 200 surface of the substrate, forms 201 work of default through-hole
Skill is anisotropic dry etch process；The etching direction of the anisotropic dry etch process is perpendicular to substrate 200
Surface, so as to form default through-hole 201 of the side wall perpendicular to 200 surface of substrate；And the base portion of the default through-hole 201
Divide and is subsequently used for being formed through-hole, and the top section of the default through-hole is subsequently used for forming buffering opening.
In the present embodiment, since the top of the default through-hole 201 is located at the first surface 210 of substrate 200, and it is described
The first surface 210 of substrate 200 is non-device layer surface, then the anisotropic dry etch process is in addition to needing to etch half
Except conductor substrate, it is also necessary to be performed etching to the device layer.
In the present embodiment, the semiconductor base is silicon substrate, the parameter of the anisotropic dry etch process
Including：Etching gas includes Cl2, HBr or Cl2With the mixed gas of HBr, the Cl2, HBr for being performed etching to silicon substrate,
The flow of HBr be 200 standard milliliters it is per minute~800 standard milliliters are per minute, Cl2Flow be 20sccm~100sccm；Partially
It sets power and is more than 100W, bias voltage is more than 10V, and pressure is the millitorr of 2 millitorrs~200, and temperature is 40 DEG C~100 DEG C.
In the present embodiment, etching gas further includes carbon fluorine gas, and the carbon fluorine gas includes CF4、CHF3、CH2F2、CH3In F
It is one or more, for etching the device layer and semiconductor base, the flow of the carbon fluorine gas is the carbon fluorine gas
50sccm~100sccm.The etching gas can also include O2, the flow of oxygen is 50sccm~100sccm, O2For disappearing
Consumption carbon fluorine gas is formed by polymer, and the polymeric layer can be attached to the etching through hole sidewall surfaces in etching process, right
It etches the default through-hole side wall formed and the angle on 200 surface of substrate is regulated and controled.The etching gas can also include carrier gas,
In the present embodiment, the carrier gas is inert gas, and the flow of the carrier gas is 50sccm~1000sccm.
In the present embodiment, due to before forming the default through-hole 201, subtracting to the first surface 210 of substrate 200
It is thin, and form weld pad 221 in the second surface 220, then 201 bottom-exposed of default through-hole for etching formation goes out the weld pad
221 so that be subsequently formed and can be in contact with the weld pad 221 in the conductive layer in buffering opening and through-hole.
Referring to FIG. 6, removing the part mask layer 202 around the default through-hole 201, the default through-hole is exposed
200 surface of section substrate around 201 makes the dimension of picture that the mask open 203 is projected on 200 surface of substrate increase.
In the present embodiment, by increasing the size of the mask open 203, after so that the mask layer 202 is used as
Continuous etching forms the mask of buffering opening, and essence can be carried out to the increased size of institute by increasing 203 dimension process of mask open
True regulation and control, so as to keep the top dimension for being subsequently formed by buffering opening accurate.And if directly forming default through-hole
After 201, the mask for etching buffering opening is formed, then is limited to the limitation of photoetching process alignment precision, the mask holds
Easily and deviation occurs for the position of the default through-hole 201, then influences the pattern for being subsequently formed by buffering opening and through-hole, right
The effect for the conductive ply stress that the buffering opening dispersion is subsequently formed causes harmful effect.Therefore, by straight in the present embodiment
The size for expanding mask open 203 is connect, so that the mask layer 202 can be as the mask of the follow-up buffering opening of etching.
The technique for removing the part mask layer 202 around the default through-hole 201 is isotropic dry etching
Technique or isotropic wet-etching technology.Since etch rate of isotropic etching technics in all directions is identical,
In order to avoid after expanding the mask open 203, the mask layer 202 is also removed simultaneously, the thickness of the mask layer 202
Degree needs to be more than 203 widened size of the mask open.In the present embodiment, the side wall of the mask open 203 is described in
The distance of 201 side wall of default through-hole is 1 micron~20 microns, that is, arrives through-hole side wall at the top of the buffering opening sidewalls being subsequently formed
Distance is 5 microns~20 microns.And isotropic etching technics can accurately control etch thicknesses, so as to institute
It states 203 widened size of mask open to be regulated and controled, to the top dimension for the buffering opening that control is subsequently formed.
In the present embodiment, the mask layer 202 is photoresist layer；The etching of isotropic dry etch process
Gas includes oxygen-containing gas, and the oxygen-containing gas includes O2Or O3, the flow of the oxygen-containing gas is 10sccm~100sccm, partially
It sets power and is less than 100W, bias voltage is less than 10V；The wet-etching technology can be the wet method degumming process of photoresist.
Referring to FIG. 7, after removing the part mask layer 202 around the default through-hole 201 (as shown in Figure 6), with
The mask layer 202 is mask, etches the substrate 200, and buffering opening 204 is formed in the substrate 200, is located at described slow
The default through-hole 201 for washing 204 bottom of mouth open forms the through-hole 201a, and the side wall of the buffering opening 204 is relative to substrate 200
Surface tilts, and the top dimension of the buffering opening 204 is more than bottom size.
The through-hole 201a of the buffering opening 204 and bottom is used to form through-silicon via structure.When subsequently in the substrate
The side wall and bottom surface on 200 surfaces, the sidewall surfaces of buffering opening 204 and the through-hole 201a are formed after conductive layer, by
It is tilted relative to 200 surface of substrate in the side wall of the buffering opening 204, and the top dimension of the buffering opening 204 is more than
Bottom size can avoid constituting apex angle between 200 surface of the substrate and the side wall of through-hole 201a so that be easy accumulation and top
Stress at angle is disperseed, to avoid in the vertex cumulative stress constituted.If the vertex cumulative stress, when follow-up
After the first surface 210 of the substrate 200 and the sidewall bottom surface of default through-hole 201 form the first insulating layer, by
It is relatively thin in the first thickness of insulating layer for being formed in the vertex, and the stress of vertex accumulation can discharge, to hold
Easily lead to the first insulating layer generation fracture (crack) for being covered in the vertex.And once first insulating layer occurs to break
It splits, subsequently after first surface of insulating layer forms conductive layer, the material of the conductive layer can directly be sent out with the substrate
Raw contact, so as to cause short circuit occurs between conductive layer and substrate 200.Therefore, because formed the buffering be open 204 it
Afterwards, the stress for accumulating on vertex can be disperseed, so as to avoid first time insulating layer from being broken, avoid being subsequently formed
Short circuit occurs between conductive layer and substrate 200.
Since the sidewall direction and the side wall on 200 surface of substrate and through-hole 201a of the buffering opening 204 are all different,
So that the stress of 204 sidewall surfaces of the buffering opening is formed in, with 200 surface of substrate and the stress side of through-hole 201a side walls
To being all different, so that stress does not concentrate on the vertex.
In the present embodiment, the sidewall surfaces of the buffering opening 204 are plane；In another embodiment, the buffering
The sidewall surfaces of opening are arc surface outstanding.The dispersion that the buffering opening 204 is conducive to stress is formed, avoids described the
One insulating layer is broken due to by excessive stress, to ensure that the electric isolution performance between conductive layer and substrate 200
Stablize, avoid that short circuit occurs between conductive layer and substrate 200, to ensure that the performance for being formed by through-silicon via structure it is stable,
Reliability improves.
The technique for forming the buffering opening 204 is anisotropic dry etch process.Due in the mask layer 202
203 size of mask open be extended, 200 surface of section substrate of the default through-hole 201 is exposed, along the mask layer
202 pairs of substrates 200 perform etching, and can make the side wall for being formed by buffering 204 side walls of opening along the mask open 203
Extend to the side wall of the default through-hole 201, to form the buffering opening 204 of sidewall slope.
The side wall of the buffering opening 204 is 30 °~70 ° relative to the inclined angle in 200 surface of substrate；The buffering is opened
The depth of mouth 204 is 5 microns~50 microns.Preferably, the side wall of the buffering opening 204 is tilted relative to 200 surface of substrate
Angle be 60 °~70 °；The depth of the buffering opening 204 is 5 microns~20 microns.
The sidewall slope angle of the buffering opening 204 determines the ability of dispersive stress；If the buffering opening 204
Side wall is smaller relative to 200 surface slope of substrate, then buffering 204 side walls of opening to the apex angle between through-hole 201a side walls
It is easy to happen cumulative stress；If the side wall of the buffering opening 204 is larger relative to 200 surface slope of substrate, described slow
The apex angle for washing 204 side wall of mouth to 200 surface of substrate open, which is appointed, is easy to happen cumulative stress.Therefore, it is necessary to buffering opening 204
Side wall is adjusted relative to the angle of inclination on 200 surface of substrate, so that there is buffering opening 204 good stress to disperse
Effect.
The anisotropic dry etch process includes：Bias power is more than 100W, and bias voltage is more than 10V, pressure
For the millitorr of 2 millitorrs~200；Etching gas includes carbon fluorine gas, the carbon fluorine gas can substrate 200 is performed etching it is same
When, polymeric layer is formed in the sidewall surfaces that etching is formed, the carbon fluorine gas includes CF4、CHF3、CH2F2、CH3One kind in F
Or it is a variety of, the flow of the carbon fluorine gas is 50sccm~100sccm；The etching gas can also include O2, O2Flow be
50sccm~100sccm, the O2It is formed by polymer for consuming carbon fluorine gas；The etching gas can also include carrying
Gas, the carrier gas are inert gas, and the flow of the carrier gas is 50sccm~1000sccm.By adjust the carbon fluorine gas with
O2Ratio between gas, can be open to the buffering that etching is formed inclination angle of 204 sidewall surfaces relative to 200 surface of substrate
Degree is regulated and controled.
Referring to FIG. 8, in 200 surface of the substrate, the side of buffering 204 sidewall surfaces of opening and the through-hole 201a
Wall surface forms the first insulating layer 205.
In the present embodiment, it before forming first insulating layer 205, removes the mask layer 202 and (please refers to figure
7)；The technique for removing the mask layer 202 can be wet-etching technology or dry etch process.
First insulating layer 205 between the conductive layer and substrate 200 being subsequently formed for being electrically isolated.Described
One insulating layer, 205 material is one or more combinations in silica, silicon nitride, silicon oxynitride；First insulating layer 205
Formation process is chemical vapor deposition method, physical gas-phase deposition or atom layer deposition process.
In the present embodiment, in order to make the conductive layer being subsequently formed be in contact with the weld pad 221, etching removal institute is needed
205 material of the first insulating layer of part of the bottoms through-hole 201a is stated, and exposes 221 surface of the weld pad, is carrying out the etching
Before technique, the graphical photoresist layer for the first insulating layer 205 for exposing 221 surface of weld pad can be formed, with the figure
It is the first insulating layer 205 described in mask etching to change photoresist layer, and after exposing weld pad 221, removes the graphical light
Photoresist layer.
Referring to FIG. 9, forming conductive layer 206 in the bottom surface of 205 surface of the first insulating layer and through-hole 201a.
In the present embodiment, the conductive layer 206 is not filled by completely 204 and through-hole 201a of the buffering opening.In another reality
It applies in example, 204 and through-hole 201a of the full buffering opening of conductive layer filling.
The conductive layer 206 runs through the substrate 200, for the conducting wire being connect with weld pad 221 to be drawn out to substrate
On 200 first surfaces 210, so that the envelope subsequently after the first surface 210 of substrate 200 carries out plant ball and carries out in processing procedure is surveyed.
In the present embodiment, the formation process of the conductive layer 206 includes：In 205 surface of the first insulating layer and through-hole
The bottom surface of 201a forms conductive film；Technique is patterned to the conductive film, until exposing positioned at substrate 200 first
First insulating layer, 205 surface on surface 210 forms the conductive layer 206, and the conductive layer 206 forms wiring.
The material of the conductive layer 206 is one or more combinations in copper, tungsten, aluminium, titanium, tantalum, titanium nitride, tantalum nitride；
The formation process of the conductive film includes chemical vapor deposition method, physical gas-phase deposition, electroplating technology or chemical plating work
Skill.In the present embodiment, the material of the conductive film is copper, and the formation process of the conductive film is electroplating technology, the plating
Technique includes：Seed layer is formed in the bottom surface of 205 surface of the first insulating layer and through-hole 201a using depositing operation；Using electricity
Depositing process grows conductive material in seed layer surface, forms conductive film.
Since the side wall of the buffering opening 204 is tilted relative to 200 surface of substrate so that the buffering opening 204
Side wall can dispersive stress, the stress being subject to so as to avoid first insulating layer 205 accumulates, described to ensure that
First insulating layer 205 will not be broken because of excessive stress, then the electric isolating effect by first insulating layer 205 is steady
Fixed, the conductive layer 206 will not be in contact with substrate 200, then will not be occurred between the conductive layer 206 and substrate 200 short
It connects.
Being patterned technique to the conductive film includes：It is formed graphically in the conductive film surface using photoetching process
Photoresist layer；Using the graphical photoresist layer as mask, the conductive film is etched using anisotropic dry etch process,
Until exposing 200 first surface 210 of substrate.
Referring to FIG. 10, forming the anti-of 204 and through-hole 201a of the full buffering opening of filling on 206 surface of the conductive layer
Layer 207, the soldermask layer 207 expose 206 surface of partial electroconductive layer.
In the present embodiment, 206 surface of the conductive layer is also formed with 204 and through-hole 201a of the full buffering opening of filling
Soldermask layer 207.The material of the soldermask layer 207 is polymer material or inorganic insulating material, and the polymer material can
For insulating resin, the inorganic insulating material can be silica, silicon nitride or silicon oxynitride.
The soldermask layer 207 is for protecting by the conductive layer 206 and the first insulating layer 205；And the soldermask layer 207 is sudden and violent
206 surface of conductive layer of exposing is subsequently used for the technique for carrying out welding tin ball.In addition, the soldermask layer 207 also helps fixation
And protect the conductive layer 206 and the first insulating layer 205.
1 is please referred to Fig.1, soldered ball 208 is formed on 206 surface of conductive layer exposed.
The conductive layer 206 is by patterning process and forms wiring, and the soldered ball 208 is located at first surface
210 206 surface of conductive layer, the soldered ball 208 can be used in subsequent encapsulation and test.The etching soldermask layer 207
Technique is anisotropic dry etch process；The technique for forming the soldered ball 208 is to plant ball technique.
To sum up, in the present embodiment, formation through-hole is gentle in substrate washes mouth open, and the buffering opening is located at the through-hole top
Portion, and the side wall of the buffering opening is tilted relative to substrate surface, the top dimension of the buffering opening is more than bottom size.
When subsequently it is described buffering opening sidewalls surface and the through-hole side wall and bottom surface formed the first insulating layer, and
First surface of insulating layer is formed after conductive layer, since the substrate surface is described slow to having between the through-hole side wall
The side wall for washing mouth open carries out excessively, and the side wall of the buffering opening is tilted relative to the substrate surface, therefore, the buffering
The stress on opening sidewalls surface is disperseed, and is accumulated between substrate surface and through-hole side wall so as to avoid stress, then
First insulating layer is avoided to be broken due to by excessive stresses so that the electric isolating effect between the conductive layer and substrate is steady
It is fixed.Performance stabilization, the reliability for being formed by through-silicon via structure improve.
Correspondingly, the embodiment of the present invention also provide it is a kind of through-silicon via structure is formed by using the above method, continuing with ginseng
Figure 11 is examined, including：Substrate 200；Through-hole (not shown) in the substrate 200；Buffering in the substrate 200 is opened
Mouth (not shown), the buffering opening are located at the via top, and the side wall of the buffering opening inclines relative to 200 surface of substrate
Tiltedly, and the top dimension of the buffering opening is more than bottom size；Positioned at the buffering opening sidewalls surface and the through-hole
Side wall and bottom surface the first insulating layer 205；Conductive layer 206a positioned at 205 surface of the first insulating layer
It is described in detail below with reference to attached drawing.
There is the substrate 200 opposite first surface 210 and second surface 220, the buffering open top to be located at institute
State the first surface 210 of substrate 200.
The substrate 200 includes semiconductor base.In the present embodiment, the substrate 200 further includes positioned at semiconductor-based
The first surface 210 of the device layer that bottom includes, the substrate 200 is non-device layer surface；It include device junction in the device layer
Structure, conductive structure and the dielectric layer for surrounding the device architecture and conductive structure.In other embodiments, the substrate 200
It can also be only the semiconductor base.
The semiconductor base include silicon substrate, silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator substrate, on insulator
Germanium substrate, glass substrate or III-V compound substrate (such as gallium nitride substrate or gallium arsenide substrate etc.).
The device architecture includes gate structure, fuse-wires structure, electric resistance structure, capacitance structure, the induction structure of transistor
In it is one or more.The dielectric layer is located at the semiconductor substrate surface, and the dielectric layer covers the device architecture,
For making to be electrically isolated from each other between the device architecture and conductive structure；The material of the dielectric layer is silica, silicon nitride, nitrogen
It is one or more in silica, low-K dielectric material, ultralow K dielectric materials.The conductive structure is used to make between device architecture
Realize and be electrically interconnected, the material of the conductive structure includes metal or metallic compound, such as copper, tungsten, aluminium, titanium, nickel, titanium nitride and
One or more combinations in tantalum nitride.The conductive structure includes：Positioned at semiconductor substrate surface or device architecture surface
Conductive plunger and the electrical interconnection line at the top of conductive plunger, the electrical interconnection line realize electricity for making between conductive plunger
Connection, the needs of the conductive layer 206 are connected with the conductive structure.
The second surface 220 of the substrate 200 exposes 206 surface of the conductive layer.In the present embodiment, the substrate
200 second surfaces 220 also have the weld pad 221 positioned at 206 surface of conductive layer；The substrate 200 and 221 surface of weld pad have blunt
Change layer 222.The material of the weld pad 221 includes one or more combinations in copper, tungsten, aluminium, titanium, nickel, titanium nitride and tantalum nitride；
The material of the passivation layer 222 is inorganic insulating material or insulating material of polymer；The inorganic insulating material include silica,
It is one or more in silicon nitride, silicon oxynitride.
In one embodiment, there is second insulating layer between the second surface and weld pad of the substrate, described second absolutely
The material of edge layer is insulating materials, and the second insulating layer is for making to be electrically isolated between the weld pad and substrate
There is through-silicon via structure in the through-hole of the buffering opening and bottom, since the side wall of the buffering opening is opposite
It is tilted in 200 surface of substrate, and the top dimension of the buffering opening is more than bottom size, can avoid 200 table of the substrate
Apex angle is constituted between face and the side wall of through-hole, to the top for avoiding stress from being constituted on 200 surface of the substrate and through-hole side wall
It is accumulated at angle；And the sidewall direction and the side wall on 200 surface of substrate and through-hole due to the buffering opening are all different so that
Stress is disperseed, and is avoided first insulating layer 205 and is broken due to by excessive cumulative stress, is led to ensure that
Electric isolution performance between electric layer 206 and substrate 200 is stablized, and avoids that short circuit occurs between conductive layer 206 and substrate 200, to
It ensure that the performance stabilization, the reliability that are formed by through-silicon via structure improve.
The side wall of the buffering opening is 30 °~70 ° relative to the inclined angle in 200 surface of substrate；The buffering opening
Depth be 5 microns~50 microns.Preferably, the side wall of the buffering opening is relative to the inclined angle in 200 surface of substrate
60 °~70 °；The depth of the buffering opening is 5 microns~20 microns.The sidewall slope angle of the buffering opening, which determines, answers
The dispersibility of power；If the side wall of the buffering opening is smaller relative to 200 surface slope of substrate, the buffering open side
Wall is easy to happen cumulative stress to the apex angle between through-hole side wall；If the side wall of the buffering opening is relative to 200 surface of substrate
Gradient is larger, then the apex angle on buffering opening sidewalls to 200 surface of substrate is still easy to happen cumulative stress.Therefore, it is necessary to
The buffering opening sidewalls are adjusted relative to the angle of inclination on 200 surface of substrate, so that buffering opening is with good
Good stress dispersion effect.
First insulating layer, 205 material is one or more combinations in silica, silicon nitride, silicon oxynitride；It is described
The material of conductive layer 206 is one or more combinations in copper, tungsten, aluminium, titanium, tantalum, titanium nitride, tantalum nitride.
In the present embodiment, the conductive layer 206 is not filled by the completely described buffering opening and through-hole, 206 table of the conductive layer
Also there is the soldermask layer 207 of filling full the buffering opening and through-hole, the soldermask layer 207 to expose partial electroconductive layer 206 in face
Surface；206 surface of conductive layer that the soldermask layer 207 exposes has soldered ball 208.In another embodiment, the conductive layer
The full buffering opening of filling and through-hole.
To sum up, have through-hole is gentle to wash mouth open in the present embodiment, in the substrate, the buffering opening is located at the through-hole
Top, and the side wall of the buffering opening is tilted relative to substrate surface, the top dimension of the buffering opening is more than bottom ruler
It is very little.The side wall and bottom surface of the buffering opening sidewalls surface and the through-hole have the first insulating layer and conductive layer,
Since the substrate surface is excessive to having the side wall of the buffering opening to carry out between the through-hole side wall, and the buffering is opened
The side wall of mouth is tilted relative to the substrate surface, and therefore, the stress on the buffering opening sidewalls surface is disperseed, to avoid
The stress is accumulated between substrate surface and through-hole side wall, then avoids first insulating layer because being answered by excessive
Power and be broken so that electric isolating effect between the conductive layer and substrate is stablized.The performance of the through-silicon via structure is stable, can
It is improved by property.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (16)
1. a kind of forming method of through-silicon via structure, which is characterized in that including：
Semiconductor base is provided, a surface of the semiconductor base is formed with weld pad；
Formation through-hole is gentle in the semiconductor base washes mouth open, and the bottom-exposed of the through-hole goes out the upper table of the weld pad
Face, the buffering opening are located at the via top, and the side wall of the buffering opening is tilted relative to substrate surface, and described slow
The top dimension for washing mouth open is more than bottom size, tired to avoid stress from occurring between semiconductor substrate surface and through-hole side wall
Product；
The first insulating layer is formed in the sidewall surfaces of the buffering opening sidewalls surface and the through-hole；
Conductive layer is formed in first surface of insulating layer and the weld pad upper surface exposed.
2. the forming method of through-silicon via structure as described in claim 1, which is characterized in that the substrate has opposite first
The top of surface and second surface, the buffering opening is located at the first surface of the substrate.
3. the forming method of through-silicon via structure as claimed in claim 2, which is characterized in that further include：Forming the conduction
After layer, the first surface of the substrate is thinned, until exposing the conductive layer surface.
4. the forming method of through-silicon via structure as described in claim 1, which is characterized in that the gentle shape for washing mouth open of the through-hole
Include at method：Mask layer is formed in the substrate surface, the mask open in the mask layer is projected on the figure of substrate surface
The shape and position consistency of shape and the default via top being subsequently formed；Using the mask layer as mask, the substrate is etched,
It is formed in the substrate and presets through-hole, and mask layer is formed in the substrate surface, the side wall of the default through-hole is perpendicular to institute
State substrate surface, there is the mask open for exposing the default through-hole in the mask layer, the side wall of the mask open with
The side wall of the default through-hole flushes；The part mask layer around the default through-hole is removed, the default through-hole week is exposed
The section substrate surface enclosed makes the dimension of picture that the mask open is projected on substrate surface increase；It is described default logical removing
After part mask layer around hole, using the mask layer as mask, the substrate is etched, buffering is formed in the substrate and opens
Mouthful, the default through-hole positioned at the buffering open bottom forms the through-hole.
5. the forming method of through-silicon via structure as claimed in claim 4, which is characterized in that the mask layer includes photoresist
Layer.
6. the forming method of through-silicon via structure as claimed in claim 4, which is characterized in that the removal default through-hole week
The technique of the part mask layer enclosed is isotropic dry etch process or isotropic wet-etching technology.
7. the forming method of through-silicon via structure as claimed in claim 4, which is characterized in that the technique for forming the buffering opening
For anisotropic dry etch process.
8. the forming method of through-silicon via structure as described in claim 1, which is characterized in that first insulating layer and conductive layer
Formation process include：First is formed in the sidewall surfaces of the substrate surface, buffering opening sidewalls surface and the through-hole
Insulating layer；Conductive film is formed in the bottom surface of first surface of insulating layer and through-hole；The conductive film is patterned
Technique, and the first insulating layer positioned at substrate surface is exposed, the conductive layer is formed, and the conductive layer forms circuit cloth
Line.
9. the forming method of through-silicon via structure as claimed in claim 8, which is characterized in that the conductive film filling is not filled by
The full buffering opening and through-hole；After being patterned technique to the conductive film, in the conductive layer and the first insulating layer
Surface forms soldermask layer.
10. a kind of through-silicon via structure, which is characterized in that including：
One surface of semiconductor base, the semiconductor base is formed with weld pad；
Through-hole in the semiconductor base, the bottom-exposed of the through-hole go out the upper surface of the weld pad；
Buffering opening in the semiconductor base, the buffering opening are located at the via top, the buffering opening
Side wall relative to substrate surface tilt, and it is described buffering opening top dimension be more than bottom size, to avoid stress from existing
It is accumulated between semiconductor substrate surface and through-hole side wall；
Positioned at the buffering opening sidewalls surface and the first insulating layer of the sidewall surfaces of the through-hole；
Conductive layer positioned at first surface of insulating layer and the weld pad upper surface exposed.
11. through-silicon via structure as claimed in claim 10, which is characterized in that the substrate has opposite first surface and the
The top on two surfaces, the buffering opening is located at the first surface of the substrate.
12. through-silicon via structure as claimed in claim 11, which is characterized in that the second surface of the substrate exposes described lead
Electric layer surface.
13. through-silicon via structure as claimed in claim 10, which is characterized in that the substrate includes semiconductor base.
14. through-silicon via structure as claimed in claim 13, which is characterized in that the substrate further includes：Positioned at semiconductor base
Including device layer, the second surface of the substrate is device layer surface, includes device architecture, conductive knot in the device layer
Structure and the dielectric layer for surrounding the device architecture and conductive structure.
15. through-silicon via structure as claimed in claim 10, which is characterized in that the side wall of the buffering opening is relative to substrate table
The inclined angle in face is 30 °~70 °；The depth of the buffering opening is 5 microns~50 microns.
16. through-silicon via structure as claimed in claim 10, which is characterized in that the conductive layer filling is not filled by completely described slow
Wash mouth and through-hole open, the conductive layer surface also has soldermask layer.
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| CN109817531B (en) * | 2019-02-02 | 2021-03-12 | 合肥鑫晟光电科技有限公司 | Array substrate and manufacturing method thereof |
| CN110867432A (en) * | 2019-11-28 | 2020-03-06 | 苏州晶方半导体科技股份有限公司 | Chip packaging structure and packaging method |
| CN115172270A (en) * | 2022-07-26 | 2022-10-11 | 华进半导体封装先导技术研发中心有限公司 | Silicon through hole structure and manufacturing method thereof |
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