CN106229272A - Wafer stage chip encapsulation method and structure - Google Patents
Wafer stage chip encapsulation method and structure Download PDFInfo
- Publication number
- CN106229272A CN106229272A CN201610708182.7A CN201610708182A CN106229272A CN 106229272 A CN106229272 A CN 106229272A CN 201610708182 A CN201610708182 A CN 201610708182A CN 106229272 A CN106229272 A CN 106229272A
- Authority
- CN
- China
- Prior art keywords
- insulating barrier
- hole
- wafer
- metal gasket
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
Abstract
The invention discloses wafer stage chip encapsulation method and structure.The method includes: providing wafer, this wafer has first surface and the second surface relative with first surface, and second surface is provided with the first insulating barrier；This wafer includes multiple chip unit, and each chip unit is provided with some metal gaskets at described first insulating barrier away from the side of described second surface；First surface at this wafer forms the through hole arriving at described first insulating barrier, exposes described first insulating barrier, and described metal gasket is in the underface of described through hole；Etch described first insulating barrier between described through hole and metal gasket, expose metal gasket；Formed and cover described through hole and the second insulating barrier of described wafer first surface；Photoetching or etch described second insulating barrier of described through hole bottom surface, exposes described metal gasket.The wafer stage chip encapsulation method of present invention offer and structure, to metal gasket without destroying, it is possible to achieve wire contacts with the face of metal gasket, improves signal stabilization.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to wafer stage chip encapsulation method and structure.
Background technology
When chip is packaged by existing Wafer level packaging, silicon through hole technology is typically utilized to carry out circuit interconnection,
This technology uses the mode of laser boring to be punched by the insulating barrier on chip metal liner mostly, and recycling metal reroutes technology
Signaling point on metal gasket is guided on surface.Also can be by gold while the insulating barrier on metal gasket being punched due to laser
Belong to liner to puncture, punch metal gasket and be easily caused the problems such as chip reliability difference, sealed by laser boring mode in addition
During dress wire with the metal pad on wafer be point cantact, signal stabilization is poor.
Summary of the invention
In view of this, the embodiment of the present invention provides wafer stage chip encapsulation method and structure, to metal gasket without destroying, and can
To realize wire with the face contact of metal gasket, raising signal stabilization.
First aspect, the embodiment of the present invention provides a kind of wafer stage chip encapsulation method, including:
Step 110, offer wafer, described wafer has first surface and the second surface relative with first surface, institute
State second surface and be provided with the first insulating barrier；Described wafer includes multiple chip unit, and each described chip unit is described
One insulating barrier is provided with some metal gaskets away from the side of described second surface；
Step 120, formed at the first surface of described wafer and arrive at the through hole of described first insulating barrier, expose described first
Insulating barrier, described metal gasket is in the underface of described through hole；
Step 130, described first insulating barrier etched between described through hole and described metal gasket, expose described metal liner
Pad；
Step 140, formation cover described through hole and the second insulating barrier of described wafer first surface；
Step 150, photoetching or etch described second insulating barrier of described through hole bottom surface, expose described metal gasket；
Step 160, sequentially forming metal wiring layer and solder mask, described metal wiring layer is electrical with described metal gasket
Connect.
Preferably, described step 130 includes:
Remove described first insulating barrier between described through hole and described metal gasket by dry etch process, expose institute
State metal gasket.
Preferably, described second insulating barrier can be inorganic insulating material or organic insulation, and described step 150 is wrapped
Include:
Removed described second insulating barrier of described through hole bottom surface by dry etch process or wet-etching technology, expose institute
State metal gasket.
Preferably, described second insulating barrier is sensitive material, and described step 150 includes:
Removed described second insulating barrier of described through hole bottom surface by photoetching process, expose described metal gasket.
Preferably, it is characterised in that described first insulating barrier is SiO2, described second insulating barrier is photosensitive resin photoetching
Glue.
Second aspect, the embodiment of the present invention provides a kind of wafer stage chip encapsulation method, including:
Step 210, offer wafer, described wafer has first surface and the second surface relative with first surface, institute
State second surface and be provided with the first insulating barrier；Described wafer includes multiple chip unit, and each described chip unit is described
One insulating barrier is provided with some metal gaskets away from the side of described second surface；
Step 220, formed at the first surface of described wafer and arrive at the through hole of described first insulating barrier, expose described first
Insulating barrier, described metal gasket is positioned at immediately below the correspondence of described through hole；
Step 230, formation cover the second insulating barrier of the first surface of described through hole and described wafer；
Step 240, photoetching or etch described second insulating barrier of described through hole bottom surface, expose described first insulating barrier；
Step 250, etch described first insulating barrier of described through hole bottom surface, expose described metal gasket；
Step 260, sequentially forming metal wiring layer and solder mask, described metal wiring layer is electrical with described metal gasket
Connect.
Preferably, described second insulating barrier is inorganic insulating material or organic insulation, and described step 240 includes:
Removed described second insulating barrier of described through hole bottom surface by dry etch process or wet-etching technology, expose institute
State the first insulating barrier.
Preferably, described second insulating barrier is sensitive material, and described step 240 includes:
Removed described second insulating barrier of described through hole bottom surface by photoetching process, expose described first insulating barrier.
Preferably, described first insulating barrier is SiO2, described second insulating barrier is photosensitive resin photoresist.
The third aspect, the embodiment of the present invention provides a kind of wafer stage chip encapsulating structure, including:
Wafer, described wafer has first surface and the second surface relative with first surface, on described second surface
It is coated with the first insulating barrier；Described wafer includes multiple chip unit, and each described chip unit is remote at described first insulating barrier
The side of described second surface is provided with some metal gaskets；Described first insulating barrier has multiple hatch frame, described in open
Mouth structure exposes described metal gasket；Described first surface has multiple through hole, and described through hole is corresponding with described hatch frame to be set
Putting, and expose described metal gasket, described metal gasket is immediately below the correspondence of described through hole；The sidewall of described through hole and institute
Stating first surface and be coated with the second insulating barrier, above described second insulating barrier and the bottom of described through hole is coated with metal successively
Wiring layer and solder mask, described metal wiring layer is electrically connected with described metal gasket；Described second insulating barrier is photosensitive material
Material.
The embodiment of the present invention, by forming described through hole at wafer first surface, removes through hole by photoetching or etching technics
The first insulating barrier between bottom surface and metal gasket and the second insulating barrier, expose metal gasket, logical compared in prior art
Cross laser boring and remove the mode of metal gasket overlying insulating layer, can avoid, when removing insulating barrier, destroying metal gasket very
To the problem that metal gasket is punched.Owing to removing first between through hole bottom surface and metal gasket by photoetching or etching technics
Insulating barrier and the second insulating barrier are to metal gasket without destroying, and therefore the metal wiring layer of subsequent deposition can be formed with metal gasket
Face contacts, it is to avoid the situation of loose contact so that more stable at the signal of telecommunication of the integrated described chip unit of crystal column surface, increases
Strong chip reliability.
Accompanying drawing explanation
The schematic flow sheet of a kind of wafer stage chip encapsulation method that Fig. 1 provides for the embodiment of the present invention one；
Fig. 2 a-2f is section corresponding to each step of a kind of wafer stage chip encapsulation method that the embodiment of the present invention one provides
Figure；
The schematic flow sheet of a kind of wafer stage chip encapsulation method that Fig. 3 provides for the embodiment of the present invention two；
Profile corresponding to each step of a kind of wafer stage chip encapsulation method that Fig. 4 a-4f embodiment of the present invention two provides.
Detailed description of the invention
The present invention is described in further detail with embodiment below in conjunction with the accompanying drawings.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention, rather than limitation of the invention.It also should be noted that, in order to just
Part related to the present invention is illustrate only rather than entire infrastructure in description, accompanying drawing.
Embodiment one
The schematic flow sheet of a kind of wafer stage chip encapsulation method that Fig. 1 provides for the embodiment of the present invention one, Fig. 2 a-2f is
Profile corresponding to each step of a kind of wafer stage chip encapsulation method that the embodiment of the present invention one provides.See Fig. 1, described method
Comprise the following steps:
Step 110, offer wafer, described wafer has first surface and the second surface relative with first surface, institute
State second surface and be provided with the first insulating barrier；Described wafer includes multiple chip unit, and each described chip unit is described
One insulating barrier is provided with some metal gaskets away from the side of described second surface.
Referring to Fig. 2 a, wafer 10 has first surface 100 and the second surface 200 relative with first surface 100.The
Two surfaces 200 are provided with the first insulating barrier 101.Wafer 10 includes multiple chip unit (not shown), and each chip unit is
One insulating barrier 101 is provided with some metal gaskets 102 away from the side of second surface 200.Wafer 10 can be silicon, germanium or its
Its semiconductor substrate materials.First insulating barrier 101 can be at the second surface 200 of wafer 10 by oxidation or depositing technics
Formed.
Alternatively, the first insulating barrier 101 can be SiO2.When the first insulating barrier 101 is SiO2Time, SiO2Can be raw by heat
Long or deposit mode generates.Thermally grown technique i.e. is allowed to react with wafer (such as silicon chip) by being externally supplied high purity oxygen gas,
Forming layer of oxide layer at silicon chip surface, this oxide layer is the first insulating barrier 101.Deposit is i.e. by being externally supplied oxygen and silicon
Source, makes them react in cavity, thus forms layer of oxide layer thin film, the i.e. first insulating barrier 101 at silicon chip surface.
Step 120, formed at the first surface of described wafer and arrive at the through hole of described first insulating barrier, expose described first
Insulating barrier, described metal gasket is in the underface of described through hole.
Seeing Fig. 2 b, the first surface 100 at wafer 10 forms the through hole 103 arriving at the first insulating barrier 101.Through hole 103
Exposing the first insulating barrier 101, metal gasket 102 is in the underface of through hole 103.Through hole 103 such as can by continuous photoetching and
Deep reaction ion etching technique is formed.Alternatively, through hole 103 can be stairstepping through hole or columnar through holes.If ladder
Shape through hole, can first open slot-like opening, then open circular hole opening bottom slot-like opening again, by two mask plates, twice quarter
Etching technique completes.If columnar through holes needs a mask plate, once etching can complete.If it should be noted that through hole
103 is stairstepping through hole, it is ensured that in the forming process of follow-up each film layer, and the deposition uniformity on through hole 103 sidewall is kept away
Exempt from the problem that through hole 103 causes the partial sidewall of through hole 103 cannot cover subsequent film the most deeply.
Step 130, described first insulating barrier etched between described through hole and described metal gasket, expose described metal liner
Pad.
See Fig. 2 c, the first insulating barrier 101 between etching through hole 103 and metal gasket 102, exposes metal gasket 102.
Due to use etching technics remove through hole 103 and metal gasket 102 between the first insulating barrier 101, thus without destroying metal
Liner 102.
It should be noted that the embodiment of the present invention can remove through hole 103 by dry etching or wet-etching technology
And the first insulating barrier 101 between metal gasket 102, exposes metal gasket 102.Preferably, it is possible to use dry etch process
Remove the first insulating barrier 101 between through hole 103 and metal gasket 102, it is to avoid to core integrated in wafer 10 during wet etching
The corrosion of blade unit.
The first insulating barrier 101 between described through hole 103 and described metal gasket 102 is removed by dry etch process,
Expose described metal gasket 102.When removing the first insulating barrier 101 between through hole 103 and metal gasket 102, it is ensured that do not break
Bad described metal gasket 102.Described dry etch process can utilize electron cyclotron to accelerate oscillating reactions device, reactive ion etching
Reactor, magnetic intensified response ion etching reactor or inductively coupled plasma reactor perform etching, and described dry method is carved
The etching gas of erosion is containing the halogens such as fluorine, chlorine, bromine, iodine or oxygen element or the etching gas of element sulphur.Can be according to
The material of one insulating barrier 101, selects corresponding etching gas.Exemplary, SiO2Material generally uses the quarter of fluorocarbons
Erosion gas.
Step 140, formation cover described through hole and the second insulating barrier of described wafer first surface.
See Fig. 2 d, formed and cover through hole 103 and the second insulating barrier 104 of wafer first surface 100.Second insulating barrier
104 are the electric isolution of the metallic circuit layer in order to realize wafer 10 and subsequent deposition and arrange, it is to avoid metallic circuit layer is direct
Contact with wafer 10 and cause short circuit etc..
Step 150, photoetching or etch described second insulating barrier of described through hole bottom surface, expose described metal gasket.
See the second insulating barrier 104 of Fig. 2 e, photoetching or etching through hole 103 bottom surface, expose metal gasket 102.In order to
Protection metal gasket 102 when removing the second insulating barrier 104, uses the method for photoetching or etching to remove.
Alternatively, described second insulating barrier can be inorganic insulating material (such as SiO2, SiNx etc.) or organic insulation material
Material, can be removed described second insulating barrier of described through hole bottom surface, expose institute by dry etch process or wet-etching technology
State metal gasket.
The second insulating barrier 104 in the present embodiment can also is that sensitive material.Described through hole 103 is removed by photoetching process
Second insulating barrier 104 of bottom surface, exposes metal gasket 102.
Such as can form the second insulating barrier 104 by spin coating proceeding, owing to the second insulating barrier 104 is sensitive material, because of
This can be exposed by having the mask plate of exposure figure, and the exposure figure of mask plate exposes second bottom through hole 103
Insulating barrier 104.Can be exposed by ultraviolet light, the exposure figure of UV light permeability mask plate, be irradiated to the second insulating barrier
On 104, and react.Developing after exposure, the second insulating barrier 104 irradiated by ultraviolet light can be reacted by developing agent
And then dissolved removal, expose metal substrate 102, and leave the second insulating barrier 104 not irradiated by ultraviolet light.Additionally, it is logical
The mode crossing photoetching removes the second insulating barrier 104 of through hole 103 bottom surface, on the one hand will not destroy metal substrate 102, on the other hand
Remove the second insulating barrier 104 of through hole 103 bottom surface compared to dry etching or wet etching, follow-up etching work can be saved
Skill, decreases manufacturing process, improves production efficiency.
Preferably, the second insulating barrier is photosensitive resin photoresist.Photosensitive resin photoresist is that a kind of light sensitive characteristic is good
Photoresist.Photosensitive resin photoresist has good insulating properties, and after photoetching, remaining part need not be peeled off, as isolation crystalline substance
Circle and the insulant of subsequent metal wiring layer, do not interfere with device performance.
Step 160, sequentially forming metal wiring layer and solder mask, described metal wiring layer is electrical with described metal gasket
Connect.
See Fig. 2 f, sequentially form metal wiring layer 105 and solder mask 106, metal wiring layer 105 and metal gasket
102 are electrically connected with.It is alternatively possible to the metal wiring layer on the second insulating barrier 104 can include one or more layers metal.Gold
The preparation technology belonging to wiring layer can be such as magnetron sputtering depositing process.Metal gasket 102 is led to crystalline substance by metal wiring layer 105
The first surface 100 of circle 10.It should be noted that multiple layer metal forms metal wiring layer relatively layer of metal forms metal wiring layer
Can preferably electrically connect with being formed between metal gasket.Exemplarily, at the second insulating layer material 104 surface and through hole
Splash-proofing sputtering metal titanium bottom 103, then sputter layer of metal copper by magnetron sputtering at metallic titanium surface, thus complete metal wiring layer
Making.During due to the first insulating barrier 101 in removing through hole 103 and the second insulating barrier 104, metal gasket is not caused
Damage, therefore form the electrical connection of face contact between metal wiring layer and metal gasket, improve signal stabilization.
The embodiment of the present invention, by forming through hole at wafer first surface, removes through hole bottom surface and metal by etching technics
The first insulating barrier between liner, exposes metal gasket, then makes the second insulating barrier, photoetching or etching through hole bottom surface and metal
The second insulating barrier between liner, exposes metal gasket, finally sequentially forms metal wiring layer and solder mask, makes hardware cloth
Line layer is electrically connected with metal gasket.Owing to removing first between through hole bottom surface and metal gasket by photoetching or etching technics
Insulating barrier and the second insulating barrier are to metal gasket without destroying, and therefore the metal wiring layer of subsequent deposition can be formed with metal gasket
Face contacts, it is to avoid the situation of loose contact so that more stable at the signal of telecommunication of the integrated described chip unit of crystal column surface, increases
Strong chip reliability.The second insulating barrier in the present embodiment can also is that sensitive material.Through hole is removed by the way of photoetching
Second insulating barrier of bottom surface, on the one hand will not destroy metal substrate, on the other hand leads to compared to dry etching or wet etching
Second insulating barrier of bottom surface, hole, can save follow-up etching technics, decrease manufacturing process, improve production efficiency.
Embodiment two
The schematic flow sheet of a kind of wafer stage chip encapsulation method that Fig. 3 provides for the embodiment of the present invention two；Fig. 4 a-4f is originally
Profile corresponding to each step of a kind of wafer stage chip encapsulation method that inventive embodiments two provides.With reference to Fig. 3, described method bag
Include following steps:
Step 210, offer wafer, described wafer has first surface and the second surface relative with first surface, institute
State second surface and be provided with the first insulating barrier；Described wafer includes multiple chip unit, and each described chip unit is described
One insulating barrier is provided with some metal gaskets away from the side of described second surface.
Referring to Fig. 4 a, wafer 20 has first surface 300 and the second surface 400 relative with first surface 300.The
Two surfaces 400 are provided with the first insulating barrier 201.Wafer 20 includes multiple chip unit (not shown), and each chip unit is
One insulating barrier 201 is provided with some metal gaskets 202 away from the side of second surface 400.Wafer 20 can be silicon, germanium or its
Its semiconductor substrate materials.First insulating barrier 201 can be at the second surface 400 of wafer 20 by oxidation or depositing technics
Formed.
Alternatively, the first insulating barrier 201 can be SiO2.When the first insulating barrier 201 is SiO2Time, SiO2Can be raw by heat
Long or deposit mode generates.
Step 220, formed at the first surface of described wafer and arrive at the through hole of described first insulating barrier, expose described first
Insulating barrier, described metal gasket is positioned at immediately below the correspondence of described through hole.
Seeing Fig. 4 b, the first surface 300 at wafer 20 forms the through hole 203 arriving at the first insulating barrier 201.Through hole 203
Exposing the first insulating barrier 201, metal gasket 202 is in the underface of through hole 203.Through hole 103 such as can by continuous photoetching and
Deep reaction ion etching technique is formed.Alternatively, through hole 203 can be stairstepping through hole or columnar through holes.If ladder
Shape through hole, can first open slot-like opening, then open circular hole opening bottom slot-like opening again, by two mask plates, twice quarter
Etching technique completes.If columnar through holes needs a mask plate, once etching can complete.If it should be noted that through hole
203 is stairstepping through hole, it is ensured that in the forming process of follow-up each film layer, and the deposition uniformity on through hole 203 sidewall is kept away
Exempt from the problem that through hole 203 causes the partial sidewall of through hole 203 cannot cover subsequent film the most deeply.
Step 230, formation cover the second insulating barrier of the first surface of described through hole and described wafer.
See Fig. 4 c, formed and cover described through hole 203 and the second insulating barrier 204 of described wafer first surface 300.The
Two insulating barriers 204 are the electric isolution of the metallic circuit layer in order to realize wafer 20 and subsequent deposition and arrange, it is to avoid metal wire
Road floor directly contacts with wafer 20 and causes short circuit etc..
Step 240, photoetching or etch described second insulating barrier of described through hole bottom surface, expose described first insulating barrier.
See the second insulating barrier 204 of Fig. 4 d, photoetching or etching through hole 203 bottom surface, expose the first insulating barrier 201.In order to
Protect the first insulating barrier 201 and metal gasket 202 when removing the second insulating barrier 204, use the method for photoetching or etching to make a return journey
Remove.
Alternatively, described second insulating barrier is electrodeless insulant or organic insulation, by dry etch process or
Wet-etching technology removes described second insulating barrier of described through hole bottom surface, exposes described first insulating barrier.
The second insulating barrier 204 in the present embodiment can also is that sensitive material.Described through hole 103 is removed by photoetching process
Second insulating barrier 204 of bottom surface, exposes the first insulating barrier 201.
Such as can form the second insulating barrier 204 by spin coating proceeding, owing to the second insulating barrier 204 is sensitive material, because of
This can be exposed by having the mask plate of exposure figure, and the exposure figure of mask plate exposes second bottom through hole 203
Insulating barrier 204.Can be exposed by ultraviolet light, the exposure figure of UV light permeability mask plate, be irradiated to the second insulating barrier
On 204, and react.Developing after exposure, the second insulating barrier 204 irradiated by ultraviolet light can be reacted by developing agent
And then dissolved removal, expose the first insulating barrier 201, and leave the second insulating barrier 204 not irradiated by ultraviolet light.Additionally,
By the way of photoetching, remove the second insulating barrier 204 of through hole 203 bottom surface, on the one hand will not destroy the first insulating barrier 201 and gold
Belong to substrate 202, on the other hand compared to dry etching or the second insulating barrier 204, Ke Yijie of wet etching through hole 203 bottom surface
Save follow-up etching technics, decrease manufacturing process, improve production efficiency.
Preferably, the second insulating barrier is photosensitive resin photoresist.Photosensitive resin photoresist is that a kind of light sensitive characteristic is good
Photoresist.Photosensitive resin photoresist has good insulating properties, and after photoetching, remaining part need not be peeled off, as isolation crystalline substance
Circle and the insulant of subsequent metal wiring layer, do not interfere with device performance.
Step 250, etch described first insulating barrier of described through hole bottom surface, expose described metal gasket.
See Fig. 4 e, the first insulating barrier 201 between etching through hole 203 and metal gasket 202, exposes metal gasket 202.
Due to use etching technics remove through hole 203 and metal gasket 202 between the first insulating barrier 201, thus without destroying metal
Liner 202.Preferably, it is possible to use dry etch process removes the first insulating barrier between through hole 203 and metal gasket 202
201, it is to avoid corrosion to chip unit integrated in wafer 10 during wet etching.
Step 260, sequentially forming metal wiring layer and solder mask, described metal wiring layer is electrical with described metal gasket
Connect.
See Fig. 4 f, sequentially form metal wiring layer 205 and solder mask 206, metal wiring layer 205 and metal gasket
202 are electrically connected with.It is alternatively possible to the metal wiring layer on the second insulating barrier 204 can include one or more layers metal.Gold
The preparation technology belonging to wiring layer can be such as magnetron sputtering technique.Metal gasket 202 is led to wafer by metal wiring layer 205
The first surface 300 of 20.It should be noted that multiple layer metal formation metal wiring layer relatively layer of metal formation metal wiring layer can
Electrically connect with being formed between metal gasket with more preferable.Exemplarily, at the second insulating layer material 204 surface and through hole 203
Bottom splash-proofing sputtering metal titanium, then sputter layer of metal copper by magnetron sputtering at metallic titanium surface, thus complete metal wiring layer
Make.During due to the first insulating barrier 201 in removing through hole 203 and the second insulating barrier 204, metal gasket is not caused damage
Bad, therefore form the electrical connection of face contact between metal wiring layer and metal gasket, improve signal stabilization.
The embodiment of the present invention, by forming through hole at wafer first surface, makes the second insulating barrier in through-hole surfaces, passes through
Photoetching or etching technics remove the second insulating barrier between through hole bottom surface and metal gasket and the first insulating barrier, expose metal liner
Pad, is removed by the way of metal gasket overlying insulating layer by laser boring compared in prior art, can avoid removing absolutely
During edge layer, destroy the problem that metal gasket is even punched by metal gasket.Owing to being removed at the bottom of through hole by photoetching or etching technics
The first insulating barrier between face and metal gasket and the second insulating barrier to metal gasket without destroying, the therefore hardware cloth of subsequent deposition
Line layer can form face with metal gasket and contact, it is to avoid the situation of loose contact so that at the described core that crystal column surface is integrated
The signal of telecommunication of blade unit is more stable, enhances chip reliability.The second insulating barrier in the present embodiment can also is that sensitive material.
By the way of photoetching, remove the second insulating barrier of through hole bottom surface, on the one hand will not destroy the first insulating barrier and metal substrate, separately
On the one hand compared to dry etching or the second insulating barrier of wet etching through hole bottom surface, follow-up etching technics can be saved,
Decrease manufacturing process, improve production efficiency.
Embodiment three
Based on same inventive concept, the embodiment of the present invention three provides a kind of wafer stage chip encapsulating structure, and the present invention is real
The wafer stage chip encapsulating structure that executing example three provides may refer to Fig. 2 f or Fig. 4 f.Describe in detail as a example by Fig. 2 f below.
Seeing Fig. 2 f, wafer stage chip encapsulating structure includes wafer 10.Wherein wafer 10 has first surface 100 and and first surface
Relative second surface 200.The first insulating barrier 101 it is coated with on second surface 200.Wafer includes multiple chip unit and (does not shows
Go out), each chip unit is provided with some metal gaskets 102 at the first insulating barrier 101 away from the side of second surface 200.The
One insulating barrier 101 has multiple hatch frame, and hatch frame exposes metal gasket 102.First surface 100 has multiple through hole
103, through hole 103 is correspondingly arranged with hatch frame, and exposes metal gasket 102, metal gasket 102 through hole 103 correspondence just
Lower section.The sidewall of through hole 103 and first surface 100 are coated with the second insulating barrier 104, above the second insulating barrier 104 and logical
The bottom in hole 103 is coated with metal wiring layer 105 and solder mask 106, metal wiring layer 105 and metal gasket 102 electricity successively
Property connect, the second insulating barrier 104 is sensitive material.
It should be noted that the wafer stage chip encapsulating structure described in the embodiment of the present invention can be by any of the above-described wafer scale
Chip packaging method preparation is formed.
Alternatively, described first insulation between described through hole and described metal gasket is removed by dry etch process
Layer, exposes described metal gasket.
Removed described second insulating barrier of described through hole bottom surface by photoetching process, expose described metal gasket.
Alternatively, described second insulating barrier is photosensitive resin photoresist.
The wafer stage chip encapsulating structure that the embodiment of the present invention provides, owing to removing between through hole bottom surface and metal gasket
The first insulating barrier and during the second insulating barrier, metal gasket is not damaged, therefore metal wiring layer can and metal liner
Contact for face between pad, it is to avoid the situation of loose contact so that at the signal of telecommunication of the integrated described chip unit of crystal column surface
More stable, enhance chip reliability.
Note, above are only presently preferred embodiments of the present invention and institute's application technology principle.It will be appreciated by those skilled in the art that
The invention is not restricted to specific embodiment described here, can carry out for a person skilled in the art various obvious change,
Readjust and substitute without departing from protection scope of the present invention.Therefore, although by above example, the present invention is carried out
It is described in further detail, but the present invention is not limited only to above example, without departing from the inventive concept, also
Other Equivalent embodiments more can be included, and the scope of the present invention is determined by scope of the appended claims.
Claims (10)
1. a wafer stage chip encapsulation method, it is characterised in that described method includes:
Step 110, providing wafer, described wafer has first surface and a second surface relative with first surface, and described the
Two surface configurations have the first insulating barrier；Described wafer includes multiple chip unit, and each described chip unit is described first exhausted
Edge layer is provided with some metal gaskets away from the side of described second surface；
Step 120, formed at the first surface of described wafer and arrive at the through hole of described first insulating barrier, expose described first insulation
Layer, described metal gasket is in the underface of described through hole；
Step 130, described first insulating barrier etched between described through hole and described metal gasket, expose described metal gasket；
Step 140, formation cover described through hole and the second insulating barrier of described wafer first surface；
Step 150, photoetching or etch described second insulating barrier of described through hole bottom surface, expose described metal gasket；
Step 160, sequentially forming metal wiring layer and solder mask, described metal wiring layer electrically connects with described metal gasket
Connect.
Method the most according to claim 1, it is characterised in that described step 130 includes:
By dry etch process or wet-etching technology remove between described through hole and described metal gasket described first exhausted
Edge layer, exposes described metal gasket.
Method the most according to claim 1, it is characterised in that described second insulating barrier can be inorganic insulating material or have
Machine insulant, described step 150 includes:
Removed described second insulating barrier of described through hole bottom surface by dry etch process or wet-etching technology, expose described gold
Belong to liner.
Method the most according to claim 1, it is characterised in that described second insulating barrier is sensitive material, described step 150
Including:
Removed described second insulating barrier of described through hole bottom surface by photoetching process, expose described metal gasket.
Method the most according to claim 4, it is characterised in that described second insulating barrier is photosensitive resin photoresist.
6. a wafer stage chip encapsulation method, it is characterised in that described method includes:
Step 210, providing wafer, described wafer has first surface and a second surface relative with first surface, and described the
Two surface configurations have the first insulating barrier；Described wafer includes multiple chip unit, and each described chip unit is described first exhausted
Edge layer is provided with some metal gaskets away from the side of described second surface；
Step 220, formed at the first surface of described wafer and arrive at the through hole of described first insulating barrier, expose described first insulation
Layer, described metal gasket is positioned at immediately below the correspondence of described through hole；
Step 230, formation cover the second insulating barrier of the first surface of described through hole and described wafer；
Step 240, photoetching or etch described second insulating barrier of described through hole bottom surface, expose described first insulating barrier；
Step 250, etch described first insulating barrier of described through hole bottom surface, expose described metal gasket；
Step 260, sequentially forming metal wiring layer and solder mask, described metal wiring layer electrically connects with described metal gasket
Connect.
Method the most according to claim 6, it is characterised in that described second insulating barrier be inorganic insulating material or organic absolutely
Edge material, described step 240 includes:
Removed described second insulating barrier of described through hole bottom surface by dry etch process or wet-etching technology, expose described the
One insulating barrier.
Method the most according to claim 6, it is characterised in that described second insulating barrier is sensitive material, described step 240
Including:
Removed described second insulating barrier of described through hole bottom surface by photoetching process, expose described first insulating barrier.
Method the most according to claim 8, it is characterised in that described second insulating barrier is photosensitive resin photoresist.
10. a wafer stage chip encapsulating structure, it is characterised in that including:
Wafer, described wafer has first surface and the second surface relative with first surface, and described second surface covers
There is the first insulating barrier；Described wafer includes multiple chip unit, each described chip unit at described first insulating barrier away from institute
The side stating second surface is provided with some metal gaskets；Described first insulating barrier has multiple hatch frame, and described opening is tied
Structure exposes described metal gasket；Described first surface has multiple through hole, and described through hole is correspondingly arranged with described hatch frame, and
Exposing described metal gasket, described metal gasket is immediately below the correspondence of described through hole；The sidewall of described through hole and described
One surface is coated with the second insulating barrier, and above described second insulating barrier and the bottom of described through hole is coated with metal line successively
Layer and solder mask, described metal wiring layer is electrically connected with described metal gasket；Described second insulating barrier is sensitive material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610708182.7A CN106229272A (en) | 2016-08-23 | 2016-08-23 | Wafer stage chip encapsulation method and structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610708182.7A CN106229272A (en) | 2016-08-23 | 2016-08-23 | Wafer stage chip encapsulation method and structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106229272A true CN106229272A (en) | 2016-12-14 |
Family
ID=57553012
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610708182.7A Pending CN106229272A (en) | 2016-08-23 | 2016-08-23 | Wafer stage chip encapsulation method and structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106229272A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109273406A (en) * | 2018-09-05 | 2019-01-25 | 苏州科阳光电科技有限公司 | Packaging method of wafer-level chip |
| CN110783264A (en) * | 2019-10-31 | 2020-02-11 | 长江存储科技有限责任公司 | Wafer protection structure and protection method |
| CN110867432A (en) * | 2019-11-28 | 2020-03-06 | 苏州晶方半导体科技股份有限公司 | Chip packaging structure and packaging method |
| CN110911287A (en) * | 2018-09-17 | 2020-03-24 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101774531A (en) * | 2010-01-05 | 2010-07-14 | 上海集成电路研发中心有限公司 | MEMS microbridge structure contact hole preparation method |
| CN101807560A (en) * | 2010-03-12 | 2010-08-18 | 晶方半导体科技（苏州）有限公司 | Packaging structure of semiconductor device and manufacture method thereof |
| CN101800207B (en) * | 2010-03-12 | 2011-10-26 | 苏州晶方半导体科技股份有限公司 | Packaging structure of semiconductor element and manufacture method thereof |
| CN102592982A (en) * | 2011-01-17 | 2012-07-18 | 精材科技股份有限公司 | Method for forming chip package |
| CN102951597A (en) * | 2011-08-19 | 2013-03-06 | 烟台睿创微纳技术有限公司 | Preparation method of micro-bridge structured infrared detector, and micro-bridge structure |
| US20140082936A1 (en) * | 2010-05-07 | 2014-03-27 | Seiko Epson Corporation | Method of manufacturing a wiring substrate |
| CN102187277B (en) * | 2008-10-20 | 2014-07-09 | 住友电木株式会社 | Positive photosensitive resin composition for spray coating and method for producing through electrode using same |
| US20140199835A1 (en) * | 2010-03-11 | 2014-07-17 | Xintec Inc. | Chip package and method for forming the same |
| CN104037305A (en) * | 2014-07-01 | 2014-09-10 | 江阴长电先进封装有限公司 | Packaging method and packaging structure of wafer-level LED with low heat resistance |
| CN104167387A (en) * | 2014-08-04 | 2014-11-26 | 苏州科阳光电科技有限公司 | Wafer level chip packaging technology |
| JP5655825B2 (en) * | 2012-07-30 | 2015-01-21 | セイコーエプソン株式会社 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, CIRCUIT BOARD AND ELECTRONIC DEVICE |
| CN104576564A (en) * | 2015-01-26 | 2015-04-29 | 华天科技（昆山）电子有限公司 | Wafer level chip size packaging structure and manufacturing process thereof |
| CN104617036A (en) * | 2015-01-14 | 2015-05-13 | 华天科技（昆山）电子有限公司 | Manufacturing method for interconnected through holes in wafer level chip size packaging |
| US9252082B2 (en) * | 2009-10-15 | 2016-02-02 | Seiko Epson Corporation | Semiconductor device, circuit substrate, and electronic device |
-
2016
- 2016-08-23 CN CN201610708182.7A patent/CN106229272A/en active Pending
Patent Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102187277B (en) * | 2008-10-20 | 2014-07-09 | 住友电木株式会社 | Positive photosensitive resin composition for spray coating and method for producing through electrode using same |
| US9252082B2 (en) * | 2009-10-15 | 2016-02-02 | Seiko Epson Corporation | Semiconductor device, circuit substrate, and electronic device |
| CN101774531A (en) * | 2010-01-05 | 2010-07-14 | 上海集成电路研发中心有限公司 | MEMS microbridge structure contact hole preparation method |
| US20140199835A1 (en) * | 2010-03-11 | 2014-07-17 | Xintec Inc. | Chip package and method for forming the same |
| CN101807560A (en) * | 2010-03-12 | 2010-08-18 | 晶方半导体科技（苏州）有限公司 | Packaging structure of semiconductor device and manufacture method thereof |
| CN101800207B (en) * | 2010-03-12 | 2011-10-26 | 苏州晶方半导体科技股份有限公司 | Packaging structure of semiconductor element and manufacture method thereof |
| US20140082936A1 (en) * | 2010-05-07 | 2014-03-27 | Seiko Epson Corporation | Method of manufacturing a wiring substrate |
| CN102592982A (en) * | 2011-01-17 | 2012-07-18 | 精材科技股份有限公司 | Method for forming chip package |
| CN102951597A (en) * | 2011-08-19 | 2013-03-06 | 烟台睿创微纳技术有限公司 | Preparation method of micro-bridge structured infrared detector, and micro-bridge structure |
| JP5655825B2 (en) * | 2012-07-30 | 2015-01-21 | セイコーエプソン株式会社 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, CIRCUIT BOARD AND ELECTRONIC DEVICE |
| CN104037305A (en) * | 2014-07-01 | 2014-09-10 | 江阴长电先进封装有限公司 | Packaging method and packaging structure of wafer-level LED with low heat resistance |
| CN104167387A (en) * | 2014-08-04 | 2014-11-26 | 苏州科阳光电科技有限公司 | Wafer level chip packaging technology |
| CN104617036A (en) * | 2015-01-14 | 2015-05-13 | 华天科技（昆山）电子有限公司 | Manufacturing method for interconnected through holes in wafer level chip size packaging |
| CN104576564A (en) * | 2015-01-26 | 2015-04-29 | 华天科技（昆山）电子有限公司 | Wafer level chip size packaging structure and manufacturing process thereof |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109273406A (en) * | 2018-09-05 | 2019-01-25 | 苏州科阳光电科技有限公司 | Packaging method of wafer-level chip |
| CN109273406B (en) * | 2018-09-05 | 2021-04-06 | 苏州科阳光电科技有限公司 | Packaging method of wafer-level chip |
| CN110911287A (en) * | 2018-09-17 | 2020-03-24 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN110911287B (en) * | 2018-09-17 | 2021-09-14 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN110783264A (en) * | 2019-10-31 | 2020-02-11 | 长江存储科技有限责任公司 | Wafer protection structure and protection method |
| CN110867432A (en) * | 2019-11-28 | 2020-03-06 | 苏州晶方半导体科技股份有限公司 | Chip packaging structure and packaging method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102163659B (en) | Led packaging, high-reflection submount for light-emitting diode package and fabrication method thereof | |
| KR100652443B1 (en) | Redistribution interconnection structure of wafer level package and the method for manufacturing thereof | |
| CN106229272A (en) | Wafer stage chip encapsulation method and structure | |
| US8624383B2 (en) | Integrated circuit package and method for fabrication thereof | |
| JP2008141021A (en) | Semiconductor device and manufacturing method of the semiconductor device | |
| CN102592982A (en) | Method for forming chip package | |
| US8129835B2 (en) | Package substrate having semiconductor component embedded therein and fabrication method thereof | |
| JP2012235083A (en) | Package structure and manufacturing method of the same | |
| KR20040038507A (en) | Semiconductor device having heat release structure using SOI substrate and method for fabricating the same | |
| CN106252308A (en) | Wafer encapsulation body and its preparation method | |
| KR100240916B1 (en) | Circuitized substrate with waterial containment means and method making same | |
| US8748313B2 (en) | Electroforming technique for mask formation | |
| JP2011014644A (en) | Wiring board and manufacturing method thereof | |
| CN102945840B (en) | Semiconductor chip package and method for packing | |
| JP2005175327A (en) | Semiconductor device, and manufacturing method thereof | |
| KR20110131674A (en) | Cap for protecting divice using photo-sensitivity glass substrate and menufacturing method thereof | |
| JP2004140115A (en) | Semiconductor device, its manufacturing method, circuit board, and electronic equipment | |
| JP2010192481A (en) | Semiconductor substrate, semiconductor package and method of manufacturing semiconductor substrate | |
| JP2007115853A (en) | Semiconductor device and method of manufacturing same | |
| CN111627857A (en) | Packaging method and packaging structure | |
| CN110034064A (en) | Semiconductor structure and forming method thereof | |
| CN110867432A (en) | Chip packaging structure and packaging method | |
| CN108807197A (en) | Chip package with sidewall metallization portion | |
| CN117542733B (en) | Manufacturing method, circuit and chip of semiconductor structure | |
| JP7335036B2 (en) | Semiconductor package manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20161214 |
|
| RJ01 | Rejection of invention patent application after publication |