CN117542733B - Manufacturing method, circuit and chip of semiconductor structure - Google Patents
Manufacturing method, circuit and chip of semiconductor structure Download PDFInfo
- Publication number
- CN117542733B CN117542733B CN202410033303.7A CN202410033303A CN117542733B CN 117542733 B CN117542733 B CN 117542733B CN 202410033303 A CN202410033303 A CN 202410033303A CN 117542733 B CN117542733 B CN 117542733B
- Authority
- CN
- China
- Prior art keywords
- opening
- layer
- metal layer
- photoresist mask
- photoresist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 64
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 248
- 229910052751 metal Inorganic materials 0.000 claims abstract description 195
- 239000002184 metal Substances 0.000 claims abstract description 195
- 239000000758 substrate Substances 0.000 claims abstract description 66
- 238000000034 method Methods 0.000 claims abstract description 50
- 238000005530 etching Methods 0.000 claims description 24
- 239000007769 metal material Substances 0.000 claims description 22
- 239000000463 material Substances 0.000 claims description 15
- 238000000151 deposition Methods 0.000 claims description 10
- 230000001590 oxidative effect Effects 0.000 claims description 5
- 238000005286 illumination Methods 0.000 claims description 3
- 238000003475 lamination Methods 0.000 claims description 3
- 230000003247 decreasing effect Effects 0.000 claims description 2
- 229910044991 metal oxide Inorganic materials 0.000 claims 2
- 150000004706 metal oxides Chemical class 0.000 claims 2
- 238000004090 dissolution Methods 0.000 description 9
- QVEIBLDXZNGPHR-UHFFFAOYSA-N naphthalene-1,4-dione;diazide Chemical compound [N-]=[N+]=[N-].[N-]=[N+]=[N-].C1=CC=C2C(=O)C=CC(=O)C2=C1 QVEIBLDXZNGPHR-UHFFFAOYSA-N 0.000 description 9
- 239000002923 metal particle Substances 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000008020 evaporation Effects 0.000 description 4
- 238000001704 evaporation Methods 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910052758 niobium Inorganic materials 0.000 description 3
- 239000010955 niobium Substances 0.000 description 3
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 3
- 239000005011 phenolic resin Substances 0.000 description 3
- 229920001568 phenolic resin Polymers 0.000 description 3
- 229910052594 sapphire Inorganic materials 0.000 description 3
- 239000010980 sapphire Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052715 tantalum Inorganic materials 0.000 description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052720 vanadium Inorganic materials 0.000 description 3
- GPPXJZIENCGNKB-UHFFFAOYSA-N vanadium Chemical compound [V]#[V] GPPXJZIENCGNKB-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229920001155 polypropylene Polymers 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- CFJRGWXELQQLSA-UHFFFAOYSA-N azanylidyneniobium Chemical compound [Nb]#N CFJRGWXELQQLSA-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
Abstract
The present disclosure relates to a method for manufacturing a semiconductor structure, a circuit and a chip, the method for manufacturing the semiconductor structure comprising: providing a substrate; forming a lower electrode on the substrate, and forming an insulating layer on a top surface of the lower electrode; forming a first photoresist mask on the insulating layer, and forming a first opening in the first photoresist mask, wherein the first opening at least exposes a part of the top surface of the insulating layer; forming a top metal layer, wherein part of the top metal layer is filled into the first opening and is overlapped on the insulating layer, and the other part of the top metal layer is covered on the first photoresist mask; the first photoresist mask and the top metal layer on the first photoresist mask are removed, the top metal layer in the first opening forms an upper electrode, the overlapping area of the upper electrode and the lower electrode forms a semiconductor structure, the structure and the performance of the semiconductor structure are complete, and the problem of wire breakage is avoided.
Description
Technical Field
The present disclosure relates to the field of integrated circuits, and in particular, to a method for manufacturing a semiconductor structure, a circuit and a chip.
Background
In some semiconductor device fabrication processes, a structure is fabricated in which two metal lines directly intersect. The manufacturing method adopted in common comprises the following steps: after forming the first metal line on the substrate, an insulating layer is formed on a top surface of the first metal line. And then depositing and forming a metal material layer, and etching the metal material layer to form a second metal line, wherein the first metal line and the first metal line intersect.
And etching the metal material layer to form a second metal wire, wherein the metal material layer is usually subjected to over-etching to ensure that the metal material layer is cut off, so that the problems of short circuit of devices and the like caused by insufficient etching of local areas due to different thicknesses of the metal material layers at different positions are avoided. Because the thickness of the insulating layer is very thin, the insulating layer except for the overlapping area of the first metal wire and the second metal wire may be etched and removed by performing over-etching on the metal material layer, the first metal wire except for the overlapping area may be removed, and the first metal wire is damaged, so that the problem that the first metal wire is broken and broken may even occur is caused.
Disclosure of Invention
Based on the above, the present disclosure provides a method, a circuit and a chip for manufacturing a semiconductor structure.
In a first aspect, the present disclosure provides a method for fabricating a semiconductor structure, including:
Providing a substrate;
forming a lower electrode on the substrate, and forming an insulating layer on the top surface of the lower electrode;
Forming a first photoresist mask on the insulating layer, and forming a first opening in the first photoresist mask, wherein at least part of the top surface of the insulating layer is exposed by the first opening;
Forming a top metal layer, wherein part of the top metal layer is filled into the first opening and is overlapped on the insulating layer, and the other part of the top metal layer is covered on the first photoresist mask;
And removing the first photoresist mask and the top metal layer on the first photoresist mask, wherein the top metal layer in the first opening forms an upper electrode, and the overlapping area of the upper electrode and the lower electrode forms a semiconductor structure.
In one embodiment, the top metal layer filled into the first opening and the top metal layer covering the first photoresist mask are independently disposed, and a lift-off process is used to remove the first photoresist mask and the top metal layer on the first photoresist mask.
In one embodiment, forming a first photoresist mask on the insulating layer, forming a first opening in the first photoresist mask, includes:
Forming a first photoresist layer, wherein the first photoresist layer covers the insulating layer and the substrate;
Forming a second photoresist layer, wherein the second photoresist layer covers the first photoresist layer;
And carrying out illumination and development treatment on the lamination of the first photoresist layer and the second photoresist layer, forming a first sub-opening in the first photoresist layer, forming a second sub-opening in the second photoresist layer, wherein the first sub-opening and the second sub-opening are communicated to form the first opening, and the transverse size of the first sub-opening is larger than that of the second sub-opening.
In one embodiment, the lateral dimension of the second sub-opening is gradually increased in a direction away from the first sub-opening, or gradually decreased in a direction away from the first sub-opening.
In one embodiment, forming the top metal layer includes:
Depositing a metal material, wherein part of the metal material is deposited into the first sub-opening through the second sub-opening, and part of the metal material is attached to the side wall of the second sub-opening and the top surface of the second photoresist layer to jointly form the top metal layer;
the thickness of the top metal layer deposited into the first sub-opening is controlled to be smaller than the height of the first photoresist layer, so that the top metal layer in the first opening and the top metal layer attached to the side wall of the second sub-opening are independently arranged.
In one embodiment, the top metal layer filled in the first opening is connected with the top metal layer covered on the first photoresist mask; before removing the first photoresist mask and the top metal layer on the first photoresist mask, the method further comprises:
A second photoresist mask is formed, the second photoresist mask covering the top metal layer in the first opening.
In one embodiment, removing the first photoresist mask and the top metal layer on the first photoresist mask comprises:
Etching to remove the top metal layer covered on the first photoresist mask;
And removing the first photoresist mask and the second photoresist mask.
In one embodiment, forming a lower electrode on the substrate, forming an insulating layer on a top surface of the lower electrode, includes:
forming a bottom metal layer, wherein the bottom metal layer covers the top surface of the substrate;
etching the bottom metal layer to form the lower electrode;
And oxidizing the lower electrode, wherein the top of the lower electrode is oxidized to form the insulating layer.
In a second aspect, the present disclosure provides a circuit comprising a semiconductor structure fabricated by the method of fabricating a semiconductor structure according to the first aspect of the present disclosure.
In a third aspect, the present disclosure provides a chip comprising:
A substrate;
The circuit of the second aspect of the present disclosure, the circuit being located on the substrate.
According to the manufacturing method, the circuit and the chip of the semiconductor structure, before the top metal layer is formed, the insulating layer outside the overlapping area of the upper electrode and the lower electrode is protected through the first photoresist mask, the insulating layer outside the overlapping area and the lower electrode are prevented from being damaged in the process of etching the top metal layer to form the upper electrode, the structure and the performance of the formed semiconductor structure are guaranteed to be complete, and the problem of broken wires is avoided.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments or the conventional techniques of the present disclosure, the drawings that are required to be used in the description of the embodiments or the conventional techniques will be briefly described below.
Fig. 1 is a process flow diagram of a method for fabricating a semiconductor structure according to an embodiment.
Fig. 2 is a process flow diagram of a method for fabricating a semiconductor structure according to an embodiment.
Fig. 3 is a process flow diagram of a method for fabricating a semiconductor structure according to an embodiment.
Fig. 4 is a top view of a semiconductor structure formed in one embodiment.
FIG. 5 is a cross-sectional view taken along line a-a after a first mask layer is formed over the underlying metal layer in one embodiment.
Fig. 6 is a cross-sectional view taken along line a-a after forming a bottom electrode in one embodiment.
Fig. 7 is a cross-sectional view taken along line a-a after forming an insulating layer in one embodiment.
Fig. 8 is a cross-sectional view taken along line b-b after forming an insulating layer in one embodiment.
Fig. 9 is a cross-sectional view taken along line b-b after forming a first photoresist layer and a second photoresist layer in one embodiment.
Fig. 10 is a cross-sectional view taken along line b-b after forming a first opening in one embodiment.
Fig. 11 is a cross-sectional view taken along line b-b after forming a first opening in another embodiment.
FIG. 12 is a cross-sectional view taken along line b-b after formation of a top metal layer in one embodiment.
Fig. 13 is a cross-sectional view taken along line b-b after forming an upper electrode in one embodiment.
Fig. 14 is a cross-sectional view taken along line b-b after forming a first photoresist mask in one embodiment.
FIG. 15 is a cross-sectional view taken along line b-b after formation of a top metal layer in one embodiment.
FIG. 16 is a cross-sectional view taken along line b-b after an initial photoresist layer is formed, in one embodiment.
FIG. 17 is a cross-sectional view taken along line b-b after a second initial photoresist mask is formed in one embodiment.
Fig. 18 is a cross-sectional view taken along line b-b after forming a second photoresist mask in one embodiment.
Fig. 19 is a cross-sectional view taken along line a-a after forming an upper electrode in one embodiment.
Fig. 20 is a cross-sectional view taken along line b-b after forming an upper electrode in one embodiment.
Fig. 21 is a cross-sectional view taken along line a-a after removal of the first photoresist mask and the second photoresist mask in one embodiment.
Fig. 22 is a cross-sectional view taken along line b-b after removal of the first photoresist mask and the second photoresist mask in one embodiment.
Reference numerals illustrate:
10. A substrate; 11. an oxide layer; 20. a lower electrode; 21. a bottom metal layer; 30. an insulating layer; 40. a first photoresist mask; 41. a first photoresist layer; 42. a second photoresist layer; 50. a first opening; 51. a first sub-opening; 52. a second sub-opening; 60. an upper electrode; 61. a top metal layer; 70. a second photoresist mask; 71. a second initial photoresist mask; 72. an initial photoresist layer; 80. a first mask layer; 100. a semiconductor structure; d1, a first preset direction; d2, a second preset direction.
Detailed Description
In order that the disclosure may be understood, a more complete description of the disclosure will be rendered by reference to the appended drawings. Preferred embodiments of the present disclosure are shown in the drawings. This disclosure may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.
The present disclosure provides a method for manufacturing a semiconductor structure, a circuit and a chip, the method for manufacturing the semiconductor structure includes: providing a substrate; forming a lower electrode on the substrate, and forming an insulating layer on a top surface of the lower electrode; forming a first photoresist mask on the insulating layer, and forming a first opening in the first photoresist mask, wherein the first opening at least exposes a part of the top surface of the insulating layer; forming a top metal layer, wherein part of the top metal layer is filled into the first opening and is overlapped on the insulating layer, and the other part of the top metal layer is covered on the first photoresist mask; and removing the first photoresist mask and the top metal layer on the first photoresist mask, wherein the top metal layer in the first opening forms an upper electrode, and the overlapping area of the upper electrode and the lower electrode forms a semiconductor structure. According to the manufacturing method of the semiconductor structure, before the top metal layer is formed, the insulating layer outside the overlapping area of the upper electrode and the lower electrode is protected through the first photoresist mask, so that the top metal layer only covers the insulating layer outside the overlapping area of the upper electrode and the lower electrode, the insulating layer outside the overlapping area and the lower electrode are prevented from being damaged in the process of forming the upper electrode by etching the top metal layer, the structure and the performance of the formed semiconductor structure are guaranteed to be complete, and the problem of wire breakage is avoided.
According to an exemplary embodiment, the present exemplary embodiment provides a method for manufacturing a semiconductor structure, and fig. 1 shows a flowchart of the method for manufacturing a semiconductor structure according to the present exemplary embodiment, where the method for manufacturing a semiconductor structure includes:
Step S11: a substrate is provided.
Step S12: a lower electrode is formed on a substrate, and an insulating layer is formed on a top surface of the lower electrode.
Step S13: a first photoresist mask is formed on the insulating layer, and a first opening is formed in the first photoresist mask, wherein the first opening at least exposes a part of the top surface of the insulating layer.
Step S14: and forming a top metal layer, wherein part of the top metal layer is filled into the first opening and is superposed on the insulating layer, and the other part of the top metal layer is covered on the first photoresist mask.
Step S15: and removing the first photoresist mask and the top metal layer on the first photoresist mask, wherein the top metal layer in the first opening forms an upper electrode, and the overlapping area of the upper electrode and the lower electrode forms a semiconductor structure.
In step S11, as shown in fig. 4 and 5, the substrate 10 may be a silicon crystal substrate or a sapphire substrate, or the substrate 10 may be another kind of semiconductor substrate.
In step S12, referring to fig. 5, an underlying metal layer 21 may be formed on the substrate 10, and then, referring to fig. 4 and 6, the underlying metal layer 21 is etched into the lower electrode 20 extending in the first preset direction D1. Next, referring to fig. 7, the lower electrode 20 is subjected to an oxidation treatment, and a part of the top structure of the lower electrode 20 is oxidized to form an insulating layer 30. The material of the lower electrode 20 may include at least one of niobium, aluminum, vanadium, titanium, or tantalum, and the material of the insulating layer 30 may be aluminum oxide or tantalum oxide.
In other embodiments, referring to fig. 4 and 7, after the underlying metal layer 21 is formed, an insulating layer 30 may be formed on the underlying metal layer 21 through a deposition process, and then the insulating layer 30 and the underlying metal layer 21 are etched, the underlying metal layer 21 is etched to form the lower electrode 20 extending in the first preset direction D1, and the insulating layer 30 covers the top surface of the lower electrode 20.
In step S13, a photoresist is coated, which covers the insulating layer 30 and the substrate 10 exposed by the lower electrode 20. Referring to fig. 9, 10 or 14, the photoresist is exposed and developed to form a first photoresist mask 40, and the first photoresist mask 40 has a first opening 50, the first opening 50 exposes a portion of the top surface of the insulating layer 30, and a region of the insulating layer 30 exposed by the first opening 50, that is, a region where the upper electrode 60 and the lower electrode 20 of the semiconductor structure 100 overlap (which will be described in detail later).
In step S14, referring to fig. 12 or 15, a top metal layer 61 is formed by depositing a metal material by a process such as evaporation sputtering or atomic layer deposition. A portion of the top metal layer 61 fills the first opening 50 and covers the insulating layer 30 exposed by the first opening 50, and a portion of the top metal layer 61 covers the first photoresist mask 40.
The material of the top metal layer 61 may include at least one of niobium, aluminum, vanadium, titanium, tantalum, titanium nitride, niobium nitride. In some examples, top metal layer 61 and lower electrode 20 have the same material; in other examples, the top metal layer 61 and the lower electrode 20 may be different in material or different in composition.
In some embodiments, referring to fig. 12, the top metal layer 61 filled into the first opening 50 and the top metal layer 61 covering the first photoresist mask 40 are separately provided; in other embodiments, referring to fig. 15, a top metal layer 61 filled into the first opening 50 is connected to the top metal layer 61 covering the first photoresist mask 40.
In step S15, in some embodiments, referring to fig. 12 and 13, the top metal layer 61 filled in the first opening 50 and the top metal layer 61 covering the first photoresist mask 40 are separately disposed, the first photoresist mask 40 and the top metal layer 61 on the first photoresist mask 40 are removed by a lift-off process, the top metal layer 61 located in the first opening 50 forms the upper electrode 60, and the overlapping region of the upper electrode 60 and the lower electrode 20 forms the semiconductor structure 100.
In other embodiments, referring to fig. 15 and 22, the top metal layer 61 filled in the first opening 50 is connected to the top metal layer 61 covering the first photoresist mask 40, the first photoresist mask 40 and the top metal layer 61 on the first photoresist mask 40 are etched and removed by an etching process, and the top metal layer 61 in the first opening 50 is etched and remains to form the upper electrode 60.
In the manufacturing method of the semiconductor structure of the embodiment, in the process of forming the upper electrode, the insulating layer and the lower electrode are shielded by the first photoresist mask, the top metal layer is formed based on the first photoresist mask by deposition, then the first photoresist mask and the top metal layer on the first photoresist mask are removed, the upper electrode is formed on the top metal layer with the first opening, the insulating layer and the lower electrode are protected by the first photoresist mask, the insulating layer and the lower electrode are prevented from being damaged in the process of removing the top metal layer on the first photoresist mask, the structure and the performance of the formed semiconductor structure are guaranteed to be completed, the lower electrode of the semiconductor structure is free from the defect of damage or disconnection, and the quality and the yield of the formed semiconductor structure are improved.
According to an exemplary embodiment, the present exemplary embodiment provides a method for fabricating a semiconductor structure, and fig. 2 shows a flowchart of the method for fabricating a semiconductor structure according to the present exemplary embodiment, the method for fabricating a semiconductor structure of the present exemplary embodiment includes:
step S21: a substrate is provided.
Step S22: a lower electrode is formed on a substrate, and an insulating layer is formed on a top surface of the lower electrode.
Step S23: a first photoresist mask is formed on the insulating layer, and a first opening is formed in the first photoresist mask, wherein the first opening at least exposes a part of the top surface of the insulating layer.
Step S24: and forming a top metal layer, wherein part of the top metal layer is filled into the first opening and is superposed on the insulating layer, the other part of the top metal layer is covered on the first photoresist mask, and the top metal layer filled into the first opening and the top metal layer covered on the first photoresist mask are independently arranged.
Step S25: and removing the first photoresist mask and the top metal layer on the first photoresist mask by adopting a stripping process, wherein the top metal layer in the first opening forms an upper electrode, and the overlapping area of the upper electrode and the lower electrode forms a semiconductor structure.
In step S21, as shown in fig. 4 and 5, the substrate 10 may be a silicon crystal substrate 10 or a sapphire substrate 10, or the substrate 10 may be another kind of semiconductor substrate 10. In this embodiment, the top surface of the substrate 10 is covered with an oxide layer 11.
In step S22, the lower electrode 20 is formed on the substrate 10, and the insulating layer 30 is formed on the top surface of the lower electrode 20, using the following embodiments:
step S221: and forming a bottom metal layer, wherein the bottom metal layer covers the top surface of the substrate.
As shown in fig. 5, the underlying metal layer 21 may be formed by depositing a metal material using a process such as evaporation sputtering or atomic layer deposition, and the underlying metal layer 21 is overlaid on the oxide layer 11 on the substrate 10. The material of the underlying metal layer 21 may include at least one of niobium, aluminum, vanadium, titanium, or tantalum, and in this embodiment, the material of the underlying metal layer 21 includes aluminum.
Step S222: etching the bottom metal layer to form a lower electrode.
As shown in fig. 5, a first mask layer 80 is formed on the underlying metal layer 21, the first mask layer 80 defines a mask pattern for forming the lower electrode 20, and as shown in fig. 4 and 6, the underlying metal layer 21 is etched according to the first mask layer 80, and the lower electrode 20 extending in the first preset direction D1 is formed on the substrate 10.
Step S223: the lower electrode is oxidized to form an insulating layer on top of the lower electrode.
As shown in fig. 7 and 8, the bottom electrode 20 is naturally oxidized in the process environment, and a part of the metal material on the top of the bottom electrode 20 is oxidized to form an oxide having insulation property, and an insulation layer 30 is formed on the bottom electrode 20. Alternatively, in order to improve the process efficiency, the lower electrode 20 may be treated by thermal oxidation or wet oxidation so that the top of the lower electrode 20 is oxidized to form the insulating layer 30.
In step S23, a first photoresist mask 40 is formed on the insulating layer 30, and a first opening 50 is formed in the first photoresist mask 40, including:
Step S231: a first photoresist layer is formed, the first photoresist layer covering the insulating layer and the substrate.
Step S232: a second photoresist layer is formed, and the second photoresist layer covers the first photoresist layer.
Step S233: and carrying out illumination and development treatment on the lamination of the first photoresist layer and the second photoresist layer, forming a first sub-opening in the first photoresist layer, forming a second sub-opening in the second photoresist layer, and communicating the first sub-opening with the second sub-opening to form a first opening, wherein the transverse dimension of the first sub-opening is larger than that of the second sub-opening.
Here, the "lateral direction" in the present embodiment refers to a direction perpendicular to the extending direction of the lower electrode 20, that is, the "lateral direction" is perpendicular to the first preset direction D1 (refer to fig. 4), and the "lateral direction" is parallel to the top surface of the substrate 10.
As shown in fig. 9, the first photoresist layer 41 is a positive photoresist layer, the first photoresist layer 41 includes a propylene polymer and a naphthoquinone diazide (NQD), and the first photoresist layer 41 has the propylene polymer and the naphthoquinone diazide as photoactive compounds (photo acid generator, PAC).
The second photoresist layer 42 is a positive photoresist layer, the second photoresist layer 42 includes phenolic resin and naphthoquinone diazide (NQD), the second photoresist layer 42 uses naphthoquinone diazide as a photoactive compound, and the content of the naphthoquinone diazide in the second photoresist layer 42 is greater than that in the first photoresist layer 41. The naphthoquinone diazide has an inhibitory effect on the solubility of the alkaline developer of the phenolic resin, and the dissolution rate of the first photoresist layer 41 in the alkaline developer is greater than the dissolution rate of the second photoresist layer 42 in the alkaline developer.
As shown in fig. 10, after exposing the stack of the first photoresist layer 41 and the second photoresist layer 42 to light, the unexposed first photoresist layer 41 and the unexposed second photoresist layer 42 are removed by dissolution with an alkaline developer, and dissolution of the first photoresist layer 41 and the second photoresist layer 42 with the alkaline developer has an undercut effect, i.e., dissolution rate of the first photoresist layer 41 is greater than dissolution rate of the second photoresist layer 42 within the same time, so that the lateral dimension of the first sub-opening 51 formed in the first photoresist layer 41 is greater than the lateral dimension of the second sub-opening 52 formed in the second photoresist layer 42.
The lateral dimension of the second sub-opening 52 gradually increases in a direction away from the first sub-opening 51 as shown in fig. 11, or the lateral dimension of the second sub-opening 52 gradually decreases in a direction away from the first sub-opening 51 as shown in fig. 10.
It is understood that the concentration of naphthoquinone diazide at the junction interface of the first photoresist layer 41 and the second photoresist layer 42 is the highest, and that the inhibition effect of naphthoquinone diazide on the dissolution of the phenolic resin in the second photoresist layer 42 is the greatest. As shown in fig. 10, in the present embodiment, the lateral dimension of the second sub-opening 52 gradually decreases in a direction away from the first sub-opening 51.
In other embodiments, as shown in fig. 11, the lateral dimensions of the second sub-opening 52 may be gradually increased in a direction away from the first sub-opening 51 by controlling the concentration of naphthoquinone diazide in the second photoresist layer 42 to gradually increase in a direction away from the first photoresist layer 41.
In step S24, as shown in fig. 12, referring to fig. 10, a top metal layer 61 is formed, including: depositing a metal material, wherein a part of the metal material is deposited into the first sub-opening 51 through the second sub-opening 52, and a part of the metal material is attached to the side wall of the second sub-opening 52 and the top surface of the second photoresist layer 42 to jointly form a top metal layer 61; the thickness of the top metal layer 61 deposited into the first sub-opening 51 is controlled to be smaller than the height of the first photoresist layer 41 so that the top metal layer 61 in the first opening 50 and the top metal layer 61 attached to the sidewall of the second sub-opening 52 are independently disposed.
For example, the metal material may be deposited by evaporation sputtering, atomic layer deposition or electroplating, and the particles of the metal material move in a direction perpendicular to the top surface of the substrate 10 toward the substrate 10, and when the particles of the metal material move toward the first sub-opening 51 through the second sub-opening 52, the particles of the metal material are affected by the shape of the opening with a narrow top and a wide bottom, and diffraction and scattering effects are generated, so that the angles of movement of the particles of the metal material are affected, more particles of the metal material are deposited in the first sub-opening 51, less particles of the metal material are deposited on the side wall of the second sub-opening 52, and the thickness of the top metal layer 61 attached to the side wall of the second sub-opening 52 is relatively thin.
As shown in fig. 12, the thickness of the top metal layer 61 deposited in the first sub-opening 51 may be controlled by controlling the length of time for depositing the metal material such that the thickness of the top metal layer 61 in the first sub-opening 51 is smaller than the thickness of the first photoresist layer 41, ensuring that the top metal layer 61 in the first sub-opening 51 and the top metal layer 61 attached to the sidewall of the second sub-opening 52 are discontinuous, i.e., the top metal layer 61 filled into the first opening 50 and the top metal layer 61 covered on the first photoresist mask 40 are independently disposed.
In step S25, as shown in fig. 13, referring to fig. 12, the first photoresist layer 41, the second photoresist layer 42 and the top metal layer 61 attached to the second photoresist layer 42 are stripped and removed by using a stripping solution, so that the stripping solution has a better effect of removing the first photoresist mask 40 and the top metal layer 61 on the first photoresist mask 40, and the etching step is not required, so that the insulating layer 30 and the lower electrode 20 are not damaged, and the problem that the lower electrode 20 is damaged or the lower electrode 20 is broken is avoided.
After the first photoresist mask 40 and the top metal layer 61 on the first photoresist mask 40 are stripped, the top metal layer 61 in the first sub-opening 51 forms an upper electrode 60, the upper electrode 60 extends along a second preset direction D2, the second preset direction D2 and the first preset direction D1 intersect at a preset included angle, the upper electrode 60 at least covers a part of the insulating layer 30 exposed by the first sub-opening 51, an overlapping region exists between the upper electrode 60 and the lower electrode 20, and an overlapping region between the upper electrode 60 and the lower electrode 20 forms the semiconductor structure 100.
In some embodiments, the second preset direction D2 and the first preset direction D1 perpendicularly intersect, and the upper electrode 60 and the lower electrode 20 intersect in a cross shape.
According to the manufacturing method of the semiconductor structure, the first photoresist mask comprises two layers of a first photoresist layer and a second photoresist layer with different dissolution rates, the first photoresist layer and the second photoresist layer are dissolved by alkaline developer, the transverse size of the first sub-opening is larger than that of the second sub-opening, the first opening is of a structure with the upper part narrow and the lower part wide, the duration of depositing the top metal layer is controlled by utilizing the structure with the upper part narrow and the lower part wide of the first opening, so that the top metal layer filled in the first opening and the top metal layer covered on the first photoresist mask are independently arranged, the top metal layer on the first photoresist mask and the top metal layer on the first photoresist mask can be removed through a stripping process, the insulating layer and the lower electrode are prevented from being damaged, the structural structure and the performance of the formed semiconductor are guaranteed to be complete, the wire breakage risk is avoided, and the yield of products is improved.
According to the manufacturing method of the semiconductor structure, the thickness of the formed upper electrode can be controlled by controlling the thickness of the first photoresist layer and the duration of depositing the top metal layer, so that the process control accuracy is improved.
According to an exemplary embodiment, the present exemplary embodiment provides a method for fabricating a semiconductor structure, and fig. 3 shows a flowchart of the method for fabricating a semiconductor structure according to the present exemplary embodiment, the method for fabricating a semiconductor structure of the present exemplary embodiment includes:
Step S31: a substrate is provided.
Step S32: a lower electrode is formed on a substrate, and an insulating layer is formed on a top surface of the lower electrode.
Step S33: a first photoresist mask is formed on the insulating layer, and a first opening is formed in the first photoresist mask, wherein the first opening at least exposes a part of the top surface of the insulating layer.
Step S34: and forming a top metal layer, wherein part of the top metal layer is filled into the first opening and is superposed on the insulating layer, the other part of the top metal layer is covered on the first photoresist mask, and the top metal layer filled into the first opening is connected with the top metal layer covered on the first photoresist mask.
Step S35: and removing the first photoresist mask and the top metal layer on the first photoresist mask, wherein the top metal layer in the first opening forms an upper electrode, and the overlapping area of the upper electrode and the lower electrode forms a semiconductor structure.
In step S31, as shown in fig. 4 and 5, the substrate 10 may be a silicon crystal substrate 10 or a sapphire substrate 10, or the substrate 10 may be another kind of semiconductor substrate 10. In this embodiment, the top surface of the substrate 10 is covered with an oxide layer 11.
In step S32, the lower electrode 20 is formed on the substrate 10, and the insulating layer 30 is formed on the top surface of the lower electrode 20 in the same manner as in step S21 in the above-described example. First, as shown in fig. 5, an underlying metal layer 21 is formed, the underlying metal layer 21 covering the top surface of the substrate 10. Then, as shown in fig. 6, the underlying metal layer 21 is etched to form the lower electrode 20, and the lower electrode 20 extends in the first preset direction D1. Next, as shown in fig. 7, the lower electrode 20 is oxidized, and the top of the lower electrode 20 is oxidized to form an insulating layer 30.
In step S33, as shown in fig. 4 and 14, first, a photoresist is coated to form a first photoresist mask 40, and the first photoresist mask 40 covers the insulating layer 30 and the substrate 10 exposed by the lower electrode 20. Then, the first photoresist mask 40 is subjected to light irradiation and development processes, and a first opening 50 is formed in the first photoresist mask 40, and the first opening 50 extends in the second preset direction D2 and exposes a portion of the top surface of the insulating layer 30.
In step S34, as shown in fig. 15, a metal material is deposited by evaporation sputtering or atomic layer deposition to form a top metal layer 61, the top metal layer 61 covers the exposed top surface of the insulating layer 30 and fills the first opening 50, the top metal layer 61 also covers the top surface of the first photoresist mask 40, the top metal layer 61 in the first opening 50 is connected to the top metal layer 61 covering the top surface of the first photoresist mask 40, and the top metal layer 61 in the first opening 50 and the top metal layer 61 covering the top surface of the first photoresist mask 40 have a height difference.
In step S35, before removing the first photoresist mask 40 and the top metal layer 61 on the first photoresist mask 40, the following steps are further performed:
step S35-1: a second photoresist mask is formed, the second photoresist mask covering the top metal layer in the first opening.
First, as shown in fig. 16, a photoresist is coated to form an initial photoresist layer 72, and the initial photoresist layer 72 covers the top metal layer 61 and fills the height difference of the top metal layer 61.
Then, as shown in fig. 17, the initial photoresist layer 72 is exposed and developed to form a second initial photoresist mask 71, and the second initial photoresist mask 71 covers the top metal layer 61 in the first opening 50 and a portion of the top metal layer 61 around the first opening 50.
Next, as shown in fig. 18, the sidewalls of the second initial photoresist mask 71 are etched using an etching gas, for example, carbon tetrafluoride (CF 4) may be used to etch the second initial photoresist mask 71, and a portion of the second initial photoresist mask 71 is etched away from the sidewalls of the second initial photoresist mask 71 in the lateral direction, and the second initial photoresist mask 71 covering the top metal layer 61 in the first opening 50 is etched and left as the second photoresist mask 70.
It should be noted that, under the limitations of the current photolithography process and the photolithography apparatus, it is difficult to form the initial photoresist layer 72 into the second photoresist mask 70 by only one exposure and development process, and it is difficult to secure alignment accuracy of the second photoresist mask 70 and the first opening 50. Therefore, in this embodiment, the second initial photoresist mask 71 with a larger size is formed by exposing and developing, and then the second initial photoresist mask 71 is etched to form the second photoresist mask 70 with a smaller size and a more precise size, so that the precision of the formed second photoresist mask 70 is improved, the size of the second photoresist mask 70 is ensured to be consistent with the size of the top metal layer 61 in the first opening 50, and the second photoresist mask 70 and the top metal layer 61 in the first opening 50 have high alignment precision.
In this embodiment, removing the first photoresist mask 40 and the top metal layer 61 on the first photoresist mask 40 includes:
Step S351: and etching to remove the top metal layer covered on the first photoresist mask.
As shown in fig. 4, 18 and 20, the top metal layer 61 is etched using the second photoresist mask 70 as a mask, all of the top metal layer 61 exposed by the second photoresist mask 70 is removed, the top metal layer 61 covered by the second photoresist mask 70 remains, an upper electrode 60 is formed in the first opening 50, the upper electrode 60 extends along a second preset direction D2, the second preset direction D2 and the first preset direction D1 intersect at a preset angle, the upper electrode 60 covers the insulating layer 30 exposed by the first opening 50, there is an overlapping region between the upper electrode 60 and the lower electrode 20, and the overlapping region between the upper electrode 60 and the lower electrode 20 forms the semiconductor structure 100. In some embodiments, the second preset direction D2 and the first preset direction D1 perpendicularly intersect, and the upper electrode 60 and the lower electrode 20 intersect in a cross shape.
It will be appreciated that during the etching of the top metal layer 61, part of the first photoresist mask 40 may be removed by the etching process, but after the etching process, part of the first photoresist mask 40 remains etched and covers the insulating layer 30 and the substrate 10, and the first photoresist mask 40 protects the insulating layer 30, the lower electrode 20 and the substrate 10, so as to avoid damaging or breaking the insulating layer 30, the lower electrode 20 and the substrate 10 during etching of the insulating layer 30 and the substrate 10, and avoid damaging or breaking the lower electrode 20.
Step S352: the first photoresist mask and the second photoresist mask are removed.
As shown in fig. 21 and 21, referring to fig. 19 and 20, the first photoresist mask 40 and the second photoresist mask 70 may be removed by an ashing process or dissolution using a photoresist remover.
According to the manufacturing method of the semiconductor structure, the first opening of the first photoresist mask only exposes part of the top surface of the insulating layer, the first photoresist mask is used for covering the rest of the insulating layer and the lower electrode, after the top metal layer is formed, the top metal layer located in the first opening is protected through the second photoresist mask, the top electrode is formed by etching the top metal layer based on the second photoresist mask, the insulating layer and the lower electrode outside the overlapping area of the upper electrode and the lower electrode are prevented from being damaged in the process of etching the upper electrode, the integrity of the lower electrode is guaranteed, the problem that broken wires exist in the formed semiconductor structure is avoided, and the yield of products is improved.
According to an exemplary embodiment, the present exemplary embodiment provides a circuit including a semiconductor structure fabricated by the method of fabricating a semiconductor structure of the above-described embodiments.
According to an exemplary embodiment, a chip is provided, the chip including a substrate and the circuit in the above embodiment, the circuit being located on the substrate.
The technical features of the above embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples merely represent a few embodiments of the present disclosure, which are described in more detail and are not to be construed as limiting the scope of the claims. It should be noted that variations and modifications can be made by those skilled in the art without departing from the spirit of the disclosure, which are within the scope of the disclosure. Accordingly, the scope of protection of the present disclosure should be determined by the following claims.
Claims (11)
1. A method of fabricating a semiconductor structure, comprising:
Providing a substrate;
Forming a lower electrode on the substrate, forming an insulating layer on the top surface of the lower electrode, wherein the lower electrode is a metal electrode, the insulating layer is formed by oxidizing the lower electrode, and the material of the insulating layer comprises metal oxide;
Forming a first photoresist mask on the insulating layer, and forming a first opening in the first photoresist mask, wherein at least part of the top surface of the insulating layer is exposed by the first opening;
Forming a top metal layer, wherein part of the top metal layer is filled into the first opening and is overlapped on the insulating layer, and the other part of the top metal layer is covered on the first photoresist mask;
removing the first photoresist mask and the top metal layer on the first photoresist mask, wherein the top metal layer in the first opening forms an upper electrode, the upper electrode and the lower electrode are intersected in a cross shape, and the overlapping area of the upper electrode and the lower electrode forms a semiconductor structure;
The top metal layer filled in the first opening and the top metal layer covered on the first photoresist mask are independently arranged, and a stripping process is adopted to remove the first photoresist mask and the top metal layer on the first photoresist mask;
The first photoresist mask comprises a first photoresist layer and a second photoresist layer which are sequentially formed on the insulating layer, the first opening comprises a first sub-opening formed in the first photoresist layer and a second sub-opening formed in the second photoresist layer, the transverse dimension of the first sub-opening is larger than that of the second sub-opening, and the thickness of the top metal layer in the first sub-opening is smaller than the height of the first photoresist layer.
2. The method of claim 1, wherein forming a first photoresist mask over the insulating layer, forming a first opening in the first photoresist mask, comprises:
Forming a first photoresist layer, wherein the first photoresist layer covers the insulating layer and the substrate;
forming the second photoresist layer, wherein the second photoresist layer covers the first photoresist layer;
And carrying out illumination and development treatment on the lamination of the first photoresist layer and the second photoresist layer, forming a first sub-opening in the first photoresist layer, forming a second sub-opening in the second photoresist layer, wherein the first sub-opening and the second sub-opening are communicated to form a first opening, and the transverse size of the first sub-opening is larger than that of the second sub-opening.
3. The method of fabricating a semiconductor structure of claim 2, wherein a lateral dimension of the second sub-opening is gradually increased in a direction away from the first sub-opening or gradually decreased in a direction away from the first sub-opening.
4. The method of fabricating a semiconductor structure of claim 3, wherein forming a top metal layer comprises:
Depositing a metal material, wherein part of the metal material is deposited into the first sub-opening through the second sub-opening, and part of the metal material is attached to the side wall of the second sub-opening and the top surface of the second photoresist layer to jointly form the top metal layer;
the thickness of the top metal layer deposited into the first sub-opening is controlled to be smaller than the height of the first photoresist layer, so that the top metal layer in the first opening and the top metal layer attached to the side wall of the second sub-opening are independently arranged.
5. The method of fabricating a semiconductor structure according to claim 1, wherein forming a lower electrode on the substrate and forming an insulating layer on a top surface of the lower electrode comprises:
forming a bottom metal layer, wherein the bottom metal layer covers the top surface of the substrate;
etching the bottom metal layer to form the lower electrode;
And oxidizing the lower electrode, wherein the top of the lower electrode is oxidized to form the insulating layer.
6. A method of fabricating a semiconductor structure, comprising:
Providing a substrate;
Forming a lower electrode on the substrate, forming an insulating layer on the top surface of the lower electrode, wherein the lower electrode is a metal electrode, the insulating layer is formed by oxidizing the lower electrode, and the material of the insulating layer comprises metal oxide;
Forming a first photoresist mask on the insulating layer, and forming a first opening in the first photoresist mask, wherein at least part of the top surface of the insulating layer is exposed by the first opening;
Forming a top metal layer, wherein part of the top metal layer is filled into the first opening and is overlapped on the insulating layer, and the other part of the top metal layer is covered on the first photoresist mask;
removing the first photoresist mask and the top metal layer on the first photoresist mask, wherein the top metal layer in the first opening forms an upper electrode, the upper electrode and the lower electrode are intersected in a cross shape, and the overlapping area of the upper electrode and the lower electrode forms a semiconductor structure;
The top metal layer filled in the first opening is connected with the top metal layer covered on the first photoresist mask, the first photoresist mask and the top metal layer on the first photoresist mask are etched and removed by adopting an etching process, and the top metal layer in the first opening is etched and reserved to form the upper electrode.
7. The method of claim 6, further comprising, prior to removing the first photoresist mask and the top metal layer on the first photoresist mask:
A second photoresist mask is formed, the second photoresist mask covering the top metal layer in the first opening.
8. The method of claim 7, wherein removing the first photoresist mask and the top metal layer on the first photoresist mask comprises:
Etching to remove the top metal layer covered on the first photoresist mask;
And removing the first photoresist mask and the second photoresist mask.
9. The method of fabricating a semiconductor structure according to claim 6, wherein forming a lower electrode on the substrate and forming an insulating layer on a top surface of the lower electrode comprises:
forming a bottom metal layer, wherein the bottom metal layer covers the top surface of the substrate;
etching the bottom metal layer to form the lower electrode;
And oxidizing the lower electrode, wherein the top of the lower electrode is oxidized to form the insulating layer.
10. A circuit comprising a semiconductor structure fabricated by the method of any of claims 1-5 or the method of fabricating a semiconductor structure of any of claims 6-7.
11. A chip, comprising:
A substrate;
The circuit of claim 10, the circuit being located on the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410033303.7A CN117542733B (en) | 2024-01-10 | 2024-01-10 | Manufacturing method, circuit and chip of semiconductor structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410033303.7A CN117542733B (en) | 2024-01-10 | 2024-01-10 | Manufacturing method, circuit and chip of semiconductor structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN117542733A CN117542733A (en) | 2024-02-09 |
| CN117542733B true CN117542733B (en) | 2024-04-26 |
Family
ID=89784662
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410033303.7A Active CN117542733B (en) | 2024-01-10 | 2024-01-10 | Manufacturing method, circuit and chip of semiconductor structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117542733B (en) |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4076575A (en) * | 1976-06-30 | 1978-02-28 | International Business Machines Corporation | Integrated fabrication method of forming connectors through insulative layers |
| US4398341A (en) * | 1981-09-21 | 1983-08-16 | International Business Machines Corp. | Method of fabricating a highly conductive structure |
| JPH06318605A (en) * | 1993-02-26 | 1994-11-15 | Nec Corp | Manufacture of semiconductor device |
| KR970018128A (en) * | 1995-09-30 | 1997-04-30 | 배순훈 | Metal layer formation method |
| US5937326A (en) * | 1995-06-09 | 1999-08-10 | Hyundai Electronics Industries Co., Ltd. | Method for making semiconductor device having via hole |
| US6042999A (en) * | 1998-05-07 | 2000-03-28 | Taiwan Semiconductor Manufacturing Company | Robust dual damascene process |
| US6821896B1 (en) * | 2001-05-31 | 2004-11-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method to eliminate via poison effect |
| KR20050092933A (en) * | 2004-03-17 | 2005-09-23 | 삼성전자주식회사 | Method of fabricating a fin field effect transistor using an isotropic etching technique |
| CN113257662A (en) * | 2021-07-14 | 2021-08-13 | 苏州汉天下电子有限公司 | Semiconductor device and manufacturing method thereof |
| CN114823540A (en) * | 2021-01-29 | 2022-07-29 | 长鑫存储技术有限公司 | Manufacturing method of semiconductor structure and semiconductor structure |
| CN117328015A (en) * | 2023-09-26 | 2024-01-02 | 本源量子计算科技（合肥）股份有限公司 | Mask and manufacturing method thereof, oblique evaporation coating method and superconducting circuit |
| WO2024000358A1 (en) * | 2022-06-28 | 2024-01-04 | 上海积塔半导体有限公司 | Preparation method for metal microstructure and preparation method for semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9728444B2 (en) * | 2015-12-31 | 2017-08-08 | International Business Machines Corporation | Reactive ion etching assisted lift-off processes for fabricating thick metallization patterns with tight pitch |
-
2024
- 2024-01-10 CN CN202410033303.7A patent/CN117542733B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4076575A (en) * | 1976-06-30 | 1978-02-28 | International Business Machines Corporation | Integrated fabrication method of forming connectors through insulative layers |
| US4398341A (en) * | 1981-09-21 | 1983-08-16 | International Business Machines Corp. | Method of fabricating a highly conductive structure |
| JPH06318605A (en) * | 1993-02-26 | 1994-11-15 | Nec Corp | Manufacture of semiconductor device |
| US5937326A (en) * | 1995-06-09 | 1999-08-10 | Hyundai Electronics Industries Co., Ltd. | Method for making semiconductor device having via hole |
| KR970018128A (en) * | 1995-09-30 | 1997-04-30 | 배순훈 | Metal layer formation method |
| US6042999A (en) * | 1998-05-07 | 2000-03-28 | Taiwan Semiconductor Manufacturing Company | Robust dual damascene process |
| US6821896B1 (en) * | 2001-05-31 | 2004-11-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method to eliminate via poison effect |
| KR20050092933A (en) * | 2004-03-17 | 2005-09-23 | 삼성전자주식회사 | Method of fabricating a fin field effect transistor using an isotropic etching technique |
| CN114823540A (en) * | 2021-01-29 | 2022-07-29 | 长鑫存储技术有限公司 | Manufacturing method of semiconductor structure and semiconductor structure |
| CN113257662A (en) * | 2021-07-14 | 2021-08-13 | 苏州汉天下电子有限公司 | Semiconductor device and manufacturing method thereof |
| WO2024000358A1 (en) * | 2022-06-28 | 2024-01-04 | 上海积塔半导体有限公司 | Preparation method for metal microstructure and preparation method for semiconductor device |
| CN117328015A (en) * | 2023-09-26 | 2024-01-02 | 本源量子计算科技（合肥）股份有限公司 | Mask and manufacturing method thereof, oblique evaporation coating method and superconducting circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN117542733A (en) | 2024-02-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8110340B2 (en) | Method of forming a pattern of a semiconductor device | |
| JPH07297149A (en) | Semiconductor device and fabrication thereof | |
| JP2005285890A (en) | Zinc oxide processing method | |
| JPH08160590A (en) | Formation of pattern, production of reticle and semiconductor device | |
| KR100919349B1 (en) | Method of forming metal wiring in flash memory device | |
| US6846569B2 (en) | Carbon-doped hard mask and method of passivating structures during semiconductor device fabrication | |
| CN117542733B (en) | Manufacturing method, circuit and chip of semiconductor structure | |
| KR100457046B1 (en) | Method for forming a contact in semiconductor device process | |
| JP2007149768A (en) | Method of manufacturing semiconductor device | |
| KR100853796B1 (en) | Method for fabricating semiconductor device | |
| JP3585039B2 (en) | Hole forming method | |
| US20060057783A1 (en) | Methods of forming fuses using selective etching of capping layers | |
| US6287752B1 (en) | Semiconductor device, method of manufacturing a semiconductor device, and method of forming a pattern for semiconductor device | |
| US20240145244A1 (en) | Method of patterning underlying structure | |
| US20080233735A1 (en) | Etching method for semiconductor element | |
| KR100827488B1 (en) | Method for forming a metal line pattern of the semiconductor device | |
| KR100231847B1 (en) | Method of fabricating semiconductor device | |
| US20040018743A1 (en) | Method for removing photoresist after metal layer etching in a semiconductor device | |
| US20030064599A1 (en) | Pattern forming method | |
| US7071101B1 (en) | Sacrificial TiN arc layer for increased pad etch throughput | |
| JP2008130923A (en) | Method of manufacturing semiconductor device | |
| KR100752171B1 (en) | Method of Fabricating Semiconductor Device | |
| KR20030002942A (en) | Method for forming metal interconnection in semiconductor device | |
| KR100609222B1 (en) | Formation Method of Fine Metal Wiring in Semiconductor Manufacturing Process | |
| JPH05102160A (en) | Semiconductor device and its manufacture |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |