KR970018128A - Metal layer formation method - Google Patents

Metal layer formation method Download PDF

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KR970018128A
KR970018128A KR1019950033572A KR19950033572A KR970018128A KR 970018128 A KR970018128 A KR 970018128A KR 1019950033572 A KR1019950033572 A KR 1019950033572A KR 19950033572 A KR19950033572 A KR 19950033572A KR 970018128 A KR970018128 A KR 970018128A
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layer
forming
metal layer
pattern
metal
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KR1019950033572A
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KR0159398B1 (en
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노재우
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배순훈
대우전자 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 실리콘 기판상에 메탈층을 형성시키기 위한 방법에 관한 것으로 실리콘 기판(21)상에 절연층(22)을 형성시키는 제1단계와, 상기 절연층(22)상에 시드층(23)을 형성시키는 제2단계와, 상기 시드층(23)상에 포토 레지스트를 도포시켜서 감광층(24)을 형성시키는 제3단계와, 상기 감광층(24)을 소정 시간동안 모노 클로로벤젠에 침적시키는 제4단계와, 상기 감광층(24)을 소정 형상의 제1패턴으로 패터닝시키는 제5단계와, 상기 감광층(24)의 제1패턴을 통하여 노출된 상기 시드층(23)상에 메탈층(25)을 형성시키는 제6단계와, 상기 메탈층(25)상에 보호층(26)을 형성시키는 제7단계와, 상기 시드층(23)상에 잔존하는 감광층(24)을 제거하는 제8단계와, 그리고 상기 시드층(23) 및 상기 보호층(26)을 순차적으로 제거하는 제9단계로 이루어지며 이에 의해서 상기 시드층의 제거시 상기 메탈층이 손상받는 것을 방지시키므로 원하는 형상의 패턴 치수 및 선폭을 갖는 메탈층을 형성시킨다.The present invention relates to a method for forming a metal layer on a silicon substrate, the first step of forming the insulating layer 22 on the silicon substrate 21, and the seed layer (23) on the insulating layer 22 A second step of forming a photoresist, a third step of forming a photosensitive layer 24 by applying a photoresist on the seed layer 23, and depositing the photosensitive layer 24 in monochlorobenzene for a predetermined time. A fourth step, patterning the photosensitive layer 24 into a first pattern having a predetermined shape, and a metal layer on the seed layer 23 exposed through the first pattern of the photosensitive layer 24. A sixth step of forming the 25, a seventh step of forming the protective layer 26 on the metal layer 25, and removing the remaining photosensitive layer 24 on the seed layer 23. An eighth step and a ninth step of sequentially removing the seed layer 23 and the protective layer 26. Because when the removal is prevented from being damage to the metal layer to form a metal layer having a line width of the pattern dimensions and the desired shape.

Description

메탈층 형성 방법Metal layer formation method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도(가) 내지 (마)는 본 발명에 따른 전기 도금 공정에 의하여 메탈층을 형성시키기 위한 방법을 순차적으로 도시한 공정도,2 (a) to (e) is a process diagram sequentially showing a method for forming a metal layer by the electroplating process according to the present invention,

제3도는 본 발명의 다른 실시예에 따라서 감광층이 패터닝된 것을 도시한 공정도.3 is a process chart showing that the photosensitive layer is patterned according to another embodiment of the present invention.

Claims (10)

실리콘 기판상에 메탈층을 형성시키기 위한 방법에 있어서, 실리콘 기판(21)상에 절연층(22)을 형성시키는 제1단계와, 상기 절연층(22)상에 도전성 금속을 적층시킴으로서 시드층(23)을 형성시키는 제2단계와, 상기 시드층(23)상에 포토 레지스트를 도포시켜서 감광층(24)을 형성시키는 제3단계와, 상기 감광층(24)을 소정 시간동안 모노 클로로벤젠에 침적시키는 제4단계와, 상기 감광층(24)을 소정 형상의 제1패턴으로 패터닝시키는 제5단계와, 상기 감광층(24)의 제1패턴을 통하여 노출된 상기 시드층(23)상에 메탈층(25)을 형성시키는 제6단계와, 상기 메탈층(25)상에 보호층(26)을 형성시키는 제7단계와, 상기 시드층(23)상에 잔존하는 감광층(24)을 제거하는 제8단계와, 그리고 상기 시드층(23) 및 상기 보호층(26)을 순차적으로 제거하는 제9단계로 이루어진 것을 특징으로 하는 메탈층 형성 방법.A method for forming a metal layer on a silicon substrate, the method comprising: forming a dielectric layer 22 on a silicon substrate 21; and seed layer by laminating a conductive metal on the dielectric layer 22; 23), a third step of forming a photosensitive layer 24 by applying a photoresist on the seed layer 23, and the photosensitive layer 24 in mono chlorobenzene for a predetermined time The fourth step of depositing, the fifth step of patterning the photosensitive layer 24 into a first pattern having a predetermined shape, and the seed layer 23 exposed through the first pattern of the photosensitive layer 24. A sixth step of forming the metal layer 25, a seventh step of forming the protective layer 26 on the metal layer 25, and a photosensitive layer 24 remaining on the seed layer 23. And an ninth step of sequentially removing the seed layer 23 and the protective layer 26. Metal layer formation method. 제1항에 있어서, 상기 메탈층(25)상에 상기 보호층(26)을 형성시키기 전에 상기 감광층(24)을 상기 제1패턴의 선폭보다 확대된 선폭을 갖는 제2패턴으로 형성시키는 것을 특징으로 하는 메탈층 형성 방법.The method of claim 1, wherein forming the photosensitive layer 24 in a second pattern having a line width larger than the line width of the first pattern before forming the protective layer 26 on the metal layer 25. A metal layer formation method characterized by the above-mentioned. 제2항에 있어서, 상기 제2패턴으로 형성된 상기 감광층(24)은 상기 보호층(26)의 형성 전에 미리 노광처리되는 것을 특징으로 하는 메탈층 형성 방법.3. The method of claim 2, wherein the photosensitive layer (24) formed with the second pattern is previously exposed before forming the protective layer (26). 제2항에 있어서, 상기 감광층(23)의 제2패턴의 선폭 크기는 상기 메탈층(25)의 패턴의 선폭 크기와 동일한 것을 특징으로 하는 메탈층 형성 방법.The method of claim 2, wherein the line width of the second pattern of the photosensitive layer is equal to the line width of the pattern of the metal layer. 제1항에 있어서, 상기 메탈층(25)은 전기 도금 공정에 의하여 형성되는 것을 특징으로 하는 메탈층 형성 방법.The method of claim 1, wherein the metal layer (25) is formed by an electroplating process. 제1항에 있어서 상기 시드층(23)은 도전성 금속에 대한 선택적 식각률이 양호한 반응성 이온 식각 공정에 의하여 제거되는 것을 특징으로 하는 메탈층 형성 방법.The method of claim 1, wherein the seed layer (23) is removed by a reactive ion etching process having a good selective etch rate for the conductive metal. 제6항에 있어서, 상기 반응성 이온 식각 공정은 염소 플라즈마를 사용하는 것을 특징으로 하는 메탈층 형성 방법.The method of claim 6, wherein the reactive ion etching process uses chlorine plasma. 제1항에 있어서 상기 보호층(26)은 실리콘 산화물 및 알루미나에 대한 선택적 식각률이 양호한 에칭 용액의 식각 작용에 의하여 제거되는 것을 특징으로 하는 메탈층 형성 방법.The method of claim 1, wherein the protective layer (26) is removed by etching of an etching solution having a good selective etching rate for silicon oxide and alumina. 제8항에 있어서, 상기 에칭 용액은 불산 용액을 함유하고 있는 것을 특징으로 하는 메탈층 형성 방법.The metal layer forming method according to claim 8, wherein the etching solution contains a hydrofluoric acid solution. 제9항에 있어서, 상기 에칭 용액은 불산 암모늄을 부가적으로 함유하고 있는 것을 특징으로 하는 메탈층 형성 방법.The method for forming a metal layer according to claim 9, wherein the etching solution additionally contains ammonium fluoride. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950033572A 1995-09-30 1995-09-30 Method for fabricating a metallic layer KR0159398B1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100697601B1 (en) * 2004-07-10 2007-03-21 지성우 Manufacturing process for polymer business card
CN117542733A (en) * 2024-01-10 2024-02-09 合肥晶合集成电路股份有限公司 Manufacturing method, circuit and chip of semiconductor structure

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100697601B1 (en) * 2004-07-10 2007-03-21 지성우 Manufacturing process for polymer business card
CN117542733A (en) * 2024-01-10 2024-02-09 合肥晶合集成电路股份有限公司 Manufacturing method, circuit and chip of semiconductor structure
CN117542733B (en) * 2024-01-10 2024-04-26 合肥晶合集成电路股份有限公司 Manufacturing method, circuit and chip of semiconductor structure

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