KR100208429B1 - Semiconductor element metal line manufacturing method - Google Patents

Semiconductor element metal line manufacturing method Download PDF

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KR100208429B1
KR100208429B1 KR1019950007165A KR19950007165A KR100208429B1 KR 100208429 B1 KR100208429 B1 KR 100208429B1 KR 1019950007165 A KR1019950007165 A KR 1019950007165A KR 19950007165 A KR19950007165 A KR 19950007165A KR 100208429 B1 KR100208429 B1 KR 100208429B1
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alloy
metal wiring
present
forming
cucl
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KR1019950007165A
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KR960035973A (en
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이정석
황창연
김상익
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

본 발명은 반도체 소자의 금속배선 형성방법에 관하여 개시된다.The present invention relates to a method for forming metal wiring of a semiconductor device.

본 발명은 금속배선의 전기 전도성을 높이기 위해 Cu가 함유한 합금을 사용할 때 패턴공정 후에 잔존하는 Cu잔유물을 Ar 이온 스퍼터링 효과를 이용하여 효과적으로 제거할 수 있다.The present invention can effectively remove the Cu residue remaining after the patterning process using the Ar ion sputtering effect when using the alloy containing Cu to increase the electrical conductivity of the metal wiring.

따라서, 본 발명은 금속배선의 브릿지 현상을 방지할 수 있어 소자의 수율 및 신뢰성을 향상시킬 수 있다.Therefore, the present invention can prevent the bridge phenomenon of the metal wiring to improve the yield and reliability of the device.

Description

반도체 소자의 금속배선 형성방법Metal wiring formation method of semiconductor device

제1a 내지 1c도는 종래 반도체 소자의 금속배선 형성공정을 설명하기 위해 도시된 소자의 단면도.1A to 1C are cross-sectional views of a device shown to explain a metallization process of a conventional semiconductor device.

제2a 내지 2c도는 본 발명에 의한 반도체 소자의 금속배선 형성공정을 설명하기 위한 도시된 소자의 단면도.2A to 2C are cross-sectional views of the device shown for explaining the metallization process of the semiconductor device according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

10, 20 : 웨이퍼 11, 21 : Al-Si-Cu 합금10, 20: wafer 11, 21: Al-Si-Cu alloy

11A,21A : 금속배선 12, 22 :Cu11A, 21A: Metal wiring 12, 22: Cu

12A : 잔유물 13, 23 : 포토레지스트 패턴12A: Residue 13, 23: Photoresist Pattern

본 발명은 반도체 소자의 금속배선 형성방법에 관한 것으로,특히 금속배선의 전기 전도성을 높이기 위해 Cu(Copper)를 함유한 합금을 사용할 때, 패턴공정 후에 잔존하는 잔유물을 효과적으로 제거할 수 있는 반도체 소자의 금속배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices, and more particularly, when using an alloy containing Cu (Copper) to increase the electrical conductivity of metal wirings. It relates to a metal wiring forming method.

일반적으로, 반도체 소자가 고집적화 되어감에 따라 전기 전도성이 높은 금속배선을 필요로 한다. 반도체 소자의 금속배선으로 사용되는 Al-금속에 전기 전도성을 높이기 위하여 Cu를 함유한 Al-Si-Cu 합금이 쓰이고 있다. 그런데, 금속배선을 형성하기 위한 식각공정시 Cu는 식각개스인 Cl과 반응하여 CuClx(Copper Chloride)를 생성하게 되는데, 이는 Alclx(Aluminum Chloride)보다 증기압(Vapor Pressure)이 낮아 Cl계열의 식각개스로는 CuClx잔유물을 제거하기가 어려운 문제가 있다. 이를 첨부된 도면을 참조하여 설명하면 다음과 같다.In general, as semiconductor devices are highly integrated, a metal wiring having high electrical conductivity is required. Al-Si-Cu alloys containing Cu are used to increase electrical conductivity in Al-metals used as metallization of semiconductor devices. However, during the etching process for forming the metal wiring, Cu reacts with Cl, which is an etching gas, to generate CuCl x (Copper Chloride), which is lower than Alcl x (Aluminum Chloride) in vapor pressure (Vapor Pressure). There is a problem with gas that it is difficult to remove CuCl x residues. This will be described with reference to the accompanying drawings.

제1a 내지 1c도는 종래 반도체 소자의 금속배선 형성공정을 설명하기 위해 도시된 소자의 단면도이다.1A to 1C are cross-sectional views of a device illustrated to explain a metallization process of a conventional semiconductor device.

제1a도는 웨이퍼(10)상에 Al-Si-Cu 합금(11)을 증착하고 Al-Si-Cu 합금(11)상에 포토레지스트를 도포한 후, 금속배선 마스크를 사용한 리소그라피 공정으로 포토레지스트 패턴(13)이 형성된 것이 도시된다.FIG. 1A illustrates the deposition of an Al-Si-Cu alloy 11 on a wafer 10 and a photoresist on an Al-Si-Cu alloy 11, followed by a lithography process using a metallization mask. It is shown that 13 is formed.

제1b도는 Cl 계열의 식각개스를 사용한 식각공정으로 Al-Si-Cu 합금(11)을 식각하는 것이 도시되고, 제1c도는 식각공정을 계속 실시하여 금속배선(11A)을 형성한 후, 포토레지스트 패턴(13)을 제거한 것이 도시된다.FIG. 1B shows etching of the Al-Si-Cu alloy 11 by an etching process using a Cl-based etching gas. FIG. 1C shows a photoresist after forming the metal wiring 11A by continuing the etching process. The removal of the pattern 13 is shown.

여기서, Al-Si-Cu 합금(11)은 식각개스인 Cl과 반응하여 AlClx과 CuClx로 제거된다. 그런데, 제1b도에 도시된 바와 같이 Cu(12)는 식각개스인 Cl로 제거하기 어렵다. 즉, Cu(12)는 식각개스인 Cl과 반응하여 CuClx를 생성하게 되는데, 이는 AlClx보다 증기압이 낮아 Cl계열의 식각개스로는 CuClx잔유물을 제거하기가 어렵다. 따라서, 제1c도에 도시된 바와같이 이웃하는 금속배선(11A) 사이에 CuClx또는 Cu 잔유물(12A)이 남아 브릿지(Bridge) 현상을 유발시키는 등 제품의 특성을 저하시키는 문제가 있다.Here, the Al-Si-Cu alloy 11 is removed with AlCl x and CuCl x by reacting with Cl, which is an etching gas. However, as shown in FIG. 1B, Cu 12 is difficult to remove with Cl, which is an etching gas. That is, Cu (12) reacts with Cl, which is an etching gas, to generate CuCl x , which is difficult to remove CuCl x residues with Cl-based etching gas because the vapor pressure is lower than that of AlCl x . Accordingly, as shown in FIG. 1C, there is a problem in that CuCl x or Cu residue 12A remains between neighboring metal wirings 11A, causing a bridge phenomenon, thereby degrading product characteristics.

따라서, 본 발명은 Cu에 의해 발생되는 분산물을 Ar 스퍼터링 효과를 이용하여 제거하여 Al-Si-Cu 합금을 금속배선의 재료로 사용하는 금속배선 형성공정의 안정성을 확보할 수 있어, 소자의 전기적 특성을 향상시킬 수 있을 뿐만 아니라, 소자의 신뢰성 및 수율을 향상시킬 수 있는 반도체 소자의 금속배선 형성방법을 제공함에 그 목적이 있다.Therefore, the present invention can secure the stability of the metal wiring forming process using the Al-Si-Cu alloy as a material for the metal wiring by removing the dispersion generated by Cu by using the Ar sputtering effect, It is an object of the present invention to provide a method for forming a metal wiring of a semiconductor device that can not only improve the characteristics, but also improve the reliability and yield of the device.

이러한 목적을 달성하기 위한 본 발명의 금속배선 형성방법은 웨이퍼상에 Al-Si-Cu 합금을 증착하고, Al-Si-Cu 합금상에 포토레지스트 패턴을 형성하는 단계와, 상기 포토레지스트 패턴을 식각 마스크로 Cl계열의 식각개스를 사용한 식각공정시 Ar이온 스퍼터링 효과를 이용하여 상기 Al-Si-Cu 합금을 식각하는 동시에 식각공정중에 발생되는 CuClx부산물을 제거하고, 이로인하여 Al-Si-Cu 합금 배선이 형성되는 단계와, 상기 포토레지스트 패턴을 제거하는 단계로 이루어지는 것을 특징으로 한다.The metallization method of the present invention for achieving the above object is to deposit an Al-Si-Cu alloy on the wafer, to form a photoresist pattern on the Al-Si-Cu alloy, and to etch the photoresist pattern During the etching process using the Cl series etching gas as a mask, the Al-Si-Cu alloy is etched using the Ar ion sputtering effect, and at the same time, CuCl x by- products generated during the etching process are removed, and thus the Al-Si-Cu alloy is used. And forming a wiring and removing the photoresist pattern.

이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

제2a 내지 2C도는 본 발명에 의한 반도체 소자의 금속배선 형성공정을 설명하기 위해 도시된 소자의 단면도이다.2A to 2C are cross-sectional views of the device shown to explain the metallization process of the semiconductor device according to the present invention.

제2a 도는 웨이퍼(20)상에 Al-Si-Cu 합금(21)을 증착하고, Al-Si-Cu 합금(21)상에 포토레지스트를 도포한 후, 금속배선 마스크를 사용한 리소그라피 공정으로 포토레지스트 패턴(23)이 형성된 것이 도시된다.2a or Al-Si-Cu alloy 21 is deposited on the wafer 20, a photoresist is applied on the Al-Si-Cu alloy 21, and then the photoresist is subjected to a lithography process using a metallization mask. It is shown that the pattern 23 is formed.

제2b도는 포토레지스트 패턴(23)을 식각마스크로 Cl계열의 식각개스를 사용한 식각공정시 Ar 이온 스퍼터링 효과를 이용하여 Al-Si-Cu 합금(21)을 식각하는 것이 도시되고, 제2c도는 식각공정을 계속 실시하여 금속배선(21A)을 형성한 후, 포토레지스트 패턴(23)을 제거한 것이 도시된다.FIG. 2B shows etching of the Al-Si-Cu alloy 21 by using an Ar ion sputtering effect in the etching process using the Cl series etching gas using the photoresist pattern 23 as an etching mask, and FIG. It is shown that the photoresist pattern 23 is removed after the process is continued to form the metal wiring 21A.

여기서, Al-Si-Cu 합금(21)은 식각개스인 Cl과 반응하여 AlClx과 CuClx로 제거되는데, 종래와는 달리 식각공정시 Ar 이온을 주입시켜 Ar이온 스퍼터링 효과를 이용하여 낮은 증기압 특성을 갖는 CuClx잔유물을 효과적으로 제거할 수 있다(제2b도). 이로 인하여 제2c도에 도시된 바와같이 금속배선(21A) 사이에 CuClx또는 Cu 잔유물이 없게 된다.Here, the Al-Si-Cu alloy 21 is removed by AlCl x and CuCl x by reacting with Cl, which is an etching gas. Unlike the conventional art, the Al-Si-Cu alloy has a low vapor pressure characteristic by using Ar ions sputtering effect by injecting Ar ions during the etching process. It is possible to effectively remove the CuCl x residues having (Fig. 2b). This results in no CuCl x or Cu residues between the metallizations 21A as shown in FIG. 2C.

상술한 바와 같이, 본 발명은 금속배선의 전기 전도성을 높이기 위해 Cu를 함유한 합금을 사용할 때, 패턴공정 후에 잔존하는 Cu잔유물을 Ar 이온 스퍼터링 효과를 이용하여 효과적으로 제거하여, 기존과 같은 금속배선간의 브릿지 현상 등의 문제를 해결하므로써 금속배선 형성공정의 안정성을 확보할 수 있어, 소자의 전기적 특성을 향상시킬 수 있을 뿐만 아니라, 소자의 신뢰성 및 수율을 향상시킬 수 있다.As described above, in the present invention, when using an alloy containing Cu to increase the electrical conductivity of the metal wiring, the Cu residues remaining after the patterning process are effectively removed by using the Ar ion sputtering effect, and thus, the metal wiring between By solving the problems such as the bridge phenomenon, the stability of the metallization forming process can be ensured, and the electrical characteristics of the device can be improved, and the reliability and yield of the device can be improved.

Claims (1)

반도체 소자의 금속배선 형상방법에 있어서, 웨이퍼상에 Al-Si-Cu 합금을 중착하고 Al-Si-Cu 합금상에 포토레지스트 패턴을 형성하는 단계와, 상기 포토레지스트 패턴을 식각마스크로 Cl계열의 식각개스를 사용한 식각공정시 Ar 이온 스퍼터링 효과를 이용하여 상기 Al-Si-Cu 합금을 식각하는 동시에 식각공정중에 발생되는 CuClx부산물을 제거하고, 이로 인하여 Al-Si-Cu 합금 배선이 형성되는 단계와, 상기 포토레지스트 패턴을 제거하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.A method of forming a metallization of a semiconductor device, the method comprising: depositing an Al-Si-Cu alloy on a wafer and forming a photoresist pattern on the Al-Si-Cu alloy; During the etching process using an etching gas, the Al-Si-Cu alloy is etched by using an Ar ion sputtering effect, and CuCl x by- products generated during the etching process are removed, thereby forming an Al-Si-Cu alloy wiring. And removing the photoresist pattern.
KR1019950007165A 1995-03-31 1995-03-31 Semiconductor element metal line manufacturing method KR100208429B1 (en)

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KR100208429B1 true KR100208429B1 (en) 1999-07-15

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