CN105575880B - A kind of production method of semiconductor devices - Google Patents
A kind of production method of semiconductor devices Download PDFInfo
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- CN105575880B CN105575880B CN201410528396.7A CN201410528396A CN105575880B CN 105575880 B CN105575880 B CN 105575880B CN 201410528396 A CN201410528396 A CN 201410528396A CN 105575880 B CN105575880 B CN 105575880B
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Abstract
The present invention provides a kind of production method of semiconductor devices, including：Wafer is provided, wafer includes semiconductor substrate and the device in semiconductor substrate, and is formed in the interlayer dielectric layer of covering device in semiconductor substrate；Negative photoresist layer is formed on interlayer dielectric layer；Pre-exposure is carried out to the negative photoresist layer of the invalid chip area of crystal round fringes；Remaining unexposed negative photoresist layer is exposed and is developed, to form patterned negative photoresist layer；Using patterned negative photoresist layer as mask, interlayer dielectric layer is etched, forms opening exposing semiconductor substrate；The part semiconductor substrate of exposure in opening is etched, to form silicon hole；Remove negative photoresist layer.Production method according to the present invention, the invalid chip area in crystal round fringes is avoided to form silicon hole pattern, the root that the stripping problem of crystal round fringes generates is not only reduced, the risk of Cu-W ore deposit Al process work bench has been greatly reduced, has improved the reliability and yield of product.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to more particularly to a kind of making side of semiconductor devices
Method.
Background technology
Silicon hole (Through Silicon Via, abbreviation TSV) technology is one of the key technology of 3D packaging technologies.TSV
Be by between chip and chip, make vertical conducting between wafer and wafer, realize the state-of-the-art technology interconnected between chip.
It is bonded with previous IC package and different using the superimposing technique of salient point, TSV can make the density that chip is stacked in three-dimensional
Maximum, appearance and size is minimum, and substantially improves the performance of chip speed and low-power consumption.
Stage residing for TSV manufacture crafts is different, can be divided into：Front through hole (via-first), middle through-hole (via-
Middle) and three kinds of technological processes of rear through-hole (via-last), wherein via-first is the blank silicon before manufacturing CMOS
On piece etching produces TSV；Via-middle is carved after manufacturing CMOS but before back-end process (BEOL) on wafer
TSV is produced in erosion, and via-last is to produce TSV in the back-etching of thinned wafer after back-end process.
Under normal conditions, via-middle techniques need to carry out TSV after contact hole CT etchings, filling, mechanical lapping
Etching, Cu plating filling, mechanical lapping, metal line layer M1 depositions and back-end process.This method is before metal line layer M1 depositions
TSV processing procedures are introduced, preferably fusion can be realized with various techniques in Fab, be a kind of the most commonly used method of current industry.
TSV lithographic process uses positive photoresist at present, so the invalid chip (ugly die) of crystal round fringes can also expose
Go out the pattern of TSV, and after the copper metal of TSV plating filling process, it can be by the Cu H of crystal round fringes 2mm2SO4It washes off, it is final brilliant
TSV within the edge of the circle 2mm width can become hollow bore (hollow TSV), as shown in Figure 1A.However the above process will
It can lead to following two serious hidden danger：
1) due to H2SO4Cu can only be removed, the barrier layers Ta/TaN stayed and SA-TEOS dielectric layers will become it
The root that the impurity that falls off afterwards generates, as shown in Figure 1B；
If 2) Cu side washings are insufficient, as shown in Figure 1 C, the Cu filled in the TSV through hole of crystal round fringes is not washed completely
Fall, after metal line layer M1 etchings, Cu will be stripped out, and not only generate serious defect, while can also pollute Al lines
Board causes serious loss.
Therefore, the TSV patterns removal of invalid chip region in crystal round fringes 2mm is become into a urgent problem to be solved.
Invention content
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.The Summary of the present invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection domain for attempting to determine technical solution claimed more.
In order to overcome the problems, such as presently, there are, the present invention provides a kind of production method of semiconductor devices, including：
Wafer is provided, the wafer includes semiconductor substrate and the device in the semiconductor substrate, and is formed
In the interlayer dielectric layer for covering the device in the semiconductor substrate；
Negative photoresist layer is formed on the interlayer dielectric layer；
Pre-exposure is carried out to the negative photoresist layer of the invalid chip area of the crystal round fringes；
The remaining unexposed negative photoresist layer is exposed and is developed, to form patterned negative photoresist layer, together
When, pattern will not be formed on the negative photoresist layer in the invalid chip area of the crystal round fringes；
Using the patterned negative photoresist layer as mask, the interlayer dielectric layer is etched, formation opening exposure is described partly to be led
Body substrate；
The part semiconductor substrate of exposure in the opening is etched, to form silicon hole；
Remove the negative photoresist layer.
Further, the width range of the invalid chip area of the crystal round fringes is 0.5~4mm.
Further, the thickness range of the negative photoresist layer is 30000~60000 angstroms.
Further, the negative photoresist layer be containing with photobehavior compound and thermoprene resinoid it is organic molten
Agent.
Further, it is also formed with hard mask layer between the interlayer dielectric layer and the negative photoresist layer.
Further, the contact plug being electrically connected with the device is also formed in the interlayer dielectric layer.
Further, the production method is suitable for the making of silicon hole, applies also for the making of interconnection structure and via layer.
In conclusion production method according to the present invention is avoided using the method for negative photoresist and crystal round fringes pre-exposure
The invalid chip area of crystal round fringes forms silicon hole pattern, not only reduces the root that the stripping problem of crystal round fringes generates,
It has been greatly reduced the risk of Cu-W ore deposit Al process work bench, and then has improved the reliability and yield of product.
Description of the drawings
The following drawings of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing：
Figure 1A shows the schematic diagram of the hollow TSV formed after crystal round fringes side washing；
Figure 1B shows the barrier layers Ta/TaN and the schematic diagram that SA-TEOS dielectric layers fall off；
Fig. 1 C show the schematic diagram of residual copper in silicon hole when Cu side washings are insufficient；
Fig. 2A -2D show cuing open for the device that each step is obtained in the technical process of existing TSV photoetching/etching a kind of
View；
Fig. 3 shows according to one embodiment of the present invention to make the process flow chart of TSV；
The device that each step is obtained in the technical process that Fig. 4 A-4F show one embodiment of the present invention to make TSV
The sectional view of part；
Fig. 5 shows the common W embolisms stripping defect schematic diagram of D18/D16 technologies；
Fig. 6 shows the schematic diagram that W embolisms stripping defect generates.
Specific implementation mode
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.Disclosure will be made thoroughly and complete on the contrary, providing these embodiments, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the areas Ceng He may be exaggerated.From beginning to end
Same reference numerals indicate identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties by person.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or " being directly coupled to " other elements or when layer, then element or layer between two parties is not present.It should be understood that although can make
Various component, assembly units, area, floor and/or part are described with term first, second, third, etc., these component, assembly units, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish a component, assembly unit, area, floor or part with it is another
One component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, portion
Part, area, floor or part are represented by second element, component, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and being used describe an elements or features shown in figure with
The relationship of other elements or features.It should be understood that other than orientation shown in figure, spatial relationship term intention further includes making
With the different orientation with the device in operation.For example, if the device in attached drawing is overturn, then, it is described as " under other elements
Face " or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related Listed Items and institute
There is combination.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, to illustrate proposition of the present invention
Technical solution.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, the present invention can be with
With other embodiment.
In the following, being described further to a kind of existing technical process of TSV photoetching/etching with reference to figure 2A-2D.
First, as shown in Figure 2 A, wafer is provided, the wafer includes semiconductor substrate 200 and is formed in semiconductor substrate
On device 201, and be formed in the semiconductor substrate 200 and cover the interlayer dielectric layer 202 of the device 201.
Silicon nitride layer 203 is also formed on the interlayer dielectric layer 202.
Patterned photoresist layer 204 is formed on the silicon nitride layer 203, the photoresist layer 204 is positive photoresist.Specifically
Ground, the spin coating photoresist layer above silicon nitride layer are exposed the photoresist layer light for being developed to have TSV through hole pattern
Resistance layer 204.Wherein, also expose TSV patterns in the invalid chip area of crystal round fringes.
It is mask with patterned photoresist layer 204 as shown in Fig. 2 B-2C, successively to silicon nitride layer 203, interlayer dielectric layer
202 and part semiconductor substrate 200 perform etching, to form silicon hole 205a and 205b, wherein silicon hole 205b is located at wafer
The invalid chip area at edge.
As shown in Figure 2 D, patterned photoresist layer is removed.
However above-mentioned technique is used, the invalid chip area of crystal round fringes (other photoresist layer maximum side washings, such as 2mm) also can
Expose the pattern of TSV.And after the copper metal plating filling process of TSV, it can be by the Cu H of crystal round fringes 2mm width2SO4It washes
Fall, the TSV within final crystal round fringes 2mm width can become hollow bore (hollow TSV), however the above process will
Lead to following two serious hidden danger：
1) due to H2SO4Cu can only be removed, the barrier layers Ta/TaN stayed and SA-TEOS dielectric layers will become de-
Fall the root of impurity generation；
If 2) Cu side washings are insufficient, the Cu filled in the TSV through hole of crystal round fringes is not washed off completely, in metal line layer
After M1 etchings, Cu will be stripped out, and not only generate serious defect, while can also pollute the board of Al lines, be caused serious
Loss.
Presence in view of the above problems, the present invention proposes a kind of new production method, to avoid in the invalid of crystal round fringes
Chip area exposes the pattern of TSV.
[Shi Lixingshishili ]
The production method of the semiconductor devices of the present invention is described in detail below in conjunction with Fig. 3 and Fig. 4 A-4F.
Wherein, Fig. 3 is shown according to one embodiment of the present invention to make the process flow chart of TSV；Fig. 4 A-4F are shown
The sectional view for the device that each step is obtained in technical process of the one embodiment of the present invention to make TSV.
Step 301 is executed, wafer is provided, the wafer includes semiconductor substrate and the device in semiconductor substrate,
And it is formed in the interlayer dielectric layer that the device is covered in the semiconductor substrate.
As shown in Figure 4 A, the semiconductor substrate 400 can be following at least one of the material being previously mentioned：Silicon, absolutely
Silicon (SOI) on edge body, stacking silicon (SSOI) on insulator, stacking SiGe (S-SiGeOI), germanium on insulator on insulator
Silicon (SiGeOI) and germanium on insulator (GeOI) etc..Active area can be defined in semiconductor substrate 400.
The device 401 may include multiple individual circuit elements, such as：Transistor, diode, resistor, capacitor,
Inductor etc.；Can also be other the active and passive semiconductor devices formed by a variety of ic manufacturing process.Fig. 4 A
In by the device 401 be transistor for illustrate, be not intended to limit protection scope of the present invention herein.
The interlayer dielectric layer 402 is formed in semiconductor substrate 400, covers the device 401, so that device 401
It is isolated with the interconnection structure being subsequently formed.The interlayer dielectric layer 402 can be single or multi-layer structure, can be specifically oxygen
SiClx layer manufactures work including the use of thermal chemical vapor deposition (thermal CVD) manufacturing process or high-density plasma (HDP)
The material layer for having doped or undoped silica that skill is formed, such as undoped silica glass (USG), phosphorosilicate glass
(PSG) or boron-phosphorosilicate glass (BPSG).In addition, interlayer dielectric layer can also be the spin cloth of coating-type glass for adulterating boron or adulterating phosphorus
(spin-on-glass, SOG), the tetraethoxysilane (PTEOS) or boron-doped tetraethoxysilane (BTEOS) for adulterating phosphorus.
The contact plug 403 being electrically connected with the device 401 is also formed in the interlayer dielectric layer 402.It is described to connect
The material for touching embolism 403 may include tungsten, copper etc., be used for interface unit and interconnection structure.The contact plug 403 it is specific
Forming method is well known for those skilled in the art, and details are not described herein.
Further, hard mask layer 404 is also formed on the interlayer dielectric layer 402, to protect interlayer dielectric layer
402.Illustratively, the hard mask layer 404 is nitride layer, such as silicon nitride.
Corresponding region is the invalid chip area 40 of crystal round fringes, illustratively, institute on the outside of phantom line segments in wherein Fig. 4 A
The width range for stating the invalid chip area 40 of crystal round fringes is 0.5~4mm, preferably 2mm.But limitation does not have above-mentioned width
Range is spent, can also have certain variation according to actual conditions such as the differences of wafer size.
Step 302 is executed, negative photoresist layer is formed on the hard mask layer.
With continued reference to Fig. 4 A, illustratively, one layer of negative photoresist layer 405 is coated on the hard mask layer 404.This can be used
Any method known to field technology personnel carries out the coating of negative photoresist layer 405, such as spin coating or curtain coating.Optionally, institute
State from about 30000 to about 60000 angstroms of the thickness range of negative photoresist layer.Negative photoresist is containing the compound with photobehavior
With the organic solvent of thermoprene resinoid, general photosensitive compound is diaryl azide.
The step of can also further comprising soft baking (Soft Baking) later, enhances negative photoresist layer 405 to remove solvent
Adhesion, discharge negative photoresist layer in stress, prevent photoresist contaminated equipment.
Step 303 is executed, pre-exposure is carried out to the negative photoresist layer of the invalid chip area of crystal round fringes.
Further include the steps that being aligned before carrying out pre-exposure, any applicable method can be used and be aligned, herein
It does not repeat.
It with reference to figure 4B, is exposed, so that segment beam is penetrated using reticle, be irradiated to the invalid chip region of crystal round fringes
It on the negative photoresist layer 405 in domain 40, reacts with negative photoresist layer 405, to realize the invalid chip area 40 of crystal round fringes
Negative photoresist layer 405 carries out pre-exposure.
Optionally, the step of (Post Exposure Bake, PEB) is dried after can also being carried out after exposure, to reduce standing wave effect
It answers.In one example, the step of being dried after being carried out using hotplate methodology.Optionally, the temperature dried afterwards is 105~115 DEG C, the time
It is 60 seconds.
Step 304 is executed, remaining unexposed negative photoresist layer is exposed and is developed, to form patterned negative light
Resistance layer.
With reference to figure 4C, so that segment beam is penetrated using reticle, be irradiated on unexposed negative photoresist layer 405, with negative light
Resistance layer 405 reacts, to be exposed to the negative photoresist layer 405 not being exposed.
Develop to the negative photoresist layer 405 after exposure, developer solution is sprayed onto to the surface of negative photoresist layer 405.Photoresist is
When negative photoresist, toluene or dimethylbenzene can be selected as developer solution.Negative photoresist is irradiated through light generates bridging reaction, through overlapping, firmly
Change, unexposed position is dissolved using developer solution and removed, carried out by the difference of exposed portion and unexposed portion generation solubility
The imaging of pattern forms the negative photoresist layer 405 with silicon hole pattern.
Due in step 303, pre-exposure having been carried out to the negative photoresist layer 405 of the invalid chip area 40 of crystal round fringes,
And since the present invention uses negative photoresist layer 405,405 developed dissolving of negative photoresist layer is unexposed region, and on wafer side
The negative photoresist layer 405 of the invalid chip area 40 of edge is all exposed, and unexposed negative photoresist layer 405 is not present, therefore
This step it is exposed and developed during, it is logical that silicon will not be formed on the negative photoresist layer in the invalid chip area 40 of crystal round fringes
Sectional hole patterns.
The step of can also further comprising drying negative photoresist layer 405 firmly later.Hard dry can remove in negative photoresist layer
Extra solvent enhances the adhesive force between negative photoresist layer and substrate, while improving negative photoresist layer 405 in etching process later
Corrosion stability and protective capability.
Step 305 is executed, using the patterned negative photoresist layer as mask, the hard mask layer is etched successively and interlayer is situated between
Electric layer forms the opening exposure semiconductor substrate.
With reference to figure 4D, it is mask with the negative photoresist layer 405 with silicon hole pattern, etches the mask layer successively
404 and interlayer dielectric layer 402, it forms opening 406a and exposes the semiconductor substrate 400.Dry etching or wet etching can be selected
The mask layer 404 and interlayer dielectric layer 402 are etched.Dry method etch technology includes but not limited to：Reactive ion etching
(RIE), ion beam milling, plasma etching or laser cutting.Dry method is carried out preferably by one or more RIE step
Etching.It should be noted that the through-silicon via structure does not destroy existing device 401 and contact plug 403, i.e., the described silicon hole
Structure is located in the interlayer dielectric layer 402 not including device 401 and contact plug 403, therefore the etching needle of this step is not to including
Device 401 and the interlayer dielectric layer of contact plug 403 402.
Step 306 is executed, the part semiconductor substrate of exposure in the opening is etched, it is logical to form silicon
Hole.
As shown in Figure 4 E, the part of exposure in the opening 406a semiconductor substrate 400 is etched, to be formed
Silicon hole 406.In the specific embodiment of the present invention, etching work of the dry etching execution to semiconductor substrate may be used
Skill, dry method etch technology include but not limited to：Reactive ion etching (RIE), ion beam milling, plasma etching or laser
Cutting.For example, by using plasma etching, etching gas may be used based on oxygen (O2- based) gas.Specifically, adopting
With lower RF energy and it can generate low pressure and highdensity plasma gas and realize dry etching.As a reality
Example, using plasma etching technics, the etching gas used is based on oxygen (O2- based) gas, the stream of etching gas
It can be 50 cc/mins (sccm)~150 cc/min (sccm) to measure range, and reaction room pressure can be 5 millitorrs
(mTorr)~20 millitorr (mTorr).Wherein, the etching gas of dry etching can also be bromination hydrogen, carbon tetrafluoride gas
Or gas of nitrogen trifluoride.It should be noted that above-mentioned engraving method is only exemplary, it is not limited to this method, ability
Field technique personnel can also select other common methods.
Only part semiconductor substrate 400 is etched, is ultimately formed through interlayer dielectric layer 402 and part semiconductor lining
The silicon hole 406 at bottom 400.
Step 307 is executed, with reference to figure 4F, removes negative photoresist layer.Any method well known to those skilled in the art can be used
Remove negative photoresist layer, such as the method etc. of ashing.
So far the photoetching to silicon hole and etching step are completed, the plating filling of copper metal, machine can also be carried out later
The techniques such as tool grinding, to form final through-silicon via structure, details are not described herein.
In another aspect of this invention, production method of the invention is applicable not only to the manufacture craft of silicon hole, can be with
Applied to interconnection structure and via layer, to solve the generation that crystal round fringes tungsten plug removes defect, and then yield is promoted.
Specifically, it is illustrated in figure 5 the common W embolisms stripping defect of D18/D16 technologies.It is illustrated in figure 6 the stripping of W embolisms
The principle that defect generates.
Due to interconnection structure every layer of metal layer formation during photoresist layer can be first coated on interlayer dielectric layer, then
Using EBR and WEE, the photoresist of crystal round fringes is removed, then carry out the etching of metal layer groove.Illustratively, as shown in fig. 6,
When forming the first metal layer 601 or intermediate metal layer 602, using EBR and WEE, remove in crystal round fringes about 2.8mm width ranges
Photoresist；When forming top layer metallic layer 603, the photoresist in crystal round fringes about 1mm width ranges is removed.The photoresist of crystal round fringes
After removal, interconnection structure/through-hole of crystal round fringes can be exposed, and W bolts are just will produce after the etch process of metal layer groove
The problem of plug stripping, metal crossover is caused, the reduction of yield is eventually led to.And it can be good at using the production method of the present invention
It solves the above problems.
In conclusion production method according to the present invention is avoided using the method for negative photoresist and crystal round fringes pre-exposure
The invalid chip area of crystal round fringes forms silicon hole pattern, not only reduces the root that the stripping problem of crystal round fringes generates,
It has been greatly reduced the risk of Cu-W ore deposit Al process work bench, and then has improved the reliability and yield of product.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, and be not intended to limit the invention within the scope of described embodiment.In addition people in the art
It is understood that the invention is not limited in above-described embodiment, introduction according to the present invention can also be made more kinds of member
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (7)
1. a kind of production method of semiconductor devices, including：
Wafer is provided, the wafer includes semiconductor substrate and the device in the semiconductor substrate, and is formed in institute
State the interlayer dielectric layer that the device is covered in semiconductor substrate；
Negative photoresist layer is formed on the interlayer dielectric layer；
Pre-exposure is carried out to the negative photoresist layer of the invalid chip area of the crystal round fringes；
The remaining unexposed negative photoresist layer is exposed and is developed, to form patterned negative photoresist layer, meanwhile, no
Pattern is formed on the negative photoresist layer that can be in the invalid chip area of the crystal round fringes；
Using the patterned negative photoresist layer as mask, the interlayer dielectric layer is etched, forms the opening exposure semiconductor lining
Bottom；
The part semiconductor substrate of exposure in the opening is etched, to form silicon hole；
Remove the negative photoresist layer.
2. manufacturing method according to claim 1, which is characterized in that the width of the invalid chip area of the crystal round fringes
Ranging from 0.5mm~4mm.
3. manufacturing method according to claim 1, which is characterized in that the thickness range of the negative photoresist layer be 30000~
60000 angstroms.
4. manufacturing method according to claim 1, which is characterized in that the negative photoresist layer is containing with photobehavior
The organic solvent of compound and thermoprene resinoid.
5. manufacturing method according to claim 1, which is characterized in that the interlayer dielectric layer and the negative photoresist layer it
Between be also formed with hard mask layer.
6. manufacturing method according to claim 1, which is characterized in that be also formed in the interlayer dielectric layer with it is described
The contact plug of device electrical connection.
7. manufacturing method according to claim 1, which is characterized in that the production method is suitable for the making of silicon hole,
Apply also for the making of interconnection structure and via layer.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1574254A (en) * | 2003-06-11 | 2005-02-02 | 新光电气工业株式会社 | Method of plating electrode formation |
| CN1667802A (en) * | 2004-03-11 | 2005-09-14 | 新光电气工业株式会社 | Plating method |
| CN101201545A (en) * | 2006-12-13 | 2008-06-18 | 中芯国际集成电路制造(上海)有限公司 | Pholithography and wafer forming by the same |
| CN103384451A (en) * | 2012-05-04 | 2013-11-06 | 群康科技(深圳)有限公司 | Manufacturing method for touch panel edge wire routing, touch panel and touch display device |
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| KR100650888B1 (en) * | 2005-12-29 | 2006-11-28 | 동부일렉트로닉스 주식회사 | Method for mornitering edge bead removal process of copper metallization layer |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1574254A (en) * | 2003-06-11 | 2005-02-02 | 新光电气工业株式会社 | Method of plating electrode formation |
| CN1667802A (en) * | 2004-03-11 | 2005-09-14 | 新光电气工业株式会社 | Plating method |
| CN101201545A (en) * | 2006-12-13 | 2008-06-18 | 中芯国际集成电路制造(上海)有限公司 | Pholithography and wafer forming by the same |
| CN103384451A (en) * | 2012-05-04 | 2013-11-06 | 群康科技(深圳)有限公司 | Manufacturing method for touch panel edge wire routing, touch panel and touch display device |
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