JP2009194189A5

JP2009194189A5 -

Info

Publication number: JP2009194189A5
Application number: JP2008034089A
Authority: JP
Filing date: 2008-02-15
Publication date: 2011-02-10
Anticipated expiration: 2028-02-15

Claims

A method for manufacturing a semiconductor device comprising the following steps:
(A) preparing a wiring board having an upper surface, a plurality of lead electrodes formed on the upper surface, and a lower surface opposite to the upper surface;
(B) a first semiconductor chip having a first main surface, a plurality of first pad electrodes formed on the first main surface, and a first back surface opposite to the first main surface; A step of mounting on the upper surface of the wiring board such that is opposed to the upper surface of the wiring board;
(C) mounting a spacer on the first main surface of the first semiconductor chip so that the plurality of first pad electrodes are exposed;
(D) electrically connecting the plurality of first pad electrodes of the first semiconductor chip and the plurality of lead electrodes of the wiring board via a plurality of first wires;
(E) a second semiconductor chip having a second main surface, a plurality of second pad electrodes formed on the second main surface, and a second back surface opposite to the second main surface; Mounting on the spacer so as to face the spacer;
(F) electrically connecting the plurality of second pad electrodes of the second semiconductor chip and the plurality of lead electrodes of the wiring board via a plurality of second wires;
here,
The plurality of first pad electrodes have unconnected pad electrodes that are not electrically connected to the lead electrodes of the wiring board,
Prior to the step (e), a dummy pattern is disposed on the unconnected pad electrode,
In the step (e), the second semiconductor chip is mounted on the spacer so that one of the plurality of second pad electrodes is positioned on the dummy pattern.

In the manufacturing method of the semiconductor device according to claim 1,
In the step (f), the second wire and the second pad electrode are connected by pressing a part of the second wire against the second pad electrode with a capillary. Method.

The method of manufacturing a semiconductor device according to claim 2.
After the step (f), the first semiconductor chip, the second semiconductor chip, the spacer, the plurality of first wires, and the plurality of second wires are sealed with resin. Production method.

In the manufacturing method of the semiconductor device according to claim 3,
The dummy pattern consists of the first wire,
In the step (d), the dummy pattern is joined to the unconnected pad electrode.

In the manufacturing method of the semiconductor device according to claim 3,
The dummy pattern is made of resin or paste material,
Prior to the step (e), the resin or the paste material is applied onto the unconnected pad electrode, and a heat treatment is performed.

In the manufacturing method of the semiconductor device according to claim 3,
The dummy pattern consists of a part of the spacer,
Prior to the step (e), the spacer is mounted on the first main surface of the first semiconductor chip such that the part of the spacer is positioned on the unconnected pad electrode. A method for manufacturing a semiconductor device.

A wiring board having an upper surface, a plurality of lead electrodes formed on the upper surface, and a lower surface opposite to the upper surface;
A first main surface; a plurality of first pad electrodes formed on the first main surface; and a first back surface opposite to the first main surface , wherein the first back surface is the top surface of the wiring board. A first semiconductor chip mounted on the upper surface of the wiring board so as to be opposed to
A spacer mounted on the first main surface of the first semiconductor chip such that the plurality of first pad electrodes are exposed ;
A second main surface, a plurality of second pad electrodes formed on the second main surface, and a second back surface opposite to the second main surface , wherein the second back surface faces the spacer. A second semiconductor chip mounted on the spacer;
Wherein the plurality of the lead electrodes of the plurality of first pad electrode and the wiring substrate of the first semiconductor chip, a plurality of first wires electrically connected,
Wherein the plurality of the lead electrodes of the plurality of second pad electrode and the wiring substrate of the second semiconductor chip, a plurality of second wires electrically connected,
It includes,
The plurality of first pad electrodes have unconnected pad electrodes that are not electrically connected to the lead electrodes of the wiring board ,
A dummy pattern is disposed on the unconnected pad electrode ,
In the second semiconductor chip, one of the plurality of second pad electrodes is the dummy pattern.
The semiconductor device is mounted on the spacer so as to be located on the surface.