JP5555400B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a package type semiconductor device and a manufacturing method thereof.

  In recent years, CSP (Chip Size Package) has attracted attention as a new packaging technology. The CSP refers to a small package having an outer dimension substantially the same as the outer dimension of a semiconductor chip.

  Conventionally, a BGA (Ball Grid Array) type semiconductor device is known as a kind of CSP. This BGA type semiconductor device is provided with a plurality of ball-like conductive terminals electrically connected to pad electrodes provided on a semiconductor substrate.

  When this BGA type semiconductor device is incorporated into an electronic device, each conductive terminal is mounted on a wiring pattern on the printed circuit board to electrically connect the semiconductor chip and an external circuit mounted on the printed circuit board. Connected.

  Such BGA type semiconductor devices are provided with a larger number of conductive terminals than other CSP type semiconductor devices such as SOP (Small Outline Package) and QFP (Quad Flat Package) having lead pins protruding from the side. It is widely used because it has the advantage that it can be downsized.

  FIG. 22 is a cross-sectional view showing a schematic configuration of a conventional BGA type semiconductor device 110. A device element 101 such as a CCD (Charge Coupled Device) type image sensor or a CMOS type image sensor is provided on the surface of a semiconductor substrate 100 made of silicon (Si) or the like, and a pad electrode 102 is a first insulating film 103. Is formed through. Further, for example, a glass substrate 104 is bonded to the surface of the semiconductor substrate 100 via a resin layer 105 made of epoxy resin or the like. A second insulating film 106 made of a silicon oxide film, a silicon nitride film or the like is formed on the side surface and the back surface of the semiconductor substrate 100.

  A wiring layer 107 electrically connected to the pad electrode 102 is formed on the second insulating film 106. The wiring layer 107 is formed on the side surface and the back surface of the semiconductor substrate 100. Further, a protective layer 108 made of a solder resist or the like is formed so as to cover the second insulating film 106 and the wiring layer 107. An opening is formed in a predetermined region of the protective layer 108 on the wiring layer 107, and a ball-like conductive terminal 109 electrically connected to the wiring layer 107 through the opening is formed.

The above-described technique is described in, for example, the following patent documents.
Japanese translation of PCT publication No. 2002-512436

  However, in the package type semiconductor device as described above, further simplification of the manufacturing process and reduction in manufacturing cost have been demanded. Further, in order to increase the mounting density, it has been required to reduce the thickness and size of the semiconductor device.

  Furthermore, a semiconductor device suitable for obtaining a high-density and small stacked structure has been demanded.

  The present invention has been made in view of the above problems, and its main features are as follows. That is, the semiconductor device of the present invention includes a semiconductor substrate, a support bonded to the surface of the semiconductor substrate such that at least a part of the outer peripheral portion protrudes from an end of the semiconductor substrate, and the support An electrode connection portion formed below the electrode connection portion, an opening on the electrode connection portion, and a protective layer covering the side surface of the semiconductor substrate, and a wiring layer is formed on the back surface of the semiconductor substrate. It is characterized by not.

  Further, the semiconductor device of the present invention includes a semiconductor substrate having an opening penetrating from the front surface to the back surface, a support bonded to the surface of the semiconductor substrate, and an electrode connection portion formed below the support. And a protective layer covering the side surface of the semiconductor substrate, and having no opening on the back surface of the semiconductor substrate.

  The semiconductor device of the present invention is characterized in that the support has a through-hole penetrating from the front surface to the back surface at a position where it is connected to an electrode of another device.

  Further, the semiconductor device of the present invention is a stacked semiconductor device configured by stacking a plurality of the semiconductor devices, and electrical connection between the semiconductor devices is performed through the through holes. It is characterized by being.

  The main features of the semiconductor device manufacturing method of the present invention are as follows. That is, preparing a semiconductor substrate having an electrode connection portion formed on the surface via an insulating film, attaching a support on the surface of the semiconductor substrate, removing the semiconductor substrate and the insulating film, and The method has a step of exposing the electrode connection portion and a step of forming a protective layer having an opening on the electrode connection portion, and does not have a step of forming a wiring layer on the back surface of the semiconductor substrate. .

  The method for manufacturing a semiconductor device according to the present invention includes a step of forming a through-hole penetrating the support at a position corresponding to an electrode of another device in the support.

  In addition, the method for manufacturing a semiconductor device according to the present invention includes a step of forming a conductive terminal in the through hole.

  The method for manufacturing a semiconductor device according to the present invention includes a step of dividing the semiconductor device into individual semiconductor chips along a dicing line, and a step of stacking the individual semiconductor chips via conductive terminals formed in the through holes. It is characterized by that.

  According to the present invention, the number of manufacturing steps is simplified, and the use of metal materials such as aluminum, aluminum alloys, and copper necessary for wiring formation can be suppressed, so that the manufacturing cost can be reduced. In addition, the semiconductor device can be reduced in thickness and size.

  Further, when a through hole is formed in the support bonded to the semiconductor substrate, the upper and lower devices can be electrically connected through the through hole. Therefore, a stacked structure of a plurality of semiconductor devices can be realized, and the stacked structure can be reduced in thickness and size.

  Next, a first embodiment of the present invention will be described with reference to the drawings. 1 to 6 are cross-sectional views shown in the order of manufacturing steps.

  First, as shown in FIG. 1, a semiconductor substrate 2 made of silicon (Si) or the like on which a device element 1 (for example, a light receiving element such as a CCD or an infrared sensor, a light emitting element, or other semiconductor elements) is formed is formed. prepare. The semiconductor substrate 2 has a thickness of about 300 μm to 700 μm, for example. Then, a first insulating film 3 (for example, a silicon oxide film formed by a thermal oxidation method, a CVD method, or the like) is formed on the surface of the semiconductor substrate 2 to a thickness of 2 μm, for example.

  Next, a metal layer such as aluminum (Al), aluminum alloy, or copper (Cu) is formed by sputtering, plating, or other film formation methods, and then the metal layer is etched using a resist layer (not shown) as a mask. The pad electrode 4 is formed on the first insulating film 3 to a thickness of, for example, 1 μm. The pad electrode 4 is an external connection electrode that is electrically connected to the device element 1 and its peripheral elements via a wiring (not shown). In FIG. 1, the pad electrode 4 is disposed on both sides of the device element 1, but the position thereof is not limited, and the pad electrode 4 may be disposed on the device element 1.

  Next, a passivation film 5 (for example, a silicon nitride film formed by a CVD method) that covers part or all of the pad electrode 4 is formed on the surface of the semiconductor substrate 2. In FIG. 1, a passivation film 5 is formed so as to cover a part of the pad electrode 4.

  Next, a support 7 is bonded onto the surface of the semiconductor substrate 2 including the pad electrode 4 via an adhesive layer 6 such as epoxy resin, polyimide (for example, photosensitive polyimide), resist, or acrylic.

  The support 7 may be, for example, a film-like protective tape, or may be made of glass, quartz, ceramic, metal, resin, or the like. Further, it is preferable that the support body 7 is a rigid substrate in order to firmly support the semiconductor substrate 2 to be thinned and to automate conveyance without human intervention. The support 7 has a function of supporting the semiconductor substrate 2 and protecting the element surface. When the device element 1 is a light receiving element or a light emitting element, the support 7 is made of a transparent or translucent material and has a property of transmitting light.

  Next, back grinding is performed on the back surface of the semiconductor substrate 2 using a back grinding device (grinder) to reduce the thickness of the semiconductor substrate 2 to a predetermined thickness (for example, about 50 μm). The grinding process may be an etching process, or a combination of a grinder and an etching process. Depending on the use and specifications of the final product and the initial thickness of the prepared semiconductor substrate 2, the grinding step may not be necessary.

  Next, as shown in FIG. 2, only a predetermined region corresponding to the pad electrode 4 in the semiconductor substrate 2 is selectively etched from the back side of the semiconductor substrate 2 to partially expose the first insulating film 3. Let Hereinafter, this exposed portion is referred to as an opening 8.

  The selective etching of the semiconductor substrate 2 will be described with reference to FIGS. 3A and 3B are schematic plan views seen from below (semiconductor substrate 2 side), and FIG. 2 is a cross-sectional view taken along the line P-P in FIGS. 3A and 3B. Corresponding.

  As shown in FIG. 3A, the semiconductor substrate 2 can be etched into a substantially rectangular shape that is narrower than the width of the support 7. Further, as shown in FIG. 3B, only the region where the pad electrode 4 is formed may be etched so that the outer periphery of the semiconductor substrate 2 becomes uneven. In the latter case, the overlapping area of the semiconductor substrate 2 and the support 7 is larger, and the semiconductor substrate 2 remains near the outer periphery of the support 7. Therefore, the latter configuration is preferable from the viewpoint of improving the support strength of the support 7 with respect to the semiconductor substrate 2. Moreover, according to the latter structure, since the curvature of the support body 7 by the difference in the thermal expansion coefficient of the semiconductor substrate 2 and the support body 7 can be prevented, the crack and peeling of a semiconductor device can be prevented. It is possible to design the semiconductor substrate 2 in a shape different from the planar shape shown in FIGS.

  In the present embodiment, the side wall of the semiconductor substrate 2 is etched obliquely so that the width of the semiconductor substrate 2 increases toward the front surface side. However, the width of the semiconductor substrate 2 is constant, and the side wall is a support. Etching may be performed so as to be perpendicular to the main surface of 7.

  Next, as shown in FIG. 4, the first insulating film 3 is selectively etched using the semiconductor substrate 2 as a mask. By this etching, the first insulating film 3 in the region from the end of the semiconductor substrate 2 to the predetermined dicing line is removed, and one surface of the pad electrode 4 (surface on the semiconductor substrate 2 side) at the bottom of the opening 8. Is exposed. Note that the etching can also form a resist layer and use the resist layer as a mask.

  Next, as shown in FIG. 5, a metal layer 9 is formed on the exposed pad electrode 4. The metal layer 9 is a layer in which, for example, a nickel (Ni) layer and a gold (Au) layer are sequentially laminated, and a lift-off method in which these metals are sequentially sputtered using the resist layer as a mask, and then the resist layer is removed, plating It can be formed by the method.

  In addition, the material of the metal layer 9 can be appropriately changed according to the material of the conductive terminal 12 to be formed thereafter and the electrode of another device. That is, in addition to the nickel layer and the gold layer, a titanium (Ti) layer, a tungsten (W) layer, a copper (Cu) layer, a tin (Sn) layer, or the like may be used. The material of the metal layer 9 is not particularly limited as long as it has a function of protecting the pad electrode 4 through electrical connection between the pad electrode 4 and the conductive terminal 12 or an electrode of another device. It may be a single layer or a laminate. Examples of the laminated structure are nickel layer / gold layer, titanium layer / nickel layer / copper layer, titanium layer / nickel vanadium layer / copper layer, and the like.

  Next, by partially removing the support 7 from the semiconductor substrate 2 side by a dicing blade or etching, a V-shaped groove 10 (notch groove) is formed along the dicing line DL.

  Next, a protective layer 11 having an opening at a position corresponding to the pad electrode 4 and the metal layer 9 is formed with a thickness of, for example, 10 μm. The opening is formed on the main surface of the pad electrode 4 on the semiconductor substrate 2 side.

  For example, the protective layer 11 is formed as follows. First, an organic material such as polyimide resin or solder resist is applied to the entire surface by a coating / coating method, and heat treatment (pre-baking) is performed. Next, the applied organic material is exposed to light and developed to form an opening that exposes the surface of the metal layer 9, and then heat treatment (post-bake) is applied to the pad electrode 4 and the metal layer 9. A protective layer 11 having an opening at a position to be obtained is obtained.

  Next, as shown in FIG. 6, a conductive material (for example, solder) is screen-printed on the metal layer 9 exposed at the opening of the protective layer 11, and the solder is reflowed by heat treatment to form the ball-shaped conductive terminal 12. To do. The conductive terminal 12 in this embodiment corresponds to the position of the pad electrode 4 and is formed along the outer periphery of the support 7. The conductive terminal 12 is an electrode that is adjacent to the side wall of the semiconductor substrate 2 and protrudes in the vertical direction with respect to the support 7. In addition, the conductive terminal 12 is formed to be approximately equal to or slightly higher than the height (thickness) of the semiconductor substrate 2.

  The method for forming the conductive terminal 12 is not limited to the above, and may be an electrolytic plating method using the metal layer 9 as a plating electrode, a so-called dispensing method (coating method) in which solder or the like is applied using a dispenser, or the like. It can also be formed. The conductive terminal 12 may be made of gold, copper, or nickel, and the material is not particularly limited. In some cases, the conductive terminal 12 is not formed as described below. In this case, the metal layer 9 or the pad electrode 4 is exposed from the opening of the protective layer 11 to the outside.

  Finally, it is divided along the dicing line DL and divided into individual semiconductor devices 20. In addition, as a method of dividing | segmenting into each semiconductor device 20, there exist a dicing method, an etching method, a laser cut method, etc. Thus, the semiconductor device according to this embodiment is completed.

  The completed semiconductor device 20 is mounted on a circuit board on which external electrodes are patterned. In this mounting, the conductive terminal 12 is electrically connected to the electrode on the circuit board. When the conductive terminal 12 is not formed, the metal layer 9 or the pad electrode 4 is directly connected to the electrode on the circuit board or connected through a conductive substance such as a bonding wire. A configuration in which the conductive terminal 12 is not formed in the semiconductor device 20 and the pad electrode 4 is connected to the electrode on the circuit board is shown in FIGS. 12 and 13 described later.

  According to the first embodiment, the step of forming the wiring layer 107 and the second insulating film 106 extending on the side surface and the back surface of the semiconductor substrate as shown in the conventional semiconductor device (FIG. 22) is unnecessary. . Therefore, the manufacturing process is simplified and the productivity is improved, and the manufacturing cost can be kept low.

  In the semiconductor device of this embodiment, the conductive terminal 12 is not formed on the back surface of the semiconductor substrate 2 but is formed on the outer peripheral portion of the support 7 and adjacent to the outside of the side wall of the semiconductor substrate 2. ing. Therefore, when the thickness of the conductive terminal 12 is the same as that of the conventional one, the thickness of the semiconductor device is equivalent to the height of the conductive terminal as compared with the conventional structure in which the conductive terminal is formed on the back surface of the semiconductor substrate. As a result, the semiconductor device can be made thinner and smaller.

  In the above description, the end of the semiconductor substrate 2 and the end of the pad electrode 4 are separated from each other. However, the end of the pad electrode 4 is disposed on a part of the surface of the semiconductor substrate 2. 2 can also be etched. That is, a portion of the pad electrode 4 corresponding to the metal layer 9 or the conductive terminal 12 to be formed later, or a portion corresponding to an electrode of another device (hereinafter referred to as an electrode connection portion 13) overlaps with the semiconductor substrate 2. If you don't. Therefore, if a part of the pad electrode 4 becomes the electrode connection portion 13 such as when the area of the pad electrode 4 is large, the end portion of the semiconductor substrate 2 and the end portion of the pad electrode 4 overlap as shown in FIG. Thus, the semiconductor substrate 2 can be etched.

  In the above description, the adhesive layer 6 is uniformly formed between the semiconductor substrate 2 and the support 7. However, the adhesive layer 6 may be partially formed. For example, by forming the adhesive layer 6 in a ring shape, a cavity 14 (Cavity) as shown in FIG. 8 can be formed between the semiconductor substrate 2 and the support 7. The cavity 14 is an internal space between the semiconductor substrate 2 and the support 7. In FIG. 8, an electronic device such as a MEMS (Micro Electro Mechanical Systems) element 15 is formed on the semiconductor substrate 2 via the insulating film 3 using the cavity 14. MEMS is a device in which mechanical element parts, sensors, actuators, electronic circuits and the like are integrated on a semiconductor substrate. The MEMS element 15 is electrically connected to the pad electrode 4 via a wiring (not shown).

  As described above, the operation quality of the semiconductor device may be improved by preventing the adhesive layer 6 from being formed on the device element. For example, in the case where a light receiving element or a light emitting element is formed, the operation quality is improved because no extra substance is interposed.

  The height and width of the cavity 14 can be adjusted by the thickness of the adhesive layer 6.

  Further, a step as shown in FIG. 9 may be formed on the surface of the semiconductor substrate 2 by etching or the like, and various elements including the MEMS element 16 may be formed in a portion (step bottom 16) which is lowered by the step. . According to such a configuration, the step between the semiconductor substrate 2 and the support 7 is expanded by a step, so that an element having a thickness larger than that of the configuration in FIG. 8 can be formed on the semiconductor substrate 2. Further, the space 14 can be freely adjusted by combining the adjustment of the depth of the step of the semiconductor substrate 2 and the adjustment of the thickness of the adhesive layer 6.

  Furthermore, as shown in FIG. 10, in one surface of the support 7 (surface facing the semiconductor substrate 2) by etching, laser beam irradiation, microblasting, or the like, in a region facing the device element such as the MEMS element 15 The recess 17 may be formed. According to such a configuration, since the space between the semiconductor substrate 2 and the support 7 in the region is further expanded, the space 14 can be freely adjusted as compared with the configurations of FIGS. Device elements can be formed on the semiconductor substrate 2. Microblasting is a method of processing an object by injecting fine particles such as alumina and silica onto the object.

  Moreover, although the support body 7 is bonded together in 1st Embodiment, it is also possible to isolate | separate the semiconductor substrate 2 and the support body 7 by supplying a dissolving agent to the contact bonding layer 6 before and after a dicing process. It is. The removed support 7 can be reused.

  Next, a case where the semiconductor device according to the first embodiment of the present invention is mounted on a circuit board (module board) will be described with reference to the drawings. FIG. 11A is a plan view of a device on which the semiconductor device according to this embodiment is mounted as viewed from above, and FIG. 11B is a cross-sectional view taken along line XX in FIG. It is. Note that the same components as those already shown are denoted by the same reference numerals, and the description thereof is omitted.

  As shown in FIG. 11A, the semiconductor device 20 is placed on a circuit board 30A such as a printed board. The semiconductor device 20 is placed so that the back surface side (the side on which the support 7 is not formed) faces the circuit board 30A. On the circuit board 30 </ b> A, electrodes 31 are patterned at positions corresponding to the conductive terminals 12 of the semiconductor device 20.

  The conductive terminal 12 and the electrode 31 are directly electrically connected. As described above, unlike the conventional semiconductor device 110 (see FIG. 22), since the conductive terminal is not formed on the back surface of the semiconductor substrate, the entire device can be thinned.

  Also, the mounting of the semiconductor device according to the present embodiment on a circuit board can be performed as shown in FIG. 12A is a plan view of a device in which the semiconductor device 20a according to the present embodiment is mounted on the circuit board 30B as viewed from above, and FIGS. 12B and 13A are FIGS. It is sectional drawing along the YY line of). Here, the semiconductor device 20a shows a state where the conductive terminal 12 is not formed and the pad electrode 4 is exposed. Note that the same components as those already shown are denoted by the same reference numerals, and the description thereof is omitted.

  As shown in FIG. 12B, a space (fitting portion 32) corresponding to the shape of the semiconductor device 20a is formed on the surface side of a circuit board 30B such as a printed circuit board. The semiconductor device 20a is placed so as to be embedded therein. Such a fitting portion 32 is formed by, for example, etching by laser irradiation or cutting by a drill.

  A wiring layer 33 made of, for example, copper or aluminum is formed as wiring inside the circuit board 30B. In addition, a conductive terminal 34 as an electrode on the circuit board 30 </ b> B side is formed on the wiring layer 33 via a metal layer 35. The conductive terminal 34 is electrically connected to the pad electrode 4 of the semiconductor device 20a.

  The conductive terminal 34 of the circuit board 30B has the same configuration as that of the conductive terminal 12 of the semiconductor device 20 (FIG. 6), and the metal layer 35 has the same configuration as that of the metal layer 9 of the semiconductor device 20. Further, the metal layer 9 may be provided on the pad electrode 4 of the semiconductor device 20a, and the metal layer 9 may be interposed between the pad electrode 4 and the conductive terminal.

  Further, as shown in FIG. 13B, it is preferable to form a heat dissipation layer 36 (for example, a copper layer) having high thermal conductivity at the bottom of the fitting portion 32. By providing the heat dissipation layer 36 on the contact surface between the circuit board 30B and the semiconductor device 20a in this way, heat generated during the operation of the semiconductor device 20a can be transferred from the bottom to the heat dissipation layer 36 and released to the outside. Therefore, deterioration of device elements such as transistors due to heat can be effectively prevented. In addition, dark current can be reduced. In particular, if the device element is an element such as a CCD whose electrical characteristics are likely to be deteriorated by heat, the performance is prevented from being deteriorated and the operation quality is improved as compared with the configuration in which the heat dissipation layer 36 is not provided.

  Further, from the viewpoint of improving heat radiation and improving the operation quality, the semiconductor device 20b can be configured without forming the protective layer 11 on the back surface side of the semiconductor substrate 2 as shown in FIG. This configuration can be obtained, for example, by forming an opening for opening the pad electrode 4 or the metal layer 9 and simultaneously removing the protective layer on the back surface of the semiconductor substrate 2. According to such a configuration, heat generated during operation can be directly transferred from the back surface of the semiconductor substrate 2 to the heat dissipation layer 36 and released to the outside, so that the heat dissipation effect is high.

  Further, the arrangement position of the metal layer 35 and the conductive terminal 34 on the circuit board side can be located above the circuit board 40 as shown in FIG. It is easier to form the conductive terminal 34 by arranging the conductive terminal 34 in the upper portion of the circuit board 40 in this way than arranging the conductive terminal 34 deep in the fitting portion 32.

  Although not shown, the heat radiation effect can be obtained by slightly separating the back surface of the semiconductor device from the circuit board without forming a clear heat radiation layer 36.

  12B, 13A, and 13B, the surface of the heat dissipation layer 36 is in direct contact with the semiconductor device in the fitting portion 32. An insulating film such as a silicon oxide film, a silicon nitride film, or a resin film may be formed on the 40 heat dissipation layer 36.

  Also, the mounting of the semiconductor device according to the present embodiment on a circuit board can be performed as shown in FIG. 14A is a plan view of a device in which the semiconductor device 20 according to the present embodiment is mounted on the circuit board 30C as viewed from above, and FIG. 14B is a ZZ line in FIG. 14A. FIG. Note that the same components as those already shown are denoted by the same reference numerals, and the description thereof is omitted.

  As shown in FIG. 14B, a space (fitting portion 37) corresponding to the shape of the semiconductor device 20 is formed in the circuit board 30C. The fitting portion 37 penetrates the circuit board 30C. And it arrange | positions so that the semiconductor device 20 may be embedded in the said fitting part 37, and the back surface of the semiconductor device 20 is exposed from the circuit board 30C. Such a fitting portion 37 is formed by etching by laser irradiation, cutting by a drill, or the like.

  A wiring layer 33 is formed inside the circuit board 30 </ b> C and is connected to the conductive terminal 12 of the semiconductor device 20. Further, when the semiconductor device 20 is placed, if there is a space between the side wall of the fitting portion 37 of the circuit board 30C and the semiconductor device 20, an underfill 38 made of, for example, epoxy resin is filled. To fill the space with good fit.

  Unlike the circuit board 30B described above, the circuit board 30C does not have the heat dissipation layer 36. However, as shown in FIG. 14B, the circuit board 30C is mounted so that the bottom of the semiconductor device 20 is exposed to the outside. Can escape to the outside. Therefore, it is possible to effectively prevent device elements from being deteriorated due to heat during operation.

  Next, a second embodiment of the present invention will be described with reference to the drawings. When realizing a stacked structure of a completed semiconductor device, it is necessary to reduce the height of the stacked device as much as possible to reduce the size of the entire device.

  Therefore, in the second embodiment of the present invention, in addition to the manufacturing process of the semiconductor device according to the first embodiment, a manufacturing process suitable for manufacturing a semiconductor device for stacking is employed. Details will be described below. In addition, the same code | symbol is used about the structure similar to 1st Embodiment, The description of the manufacturing process is simplified or abbreviate | omitted.

  As shown in FIG. 15, a semiconductor substrate 2 having a pad electrode 4 formed on the surface via a first insulating film 3 is prepared, and a support 7 is attached to the surface of the semiconductor substrate 2 via an adhesive layer 6. . Next, the semiconductor substrate 2 and the first insulating film 3 are partially removed from the back surface side of the semiconductor substrate 2 by etching to expose the pad electrode 4. Next, a metal layer 9 is formed on the exposed pad electrode 4.

  Next, a V-shaped groove 10 (notched groove) is formed along the dicing line DL from the semiconductor substrate 2 side by a dicing blade or etching. Next, a protective layer 11 having an opening at a position corresponding to the metal layer 9 is formed. The above process is the same as the manufacturing process according to the first embodiment described above.

  Next, as shown in FIG. 16, a through hole 41 that penetrates the support 7 and exposes the pad electrode 4 from the support 7 side is formed at a position corresponding to the pad electrode 4 in the support 7. Specifically, for example, a resist layer is formed on the surface of the support 7, the support 7 is selectively etched using the resist layer as a mask to expose the adhesive layer 6, and then the adhesive layer 6 is etched. The through hole 41 is, for example, a substantially square having a side of about 100 μm.

  Next, a metal layer 42 is formed on the pad electrode 4 exposed at the bottom of the through hole 41. The metal layer 42 has the same configuration as that of the metal layer 9 described above. For example, a nickel (Ni) layer and a gold (Au) layer are sequentially stacked. Thereby, the metal layers 9 and 42 are formed on both main surfaces of the pad electrode 4.

  Next, as shown in FIG. 17, the metal layer 9 exposed on the semiconductor substrate 2 side and the metal layer 42 exposed on the support 7 side are both electrically conductive on the metal layer 9 by an electrolytic plating method using plating electrodes. The terminal 12 and the conductive terminal 43 are simultaneously formed on the metal layer 42. Thus, rationalization of the manufacturing process is achieved by simultaneously forming the conductive terminals 12 and 43. In addition, it is the same as that of 1st Embodiment that the formation method of the conductive terminals 12 and 43 is not limited to this.

  Finally, it is divided along the dicing line DL and divided into individual semiconductor devices 50. Thus, the semiconductor device according to the second embodiment is completed. The completed semiconductor device 50 is mounted on a circuit board on which external electrodes are patterned.

  According to the completed semiconductor device 50, as shown in FIG. 18, a plurality of layers are stacked so that the conductive terminals 12 and 43 of the upper and lower devices are aligned, and the stacked structure is formed by connecting the conductive terminals by, for example, thermocompression bonding. It is possible to realize. FIG. 18 shows an example in which the semiconductor devices 50 are stacked to form a stacked structure.

  As described above, also in the second embodiment of the present invention, the process of forming the wiring layer 107 and the second insulating film 106 as in the conventional example is unnecessary, so that productivity is improved and manufacturing cost is reduced. There is an advantage that can be suppressed. Moreover, since the surface of the semiconductor substrate 2 is protected by the support body 7, the device element 1 formed on the surface and its peripheral elements can be prevented from being deteriorated, and the reliability of the semiconductor device can be increased.

  A laminated structure can be realized by joining the conductive terminals 12 and 43 of the upper and lower semiconductor devices through the through holes 41 provided in the support 7, and the height thereof can be minimized. Further, since the semiconductor device 50 can be stacked at the same time as the semiconductor device 50 is completed, workability and efficiency are good.

  Similarly to the first embodiment, either one or both of the conductive terminal 12 on the semiconductor substrate 2 side and the conductive terminal 43 in the through hole 41 may not be formed. When the conductive terminal 12 is formed and the conductive terminal 43 is not formed in the through hole 41, the metal layer 42 or the pad electrode 4 is exposed in the through hole 41 as shown in FIG. The conductive terminal 12 is connected to an electrode of another device below the semiconductor device 50 a, and the metal layer 42 or the pad electrode 4 in the through hole 41 is electrically connected to an electrode of another device above the semiconductor device 50. Is done.

  Further, when the conductive terminal 43 is formed in the through hole 41 without forming the conductive terminal 12, as shown in FIG. 20, the conductive terminal 43 is connected to the electrodes of other devices above the semiconductor device 50b. Then, the metal layer 9 or the pad electrode 4 is connected to an electrode of another device below the semiconductor device 50b.

  Further, in the second embodiment, the through hole 41, the metal layer 42, and the conductive terminal 43 are formed at positions corresponding to the pad electrode 4, the metal layer 9, and the conductive terminal 12 in the support 7, but the positions are not necessarily limited thereto. However, it can be formed at any position as long as it can be connected to electrodes of other devices above the semiconductor device 50. Therefore, it can be stacked with semiconductor devices having different chip functions and sizes.

  In the above embodiment, the BGA (Ball Grid Array) type semiconductor device having the ball-shaped conductive terminals 12 and 42 has been described. However, the present invention is not limited to the LGA (Land Grid Array) having the ball-shaped conductive terminals. ) Type and other CSP type and flip chip type semiconductor devices.

  Moreover, it goes without saying that the present invention is not limited to the above-described embodiment and can be changed without departing from the gist thereof.

  For example, the opening 60 may be provided as shown in FIG. 21A by changing the etching pattern of the semiconductor substrate 2 and the position of the dicing line. FIG. 21B is a schematic plan view of the state where the conductive terminal 12 is formed in the opening 60 as viewed from the back side of the semiconductor device. FIG. 21A is a cross-sectional view taken along line QQ in FIG.

  The periphery of the opening 60 is surrounded by the semiconductor substrate 2. Then, the conductive terminal 12 can be formed in the opening 60. The conductive terminal 12 of the semiconductor device 65 of the modified example is exposed from the back surface side of the semiconductor device, but is not exposed from the side surface side. Therefore, intrusion of corrosive materials, mechanical damage, and the like are reduced, and the reliability of the semiconductor device can be improved.

  Moreover, although the conductive terminal 12 of the semiconductor device 65 is also formed slightly higher than the height of the semiconductor substrate 2, the height can be arbitrarily changed. For example, the height of the conductive terminal 12 may be lower than the height of the semiconductor substrate 2 as long as the electrode of another device to which the conductive terminal 12 is connected protrudes. 21A and 21B, the conductive terminal 12 is formed along the outer periphery of the semiconductor device 65, but the opening 60 and the conductive terminal 12 are formed depending on the positions of the pad electrode 4 and the metal layer 9. The position of may be changed.

  When the conductive terminal 12 is not formed in the semiconductor device 65, the metal layer 9 or the pad electrode 4 is exposed in the opening 60 and is electrically connected to an electrode of another device through the opening 60. . In addition, the semiconductor device 65 can naturally be provided with the already described through holes in the support, and the semiconductor device 65 can be used to form a stacked semiconductor device as shown in FIG. is there.

  Further, as shown in the semiconductor device 65, the V-shaped groove 10 may not be provided. In FIG. 21, the same components as those already described are denoted by the same reference numerals, and the description thereof is omitted.

  Further, in the plan views of FIGS. 11A, 12A, and 14A, the semiconductor substrate 2 is drawn in a substantially rectangular shape as shown in FIG. As shown in b), the outer periphery may be configured to be uneven, or the shape can be changed according to the design.

It is sectional drawing explaining the semiconductor device which concerns on the 1st Embodiment of this invention, and its manufacturing method. It is sectional drawing explaining the semiconductor device which concerns on the 1st Embodiment of this invention, and its manufacturing method. 1 is a plan view illustrating a semiconductor device and a manufacturing method thereof according to a first embodiment of the present invention. It is sectional drawing explaining the semiconductor device which concerns on the 1st Embodiment of this invention, and its manufacturing method. It is sectional drawing explaining the semiconductor device which concerns on the 1st Embodiment of this invention, and its manufacturing method. It is sectional drawing explaining the semiconductor device which concerns on the 1st Embodiment of this invention, and its manufacturing method. It is sectional drawing explaining the semiconductor device which concerns on the 1st Embodiment of this invention, and its manufacturing method. It is sectional drawing explaining the semiconductor device which concerns on the 1st Embodiment of this invention, and its manufacturing method. It is sectional drawing explaining the semiconductor device which concerns on the 1st Embodiment of this invention, and its manufacturing method. It is sectional drawing explaining the semiconductor device which concerns on the 1st Embodiment of this invention, and its manufacturing method. It is the top view and sectional drawing explaining the mounting state of the semiconductor device which concerns on the 1st Embodiment of this invention. It is the top view and sectional drawing explaining the mounting state of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing explaining the mounting state of the semiconductor device which concerns on the 1st Embodiment of this invention. It is the top view and sectional drawing explaining the mounting state of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing explaining the semiconductor device which concerns on the 2nd Embodiment of this invention, and its manufacturing method. It is sectional drawing explaining the semiconductor device which concerns on the 2nd Embodiment of this invention, and its manufacturing method. It is sectional drawing explaining the semiconductor device which concerns on the 2nd Embodiment of this invention, and its manufacturing method. It is sectional drawing explaining the laminated structure using the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing explaining the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing explaining the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing and a top view explaining the semiconductor device of the example of a change of this invention. It is sectional drawing explaining the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Device element 2 Semiconductor substrate 3 1st insulating film 4 Pad electrode 5 Passivation film 6 Adhesive layer 7 Support body 8 Opening part 9 Metal layer 10 V-shaped groove 11 Protective layer 12 Conductive terminal 13 Electrode connection part 14 Cavity 15 MEMS element 16 Step bottom 17 Recess 20 Semiconductor device 30A, 30B, 30C Circuit board 31 Electrode 32 Fitting part 33 Wiring layer 34 Conductive terminal 35 Metal layer 36 Heat radiation layer 37 Fitting part 38 Underfill 40 Circuit board 41 Through hole 42 Metal layer 43 Conductive terminal
50, 50a, 50b Semiconductor device 60 Opening 65 Semiconductor device 100 Semiconductor substrate 101 Device element
102 pad electrode 103 first insulating film 104 glass substrate 105 resin layer 106 second insulating film 107 wiring layer 108 protective layer 109 conductive terminal 110 semiconductor device

Claims (20)

A semiconductor substrate having a pad electrode formed on the surface side;
An electrode connection portion formed of the pad electrode and surrounding the semiconductor substrate in a region separated from the semiconductor substrate;
On the region extending from the surface of the semiconductor substrate to the outside of the electrode connection portion, a support bonded together,
A wiring layer that has an opening on the back surface of the electrode connection portion and covers a side surface of the semiconductor substrate, and is connected to the back surface of the electrode connection portion and extends on the back surface of the semiconductor substrate There is not formed, and wherein a said electrode connection portion functions as an external connection electrode connected to the conductive terminal of the other devices or members. A semiconductor substrate having a pad electrode formed on the surface side ;
An electrode connection portion formed of the pad electrode and surrounding the semiconductor substrate in a region separated from the semiconductor substrate ;
On the region extending from the surface of the semiconductor substrate to the outside of the electrode connection portion, a support bonded together,
An opening on the back surface of the electrode connection portion, and a protective layer covering the side surface of the semiconductor substrate, and a wiring layer is not formed on the back surface of the semiconductor substrate, and on the back surface of the electrode connection portion. A semiconductor device, wherein a conductive terminal is formed on the semiconductor device. The semiconductor device according to claim 1, wherein an outer periphery of the semiconductor substrate has a shape including a plurality of depressions and protrusions, and the electrode connection part is formed in the depression. A semiconductor substrate having a pad electrode formed on the surface side;
A support bonded to the surface of the semiconductor substrate;
An opening penetrating from the front surface to the back surface of the semiconductor substrate;
An electrode connecting portion composed of the pad electrode exposed in the opening;
A wiring layer having an opening on a back surface of the electrode connection portion and covering a side wall of the opening portion and connected to the back surface of the electrode connection portion and extending on the back surface of the semiconductor substrate There is not formed, and wherein a said electrode connection portion functions as an external connection electrode connected to the conductive terminal of the other devices or members.   5. The semiconductor device according to claim 1, wherein the entire pad electrode constitutes the electrode connection portion. The support is in a position to be connected to the electrode of the other device, the semiconductor device according to any one of claims 1 to 4, characterized in that it has a through hole penetrating toward the rear surface from the surface. The semiconductor device according to claim 6 , wherein the position connected to the electrode of the other device is a position overlapping with the electrode connecting portion. The semiconductor device according to claim 6 , wherein a conductive terminal is formed in the through hole of the support. The semiconductor device according to any one of claims 1 to 4, characterized in that the back surface of the semiconductor substrate is exposed without being covered with the protective layer. The semiconductor substrate and the support are bonded to each other via an adhesive layer, the adhesive layer is partially formed, and a cavity is formed between the semiconductor substrate and the support. claim 1 to semiconductor device according to claim 4. At least a portion of the electrode connection part, the semiconductor device according to any one of claims 1 to 4, characterized in that it is coated with a passivation film. Wherein a semiconductor device of a stacked semiconductor device is constituted by a plurality of stacked according to any one of claims 6 to 11, electrical connection the support between each other each semiconductor device A laminated semiconductor device, which is performed through a through-hole of a body. 13. A semiconductor device, wherein the semiconductor device according to any one of claims 1 to 12 is mounted on a circuit board. Prepare a semiconductor substrate having an electrode connection portion formed on the surface via an insulating film,
A step of attaching a support on the surface of the semiconductor substrate;
Removing the semiconductor substrate and the insulating film to expose a back surface of the electrode connecting portion;
Forming a protective layer having an opening on the back surface of the electrode connection portion, and
For external connection in which the electrode connection portion is connected to the conductive terminal of another device or member without the step of forming a wiring layer connected to the back surface of the electrode connection portion and extending on the back surface of the semiconductor substrate A method for manufacturing a semiconductor device, which functions as an electrode . Prepare a semiconductor substrate having an electrode connection portion formed on the surface via an insulating film,
A step of attaching a support on the surface of the semiconductor substrate;
Removing the semiconductor substrate and the insulating film to expose a back surface of the electrode connecting portion;
Forming a protective layer having an opening on the back surface of the electrode connection portion, and forming a wiring layer connected to the back surface of the electrode connection portion and extending on the back surface of the semiconductor substrate. no, after the step of exposing the back surface of the electrode connecting portions, characterized by having a step of forming a conductive terminal on the back surface of the electrode connecting portion exposed to the spaced-apart regions from the side wall of said semiconductor substrate A method for manufacturing a semiconductor device. The method according to claim 14 or semiconductor device according to claim 15, characterized in that a step of separating said support from said semiconductor substrate. 16. The method of manufacturing a semiconductor device according to claim 14 , further comprising a step of forming a through-hole penetrating the support body at a position corresponding to an electrode of another device in the support body. Method.   18. The method of manufacturing a semiconductor device according to claim 17, wherein the position corresponding to the electrode of the other device is a position overlapping with the electrode connection portion.   The method of manufacturing a semiconductor device according to claim 17, further comprising a step of forming a conductive terminal in the through hole. Dividing into individual semiconductor chips along dicing lines;
The method of manufacturing a semiconductor device according to claim 19, further comprising a step of stacking the individual semiconductor chips via conductive terminals formed in the through holes.

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