SG139616A1 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof

Info

Publication number
SG139616A1
SG139616A1 SG200702666-9A SG2007026669A SG139616A1 SG 139616 A1 SG139616 A1 SG 139616A1 SG 2007026669 A SG2007026669 A SG 2007026669A SG 139616 A1 SG139616 A1 SG 139616A1
Authority
SG
Singapore
Prior art keywords
semiconductor substrate
pad electrode
conductive terminal
semiconductor device
manufacturing
Prior art date
Application number
SG200702666-9A
Inventor
Takashi Noma
Shigeki Otsuka
Yuichi Morita
Kazuo Okada
Hiroshi Yamada
Katsuhiko Kitagawa
Noboru Okubo
Shinzo Ishibe
Hiroyuki Shinogi
Original Assignee
Sanyo Electric Co
Sanyo Semiconductor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co, Sanyo Semiconductor Co Ltd filed Critical Sanyo Electric Co
Publication of SG139616A1 publication Critical patent/SG139616A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF A packaged semiconductor device is manufactured by a simplified manufacturing process, and is reduced in cost, in thickness and in size. A device component and a pad electrode connected with the device component are formed on a semiconductor substrate. A supporter is bonded to a top surface of the semiconductor substrate through an adhesive layer. Then, there is formed a protection layer that has an opening at a location corresponding to the pad electrode and covers a side surface and a back surface of the semiconductor substrate. A conductive terminal is formed on the pad electrode at the location corresponding to the opening formed in the protection layer. No wiring layer or conductive terminal is formed on the back surface of the semiconductor substrate. A conductive terminal is formed on a periphery of the supporter outside of and next to the side surface of the semiconductor substrate.
SG200702666-9A 2006-08-04 2007-04-11 Semiconductor device and manufacturing method thereof SG139616A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006213483A JP5555400B2 (en) 2006-08-04 2006-08-04 Semiconductor device and manufacturing method thereof

Publications (1)

Publication Number Publication Date
SG139616A1 true SG139616A1 (en) 2008-02-29

Family

ID=39110999

Family Applications (1)

Application Number Title Priority Date Filing Date
SG200702666-9A SG139616A1 (en) 2006-08-04 2007-04-11 Semiconductor device and manufacturing method thereof

Country Status (2)

Country Link
JP (1) JP5555400B2 (en)
SG (1) SG139616A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9721862B2 (en) * 2013-01-03 2017-08-01 STATS ChipPAC Pte. Ltd. Semiconductor device and method of using a standardized carrier to form embedded wafer level chip scale packages
JP6104772B2 (en) * 2013-03-29 2017-03-29 ソニーセミコンダクタソリューションズ株式会社 Laminated structure and manufacturing method thereof

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4499412B2 (en) * 2001-08-24 2010-07-07 ショット アクチエンゲゼルシャフト Method and printed circuit package for forming contacts
JP2003092375A (en) * 2001-09-19 2003-03-28 Matsushita Electric Ind Co Ltd Semiconductor device and method of manufacturing the same, and method of testing the same
JP4334397B2 (en) * 2003-04-24 2009-09-30 三洋電機株式会社 Semiconductor device and manufacturing method thereof
JP2005079304A (en) * 2003-08-29 2005-03-24 Seiko Epson Corp Semiconductor package, method of manufacturing the same and electronic equipment
JP2006191126A (en) * 2006-01-30 2006-07-20 Sanyo Electric Co Ltd Method for manufacturing semiconductor device

Also Published As

Publication number Publication date
JP5555400B2 (en) 2014-07-23
JP2008041892A (en) 2008-02-21

Similar Documents

Publication Publication Date Title
EP1840941A3 (en) Semiconductor device and manufacturing method thereof
TW200741997A (en) Stacked package structure and method for manufacturing the same
TW200802791A (en) Integrated circuit chips
TW200629490A (en) Semiconductor device, method of manufacturing the same, capacitor structure, and method of manufacturing the same
TW200735312A (en) Wafer level package including a device wafer integrated with a passive component
SG152989A1 (en) Semiconductor device and method of making integrated passive devices
WO2008018959A3 (en) Overmolded semiconductor package with a wirebond cage for emi shielding
TW200713529A (en) Semiconductor device and its manufacturing method
TW200644135A (en) Method for fabricating a wafer level package having through wafer vias for external package connectivity and related structure
EP3633723A3 (en) Semiconductor device
TW200721424A (en) Semiconductor device
TW200744173A (en) Semiconductor device and its manufacturing method
SG134334A1 (en) Semiconductor package with passive device integration
TW200739972A (en) Light-emitting device and method for manufacturing the same
TW200725880A (en) Semiconductor piezoresistive sensor and operation method thereof
TW200620502A (en) Semiconductor device, circuit board, electro-optic device, electronic device
SG170099A1 (en) Integrated circuit package system with warp-free chip
SG148987A1 (en) Inter-connecting structure for semiconductor device package and method of the same
ATE551722T1 (en) ENCAPSULATED SEMICONDUCTOR PRODUCT AND METHOD FOR PRODUCING IT
TW200733026A (en) Circuit structure of a display
GB0713791D0 (en) Semiconductor chip package
TW200737376A (en) Chip package and fabricating method thereof
WO2009072493A1 (en) Photosensitive adhesive, semiconductor device and method for manufacturing semiconductor device
WO2009028596A1 (en) Passive element built-in substrate, manufacturing method, and semiconductor device
SG122016A1 (en) Semiconductor chip package and method of manufacture