JPH10270537A - Manufacture of wafer holding board and semiconductor device - Google Patents
Manufacture of wafer holding board and semiconductor deviceInfo
- Publication number
- JPH10270537A JPH10270537A JP7171297A JP7171297A JPH10270537A JP H10270537 A JPH10270537 A JP H10270537A JP 7171297 A JP7171297 A JP 7171297A JP 7171297 A JP7171297 A JP 7171297A JP H10270537 A JPH10270537 A JP H10270537A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- sided
- double
- wafer holding
- tape
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
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- Dicing (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体素子におけ
るチップ分割に関するもの、及びＰＨＳ（Ｐｌａｔｅｄ
Ｈｅａｔ Ｓｉｎｋ：放熱板）形成後のウエハ形状で
の測定を可能にする半導体装置の製造方法に関するもの
である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to chip division in a semiconductor device, and to a PHS (plated).
The present invention relates to a method of manufacturing a semiconductor device which enables measurement in a wafer shape after forming a heat sink.
【０００２】[0002]
【従来の技術】従来、この種の半導体素子の製造方法と
しては、例えば、特開平２−２２８４１号公報の先行技
術として開示されるものがあった。図６はかかる従来の
半導体素子の製造工程断面図である。まず、図６（ａ）
に示すように、ＧａＡｓウエハ４の一方の主面に、ソー
ス電極１、ゲート電極２及びドレイン電極３を形成した
ものを薄層化した後に、図６（ｂ）に示すように、ワッ
クス５及び支持板６を着け、次に、図６（ｃ）に示すよ
うに、ＧａＡｓウエハ４の他方の主面よりソース電極１
に達する貫通孔を形成し、図６（ｄ）に示すように、ダ
イシング域を除いてＰＨＳメッキ７を施し、更に図６
（ｅ）に示すように、ＰＨＳメッキ７をマスクとしてＧ
ａＡｓウエハ４をエッチングし、最後に、図６（ｆ）に
示すようにチップの分割が行われていた。2. Description of the Related Art Heretofore, as a method of manufacturing a semiconductor element of this kind, there has been one disclosed as a prior art in Japanese Patent Application Laid-Open No. 2-22841. FIG. 6 is a sectional view showing a manufacturing process of such a conventional semiconductor device. First, FIG.
As shown in FIG. 6B, after one of the main surfaces of the GaAs wafer 4 on which the source electrode 1, the gate electrode 2 and the drain electrode 3 are formed is thinned, as shown in FIG. The support plate 6 is attached, and then, as shown in FIG.
6D, a PHS plating 7 is applied except for a dicing area as shown in FIG.
As shown in (e), the PHS plating 7 is used as a mask for G
The aAs wafer 4 was etched, and finally, the chips were divided as shown in FIG.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、上記し
た従来の半導体素子の製造方法では、ＰＨＳを形成し、
チップを分離した後、ウエハ形状としての種々の測定を
行なうようにしているため、次のような問題点があっ
た。 （１）バラバラになったチップを、１個１個を測定する
ため、時間がかかり量産に向かない。However, in the above-described conventional method for manufacturing a semiconductor device, a PHS is formed,
After the chips are separated, various measurements of the wafer shape are performed, so that the following problems arise. (1) Since each individual chip is measured individually, it takes time and is not suitable for mass production.
【０００４】（２）チップ毎にバラバラになるため、裏
面プロセスのトラブルを見つけるために、チップに通し
番号をつけなければならない。本発明は、上記問題点を
除去し、製造歩留りが向上するとともに、半導体チップ
の分離を行う前に、的確な測定が可能なウエハ保持用基
板及び半導体装置の製造方法を提供することを目的とす
る。(2) Since chips are scattered for each chip, serial numbers must be given to the chips in order to find a trouble in the back surface process. An object of the present invention is to provide a method for manufacturing a wafer holding substrate and a semiconductor device capable of accurately measuring before removing a problem and improving a manufacturing yield and separating a semiconductor chip. I do.
【０００５】[0005]
【課題を解決するための手段】本発明は、上記目的を達
成するために、 〔１〕ウエハ保持用基板は、ＵＶ光を透過する厚みの石
英基板やサファイア基板に所定の放熱板付き半導体チッ
プのサイズの半分以下の直径の貫通穴を形成してなる。According to the present invention, in order to achieve the above object, [1] a wafer holding substrate is a quartz substrate or a sapphire substrate having a thickness transmitting UV light, and a semiconductor chip with a predetermined heat radiating plate. And a through hole having a diameter of less than half the size of.
【０００６】〔２〕基板にデバイスを形成し、ＵＶ光を
透過する厚みの石英基板やサファイア基板に所定の放熱
板付き半導体チップのサイズの半分以下の直径の貫通穴
を形成してなるウエハ保持用基板を両面ＵＶテープで貼
り合わせる際に、先にＧａＡｓ基板と前記両面ＵＶテー
プを貼り合わせ、その間に生じた気泡を抜いた後に、前
記ウエハ保持用基板を貼り合わせ、該ウエハ保持用基板
と前記両面ＵＶテープに生じた気泡を前記貫通穴から抜
くようにしたものである。[2] A wafer holding device in which a device is formed on a substrate and a through hole having a diameter less than half the size of a predetermined semiconductor chip with a heat sink is formed on a quartz substrate or a sapphire substrate having a thickness transmitting UV light. When the substrate is bonded with a double-sided UV tape, the GaAs substrate and the double-sided UV tape are bonded together, and bubbles generated during the bonding are removed. Then, the wafer holding substrate is bonded. Air bubbles generated in the double-sided UV tape are removed from the through holes.
【０００７】〔３〕放熱板を形成し、半導体チップ分割
をウエハ保持用基板上で終了した後に、このウエハ保持
用基板側からＵＶ照射し、両面ＵＶテープの粘着性を低
下させた後、前記放熱板側から別個のウエハ保持用基板
を両面ＵＶテープで貼り付け、半導体チップを前記別個
のウエハ保持用基板に貼り付けることにより、ＧａＡｓ
基板の主表面を表に向けて、ウエハ形状で順序正しく配
列するようにしたものである。[3] After forming a heat sink and dividing the semiconductor chips on the wafer holding substrate, UV irradiation is performed from the wafer holding substrate side to reduce the adhesiveness of the double-sided UV tape. By attaching a separate wafer holding substrate from the heat sink side with a double-sided UV tape and attaching the semiconductor chip to the separate wafer holding substrate, GaAs
With the main surface of the substrate facing the front, they are arranged in order in a wafer shape.
【０００８】[0008]
【発明の実施の形態】以下、本発明の実施の形態につい
て図面を参照しながら詳細に説明する。図１は本発明に
用いるウエハ保持用の石英基板（又はサファイア基板）
を示す図であり、図１（ａ）はその平面図、図１（ｂ）
はその側面図である。この実施例において、ＧａＡｓ基
板として３インチφＧａＡｓウエハ（直径約７６．３ｍ
ｍ）を用いる場合、石英基板（又はサファイア基板）１
１はＧａＡｓ基板より少し大きい直径Ｌ1 （約７８ｍｍ
φ）のものを用いる。その直径は、ＧａＡｓ基板と同程
度、７６．３ｍｍφ以上の大きさがあれば良い。Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a quartz substrate (or sapphire substrate) for holding a wafer used in the present invention.
FIG. 1A is a plan view thereof, and FIG.
Is a side view thereof. In this embodiment, a 3 inch φ GaAs wafer (about 76.3 m in diameter) is used as a GaAs substrate.
m), a quartz substrate (or sapphire substrate) 1
Reference numeral 1 denotes a diameter L 1 (about 78 mm) slightly larger than the GaAs substrate.
φ) is used. The diameter may be the same as that of the GaAs substrate, and may be 76.3 mmφ or more.
【０００９】また、石英基板の厚みｔ1 は、図１（ｂ）
で示したものは、１ｍｍであるが、０．０５ｍｍ〜２ｍ
ｍの範囲内であれば良い（厚みｔ1 が厚すぎると、石英
基板を持つことが困難となる。また、薄すぎると、石英
基板にＧａＡｓ基板を貼り付けた後に曲がることがあ
る）。さらに、石英基板（又はサファイア基板）１１に
は直径１〜２ｍｍφの貫通穴１２を形成する。この貫通
穴１２は小さければ小さい程良い。Further, the thickness t 1 of the quartz substrate is shown in FIG.
Is 1 mm, but 0.05 mm to 2 m
m may be within the range of (the thickness t 1 is too thick, it is difficult to have a quartz substrate. Further, when too thin, it may bend after laminating the GaAs substrate on a quartz substrate). Further, a through hole 12 having a diameter of 1 to 2 mmφ is formed in the quartz substrate (or sapphire substrate) 11. The smaller this through hole 12 is, the better.
【００１０】例えば、製造するチップサイズが、１ｍｍ
口の大きさならば、貫通穴１２は直径０．５ｍｍφ以下
のサイズが良い。これはチップサイズよりも、貫通穴１
２のサイズが大きいと、チッププロセス中にチップが貫
通穴の中に入る問題が生じる。さらに、チップサイズよ
りも少し小さい程度の場合は、チップが割れたり、欠け
たりする問題点が生じるためである。For example, when the chip size to be manufactured is 1 mm
As long as the size of the mouth is large, the through hole 12 preferably has a diameter of 0.5 mmφ or less. This is more than the chip size,
If the size of 2 is large, there is a problem that the chip enters the through hole during the chip process. Further, when the size is slightly smaller than the chip size, there is a problem that the chip is broken or chipped.
【００１１】以上より、理想的な貫通穴１２のサイズ
は、製造するチップサイズの半分以下の直径である。ま
た、貫通穴１２の個数は図面では約５０個程度である
が、数は多ければ多い程良い。貫通穴１２は、ＧａＡｓ
基板と本発明の石英基板１１を両面ＵＶテープで貼り合
わせる時に、両面ＵＶテープと石英基板１１とで生じる
気泡を容易に抜くために必要なものである。As described above, the ideal size of the through hole 12 is less than half the diameter of the chip to be manufactured. The number of the through holes 12 is about 50 in the drawing, but the larger the number, the better. The through hole 12 is made of GaAs
When the substrate and the quartz substrate 11 of the present invention are bonded to each other with the double-sided UV tape, it is necessary to easily remove bubbles generated between the double-sided UV tape and the quartz substrate 11.
【００１２】次に、本発明の実施例を示す半導体装置の
製造方法について、図２〜図５を参照しながら説明す
る。 （１）まず、図２（ａ）に示すように、ＧａＡｓ基板２
１の表面にゲート電極２３、オーミック電極２２、パッ
シベーション膜（ＳｉＮ膜やＳｉＯ膜など）２４などを
形成する。なお、ここでは、ＧａＡｓ基板２１を用いた
が、Ｓｉ基板やＧａＡｓ基板上にＡｌＧａＡｓ等をＭＢ
Ｅ成長させた基板でも良い。Next, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. (1) First, as shown in FIG.
A gate electrode 23, an ohmic electrode 22, a passivation film (such as a SiN film or a SiO film) 24, etc. are formed on the surface of the substrate 1. Although the GaAs substrate 21 is used here, AlGaAs or the like is formed on a Si substrate or a GaAs substrate by MB.
A substrate grown by E may be used.
【００１３】（２）次に、図２（ｂ）に示すように、Ｇ
ａＡｓ基板２１の表面に両面ＵＶテープ２５を貼る。こ
の時、両面ＵＶテープ２５の粘着剤の保護膜２６を剥離
しないで貼り付け、ＧａＡｓ基板２１と両面ＵＶテープ
２５の間の気泡を保護膜２６からゆっくり押さえつける
ことにより抜く。 （３）次いで、図２（ｃ）に示すように、保護膜２６を
剥離した後、石英基板１１を貼り付ける。この時、石英
基板１１と両面ＵＶテープ２５との間の気泡は、石英基
板１１に形成されている貫通穴１２を通して抜ける。(2) Next, as shown in FIG.
A double-sided UV tape 25 is stuck on the surface of the aAs substrate 21. At this time, the adhesive protective film 26 of the double-sided UV tape 25 is adhered without being peeled off, and bubbles between the GaAs substrate 21 and the double-sided UV tape 25 are slowly pressed down from the protective film 26 to be removed. (3) Next, as shown in FIG. 2C, after the protective film 26 is peeled off, the quartz substrate 11 is attached. At this time, bubbles between the quartz substrate 11 and the double-sided UV tape 25 escape through the through holes 12 formed in the quartz substrate 11.
【００１４】（４）次いで、図２（ｄ）に示すように、
ＧａＡｓ基板２１の裏面を研磨し、５０μｍの厚さのＧ
ａＡｓ基板２１′とする。ここで、ＧａＡｓ基板２１′
の厚みを５０μｍとしたが、厚みは２０μｍでも、１０
０μｍでも別段問題はない。 （５）次に、図２（ｅ）に示すように、ＧａＡｓ基板２
１′にレジストを塗布し、両面アライナ等で露光後、現
像し、バイアホールのレジストパターン２７を形成す
る。(4) Next, as shown in FIG.
The back surface of the GaAs substrate 21 is polished, and a 50 μm thick G
aAs substrate 21 '. Here, the GaAs substrate 21 '
Is 50 μm, but even if the thickness is 20 μm,
There is no particular problem at 0 μm. (5) Next, as shown in FIG.
1 'is coated with a resist, exposed with a double-sided aligner or the like, and developed to form a resist pattern 27 of via holes.
【００１５】（６）次に、図３（ａ）に示すように、Ｇ
ａＡｓ基板２１′にウェットエッチングまたはＲＩＥな
どのドライエッチングを用い、バイアホールを形成した
ＧａＡｓ基板２１″上のレジストパターン２７〔図２
（ｅ）参照〕を除去する。 （７）次に、図３（ｂ）に示すように、ＧａＡｓ基板２
１″の全面に蒸着または、スパッタで、Ｔｉ／Ａｕ，Ｔ
ｉ／ＴｉＮ／Ａｕなどの電解めっき用のカレントフィル
ム２８を形成する。(6) Next, as shown in FIG.
A resist pattern 27 on a GaAs substrate 21 ″ having via holes formed thereon by using wet etching or dry etching such as RIE on the aAs substrate 21 ′ [FIG.
(See (e)). (7) Next, as shown in FIG.
Ti / Au, T by evaporation or sputtering on the entire surface of 1 "
A current film 28 for electrolytic plating such as i / TiN / Au is formed.
【００１６】（８）次に、図３（ｃ）に示すように、レ
ジストをカレントフィルム２８上に塗布し、両面アライ
ナ等で露光後現像し、ＰＨＳのレジストパターン２９を
形成する。 （９）次に、図３（ｄ）に示すように、選択電解めっき
法により、ＰＨＳとしてのＡｕ膜３０を形成する。ここ
では、Ａｕ膜であるが、Ｃｕ膜や、Ａｕ−Ｐｄ合金膜で
も良い。(8) Next, as shown in FIG. 3C, a resist is applied on the current film 28, exposed and developed by a double-sided aligner or the like to form a PHS resist pattern 29. (9) Next, as shown in FIG. 3D, an Au film 30 as PHS is formed by a selective electrolytic plating method. Here, the Au film is used, but a Cu film or an Au-Pd alloy film may be used.
【００１７】（１０）次に、図４（ａ）に示すように、
レジストパターン２９を剥離する。 （１１）更に、図４（ｂ）に示すように、ウェットエッ
チングや、イオンミリングなどのドライエッチングで、
Ａｕ膜３０が形成されていない余分な部分のカレントフ
ィルム２８を除去する。 （１２）更に、図４（ｃ）に示すように、余分なカレン
トフィルムの下のＧａＡｓ基板２１″もウェットエッチ
ングまたはＲＩＥ、ＥＣＲなどのドライエッチングで除
去する。この状態でＰＨＳ付きのチップが形成されたこ
とになる。ただし、この状態では、ＰＨＳが表面を向い
ているため、ＰＨＳ付きチップの測定は不可能である。(10) Next, as shown in FIG.
The resist pattern 29 is peeled off. (11) Further, as shown in FIG. 4B, wet etching or dry etching such as ion milling is performed.
An excess portion of the current film 28 where the Au film 30 is not formed is removed. (12) Further, as shown in FIG. 4C, the excess GaAs substrate 21 ″ under the current film is also removed by wet etching or dry etching such as RIE or ECR. In this state, a chip with a PHS is formed. However, in this state, it is impossible to measure the chip with the PHS because the PHS faces the surface.
【００１８】（１３）次に、図４（ｄ）に示すように、
石英基板１１側からＵＶ光３１によるＵＶ照射を行い、
両面ＵＶテープの粘着性を低下させる。つまり、粘着性
が低下した両面ＵＶテープ２５′とする。 （１４）更に、図５（ａ）に示すように、新しいもう１
枚の両面ＵＶテープ２５″を貼り付けた石英基板１１′
を用意し、ＰＨＳ側に貼り付ける。(13) Next, as shown in FIG.
UV irradiation with UV light 31 is performed from the quartz substrate 11 side,
Decreases the adhesiveness of double-sided UV tape. That is, it is a double-sided UV tape 25 'having reduced adhesion. (14) Further, as shown in FIG.
Quartz substrate 11 'with two double-sided UV tapes 25 "attached
And paste it on the PHS side.
【００１９】（１５）その後、図５（ｂ）に示すよう
に、パッシベーション膜２４側の石英基板１１を剥離す
ることにより、パッシベーション膜２４が表面となった
形状が得られる。この状態は、ほぼ最初のＧａＡｓ基板
と同一の並び及び位置のＰＨＳ付きチップが得られる。
この状態で、測定等を行い、チップの選別等が可能であ
る。(15) Then, as shown in FIG. 5B, the quartz substrate 11 on the side of the passivation film 24 is peeled off to obtain a shape having the passivation film 24 as a surface. In this state, a PHS chip having substantially the same arrangement and position as the first GaAs substrate can be obtained.
In this state, measurement and the like can be performed to select chips and the like.
【００２０】（１６）更に、図５（ｃ）に示すように、
このチップを石英基板１１′から取り出す方法として、
石英基板１１′側からＵＶ照射３１を行い両面ＵＶテー
プ２５″の粘着性を低下させた後に取り出せば良い。こ
のように、この実施例で、図２（ｃ）で示したように、
ＧａＡｓ基板２１と石英基板１１を両面ＵＶテープ２５
で貼り合わせる場合に、石英基板１１と両面ＵＶテープ
２５の間で生じた気泡を、石英基板１１に形成された貫
通穴１２〔図１（ａ）参照〕から容易に抜くことができ
る。ただし、ＧａＡｓ基板２１と両面ＵＶテープ２５は
先に貼り付けて、ＧａＡｓ基板と両面ＵＶテープの間の
気泡は抜いておく。(16) Further, as shown in FIG.
As a method of taking out this chip from the quartz substrate 11 ',
The UV irradiation 31 may be performed from the side of the quartz substrate 11 ′ to reduce the adhesiveness of the double-sided UV tape 25 ″ and then removed. In this embodiment, as shown in FIG.
GaAs substrate 21 and quartz substrate 11 are double-sided UV tape 25
In the case of bonding together, air bubbles generated between the quartz substrate 11 and the double-sided UV tape 25 can be easily removed from the through holes 12 (see FIG. 1A) formed in the quartz substrate 11. However, the GaAs substrate 21 and the double-sided UV tape 25 are attached first, and air bubbles between the GaAs substrate and the double-sided UV tape are removed.
【００２１】また、両面ＵＶテープでＧａＡｓ基板と石
英基板を貼り合わせてあるため、ＰＨＳを形成後に容易
にＧａＡｓ基板の表面を向けて、元のＧａＡｓ基板と同
一形状に貼り直しが可能になるという効果が期待でき
る。なお、本発明は上記実施例に限定されるものではな
く、本発明の趣旨に基づいて種々の変形が可能であり、
これらを本発明の範囲から排除するものではない。Further, since the GaAs substrate and the quartz substrate are bonded to each other with a double-sided UV tape, it is possible to easily turn the surface of the GaAs substrate after forming the PHS and re-attach the same shape as the original GaAs substrate. The effect can be expected. It should be noted that the present invention is not limited to the above embodiment, and various modifications are possible based on the gist of the present invention.
They are not excluded from the scope of the present invention.
【００２２】[0022]
【発明の効果】以上、詳細に説明したように、本発明に
よれば、以下のような効果を奏することができる。 （１）請求項１記載の発明によれば、半導体装置の製造
を迅速、かつ的確に行うことができるウエハ保持用基板
を得ることができる。As described above, according to the present invention, the following effects can be obtained. (1) According to the first aspect of the present invention, it is possible to obtain a wafer holding substrate capable of quickly and accurately manufacturing a semiconductor device.
【００２３】（２）請求項２記載の発明によれば、デバ
イスが形成された基板とウエハ保持基板を両面ＵＶテー
プで貼り合わせる場合に、ウエハ保持用基板と両面ＵＶ
テープの間で生じた気泡を、ウエハ保持基板に形成され
た貫通穴から容易に抜くことができ、半導体装置の製造
を容易に、かつ歩留り良く行うことができる。 （３）請求項３記載の発明によれば、半導体チップの分
離を行う前に、ウエハ形状で順序正しく配列された半導
体チップを的確に測定することができる。(2) According to the second aspect of the invention, when the substrate on which the devices are formed and the wafer holding substrate are bonded together with a double-sided UV tape, the wafer holding substrate and the double-sided UV
Bubbles generated between the tapes can be easily removed from the through holes formed in the wafer holding substrate, and the semiconductor device can be manufactured easily and with good yield. (3) According to the third aspect of the invention, it is possible to accurately measure semiconductor chips arranged in order in a wafer shape before separating the semiconductor chips.
【図１】本発明に用いるウエハ保持用の石英基板（又は
サファイア基板）を示す図である。FIG. 1 is a view showing a quartz substrate (or sapphire substrate) for holding a wafer used in the present invention.
【図２】本発明の実施例を示す半導体装置の製造工程断
面図（その１）である。FIG. 2 is a cross-sectional view (No. 1) of the manufacturing process of the semiconductor device according to the embodiment of the present invention.
【図３】本発明の実施例を示す半導体装置の製造工程断
面図（その２）である。FIG. 3 is a cross-sectional view (part 2) of a process for manufacturing a semiconductor device according to an embodiment of the present invention.
【図４】本発明の実施例を示す半導体装置の製造工程断
面図（その３）である。FIG. 4 is a sectional view (part 3) of a semiconductor device showing a manufacturing step according to an embodiment of the present invention;
【図５】本発明の実施例を示す半導体装置の製造工程断
面図（その４）である。FIG. 5 is a sectional view (part 4) of a process for manufacturing a semiconductor device according to an embodiment of the present invention.
【図６】従来の半導体装置の製造工程断面図である。FIG. 6 is a sectional view showing a manufacturing process of a conventional semiconductor device.
１１，１１′ 石英基板（又はサファイア基板） １２ 貫通穴 ２１，２１′，２１″ ＧａＡｓ基板 ２２ オーミック電極 ２３ ゲート電極 ２４ パッシベーション膜 ２５，２５″ 両面ＵＶテープ ２５′ 粘着性が低下した両面ＵＶテープ ２６ 保護膜 ２７，２９ レジストパターン ２８ カレントフィルム ３０ Ａｕ膜（放熱板） ３１ ＵＶ光 11, 11 'Quartz substrate (or sapphire substrate) 12 Through hole 21, 21', 21 "GaAs substrate 22 Ohmic electrode 23 Gate electrode 24 Passivation film 25, 25" Double-sided UV tape 25 'Double-sided UV tape with reduced adhesion 26 Protective film 27, 29 Resist pattern 28 Current film 30 Au film (heat sink) 31 UV light
Claims (3)
ァイア基板に所定の放熱板付き半導体チップのサイズの
半分以下の直径の貫通穴を形成してなるウエハ保持用基
板。1. A wafer holding substrate comprising a quartz substrate or a sapphire substrate having a thickness transmitting UV light and having a through hole having a diameter equal to or less than half the size of a predetermined semiconductor chip with a heat sink.
する厚みの石英基板やサファイア基板に所定の放熱板付
き半導体チップのサイズの半分以下の直径の貫通穴を形
成してなるウエハ保持用基板を両面ＵＶテープで貼り合
わせる際に、先にＧａＡｓ基板と前記両面ＵＶテープを
貼り合わせ、その間に生じた気泡を抜いた後に、前記ウ
エハ保持用基板を貼り合わせ、該ウエハ保持用基板と前
記両面ＵＶテープに生じた気泡を前記貫通穴から抜くこ
とを特徴とする半導体装置の製造方法。2. A wafer holding device comprising: a device formed on a substrate; and a through hole having a diameter equal to or less than half the size of a predetermined semiconductor chip with a heat sink formed on a quartz substrate or a sapphire substrate having a thickness transmitting UV light. When the substrates are bonded with a double-sided UV tape, the GaAs substrate and the double-sided UV tape are bonded together, and bubbles generated during the bonding are removed, and then the wafer holding substrate is bonded. A method for manufacturing a semiconductor device, comprising: removing air bubbles generated in a double-sided UV tape from the through hole.
エハ保持用基板上で終了した後に、該ウエハ保持用基板
側からＵＶ照射し、両面ＵＶテープの粘着性を低下させ
た後、前記放熱板側から別個のウエハ保持用基板を両面
ＵＶテープで貼り付け、半導体チップを前記別個のウエ
ハ保持用基板に貼り付けることにより、ＧａＡｓ基板の
主表面を表に向けて、ウエハ形状で順序正しく配列する
ことを特徴とする半導体装置の製造方法。3. A heat radiation plate is formed, and after dividing the semiconductor chip on the wafer holding substrate, UV irradiation is performed from the wafer holding substrate side to reduce the adhesiveness of the double-sided UV tape. By attaching a separate wafer holding substrate from the plate side with a double-sided UV tape and attaching the semiconductor chip to the separate wafer holding substrate, the main surface of the GaAs substrate is faced up and arranged in order in a wafer shape. A method of manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7171297A JPH10270537A (en) | 1997-03-25 | 1997-03-25 | Manufacture of wafer holding board and semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7171297A JPH10270537A (en) | 1997-03-25 | 1997-03-25 | Manufacture of wafer holding board and semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10270537A true JPH10270537A (en) | 1998-10-09 |
Family
ID=13468431
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7171297A Withdrawn JPH10270537A (en) | 1997-03-25 | 1997-03-25 | Manufacture of wafer holding board and semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH10270537A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002184845A (en) * | 2000-12-15 | 2002-06-28 | Kyocera Corp | Wafer support substrate |
| JP2007242812A (en) * | 2006-03-07 | 2007-09-20 | Sanyo Electric Co Ltd | Method of manufacturing semiconductor device and supporting tape |
| JP2008135471A (en) * | 2006-11-27 | 2008-06-12 | Kyocera Corp | Method for processing wafer, and process for manufacturing semiconductor chip using the method |
-
1997
- 1997-03-25 JP JP7171297A patent/JPH10270537A/en not_active Withdrawn
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002184845A (en) * | 2000-12-15 | 2002-06-28 | Kyocera Corp | Wafer support substrate |
| JP2007242812A (en) * | 2006-03-07 | 2007-09-20 | Sanyo Electric Co Ltd | Method of manufacturing semiconductor device and supporting tape |
| JP4619308B2 (en) * | 2006-03-07 | 2011-01-26 | 三洋電機株式会社 | Semiconductor device manufacturing method and supporting tape |
| JP2008135471A (en) * | 2006-11-27 | 2008-06-12 | Kyocera Corp | Method for processing wafer, and process for manufacturing semiconductor chip using the method |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20040601 |