JP2008130705A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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JP2008130705A
JP2008130705A JP2006312389A JP2006312389A JP2008130705A JP 2008130705 A JP2008130705 A JP 2008130705A JP 2006312389 A JP2006312389 A JP 2006312389A JP 2006312389 A JP2006312389 A JP 2006312389A JP 2008130705 A JP2008130705 A JP 2008130705A
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semiconductor substrate
adhesive layer
substrate
effective element
semiconductor
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Satoru Wakiyama
悟 脇山
Yoshihiro Makita
吉弘 蒔田
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Sony Corp
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Sony Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem that, after a carrier substrate is bonded on a semiconductor substrate with an adhesive layer disposed therebetween and then subjected to predetermined treatment, a residue of an adhesive remains on the semiconductor substrate when the carrier substrate is peeled from the semiconductor substrate. <P>SOLUTION: A method of manufacturing a semiconductor device includes a first step of forming adhesive layers (6A, 6B) formed of a photosensitive material on the first surface of a semiconductor substrate 1 including effective element regions 2 for forming an element circuit and ineffective regions 3 surrounding the effective element regions, a second step of exposing the adhesive layers with light and developing the adhesive layers with the adhesive layers removed from the effective element regions 2 and with the adhesive layer 6A remaining on the ineffective regions 3, a third step of bonding the carrier substrate on the first surface of the semiconductor substrate 1 with the adhesive layer 6A disposed therebetween, a fourth step of subjecting the semiconductor substrate 1 to predetermined treatment with the carrier substrate bonded thereon, and a fifth step of cutting the effective element regions 2 and the ineffective regions 3 into the individual semiconductor substrates 1. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、半導体基板に支持基板を貼り付けて所定の処理を行なう際に適用される半導体装置の製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor device applied when a support substrate is attached to a semiconductor substrate and a predetermined process is performed.

LSI(Large Scale Integration:大規模集積回路)チップに代表される半導体チップへの貫通電極を用いたチップオンチップ構造の3次元積層タイプのSIP(System in Package)を製造する場合は、半導体チップへの貫通電極や裏面配線などの形成を効率良く容易に行なうために、半導体基板(ウエハ)を薄肉化する必要がある。ただし、半導体基板を薄肉化すると、反りの発生や割れの危険性が高まり、取り扱い上のハンドリングも困難になる。   When manufacturing a 3D stacked type SIP (System in Package) with a chip-on-chip structure using a through electrode to a semiconductor chip represented by an LSI (Large Scale Integration) chip, the semiconductor chip In order to efficiently and easily form through electrodes and backside wiring, it is necessary to reduce the thickness of the semiconductor substrate (wafer). However, if the thickness of the semiconductor substrate is reduced, the risk of warping and cracking increases, and handling becomes difficult.

このため従来においては、例えば図10に示すように、バンプ50が形成された半導体基板51の主面(バンプ形成面)に接着剤層52を介して補強用の支持基板53を貼り付け、この状態で半導体基板51の裏面をグラインダー54で研削して薄肉化している。また、支持基板53を貼り付けた状態で半導体基板51に所定の処理を施し、その後、半導体基板51から接着剤層52ごと支持基板53を剥離してから、図示しないダイシング装置で半導体基板51を個片化している。   For this reason, conventionally, for example, as shown in FIG. 10, a reinforcing support substrate 53 is attached to the main surface (bump forming surface) of the semiconductor substrate 51 on which the bumps 50 are formed via an adhesive layer 52. In this state, the back surface of the semiconductor substrate 51 is ground by a grinder 54 to reduce the thickness. In addition, the semiconductor substrate 51 is subjected to a predetermined process with the support substrate 53 attached, and then the support substrate 53 is peeled off from the semiconductor substrate 51 together with the adhesive layer 52, and then the semiconductor substrate 51 is removed by a dicing apparatus (not shown). It is singulated.

このような半導体装置の製造技術に関連して、例えば特許文献1には、支持基板として半導体基板と実質的に同一の熱膨張率を有するアルミナ、窒化アルミニウム、窒化硼素、炭化珪素などの材料を用い、また支持基板と半導体基板とを接着する接着剤としてポリアミドなどの熱可塑性樹脂を用い、この接着剤の適用法として、10〜100μmの厚さのフィルムとする方法、あるいは接着剤樹脂溶液をスピンコートし、乾燥させて20μm以下のフィルムとする方法が提案されている。   In relation to such a semiconductor device manufacturing technology, for example, Patent Document 1 discloses a material such as alumina, aluminum nitride, boron nitride, or silicon carbide having a thermal expansion coefficient substantially the same as that of a semiconductor substrate as a support substrate. And a thermoplastic resin such as polyamide is used as an adhesive for bonding the support substrate and the semiconductor substrate, and as a method of applying this adhesive, a method of forming a film having a thickness of 10 to 100 μm, or an adhesive resin solution is used. A method has been proposed in which a film of 20 μm or less is formed by spin coating and drying.

また、特許文献2には、刺激により少なくとも片方の表面から気体を発生する粘着シートから形成されている支持テープを介して半導体基板を支持基板に固定する工程と、半導体基板を支持基板に固定した状態で加工する工程と、支持テープに刺激を与える工程と、半導体基板から支持テープを剥離する工程とを有するICチップの製造方法に関する技術が開示されている。   In Patent Document 2, a step of fixing a semiconductor substrate to a support substrate via a support tape formed from an adhesive sheet that generates gas from at least one surface by stimulation, and fixing the semiconductor substrate to the support substrate A technique relating to a method of manufacturing an IC chip is disclosed which includes a step of processing in a state, a step of stimulating the support tape, and a step of peeling the support tape from the semiconductor substrate.

特開2001−77304号公報JP 2001-77304 A 特開2004−186282号公報JP 2004-186282 A

しかしながら、特許文献1に記載された技術では、半導体基板と支持基板をポリアミドなどの熱可塑性樹脂を用いて接着しているため、半導体基板を薄肉化した後の加工工程で高温の雰囲気に晒されると、接着剤が溶解して半導体基板と支持基板が剥離する恐れがある。また、バンプが形成された半導体基板の主面に接着剤を塗布するため、支持基板と半導体基板を剥離する際に、例えば前工程での加熱による接着剤の組成変化により、半導体基板上に接着剤の残渣が残って接合不良が発生する恐れがある。   However, in the technique described in Patent Document 1, since the semiconductor substrate and the support substrate are bonded using a thermoplastic resin such as polyamide, the semiconductor substrate is exposed to a high-temperature atmosphere in a processing step after thinning the semiconductor substrate. Then, the adhesive may be dissolved and the semiconductor substrate and the support substrate may be separated. In addition, since the adhesive is applied to the main surface of the semiconductor substrate on which the bumps are formed, when the support substrate and the semiconductor substrate are peeled off, the adhesive is bonded onto the semiconductor substrate by, for example, the composition change of the adhesive by heating in the previous process. The residue of the agent may remain, resulting in poor bonding.

特に、チップを高密度に実装する積層タイプのSIPを製造する場合は、支持基板を貼り付けた状態の半導体基板に貫通電極や裏面配線を形成するために、300℃程度のプロセス温度で半導体基板を加工する必要があるため、接着剤の残渣が発生しやすいものとなる。また、現状では支持基板貼り付け用(仮固定用)の接着剤に求められる耐熱性、耐薬品性、剥離性などの特性を同時に満足するものが存在しない。   In particular, when manufacturing a stacked type SIP in which chips are mounted at a high density, a semiconductor substrate is formed at a process temperature of about 300 ° C. in order to form a through electrode and a backside wiring on a semiconductor substrate with a support substrate attached thereto. Since it is necessary to process, adhesive residue is likely to be generated. In addition, at present, there is no material that simultaneously satisfies the characteristics such as heat resistance, chemical resistance, and peelability required for an adhesive for attaching a support substrate (for temporary fixing).

本発明に係る半導体装置の製造方法は、素子回路が形成される有効素子領域とこの有効素子領域を囲む無効領域とを含む半導体基板の第1面に、感光性材料からなる接着剤層を形成する第1工程と、有効素子領域から接着剤層を除去しかつ無効領域に接着剤層を残す状態で接着剤層を露光・現像する第2工程と、半導体基板の第1面に接着剤層を介して支持基板を貼り付ける第3工程と、支持基板を貼り付けた状態で半導体基板に所定の処理を施す第4工程と、有効素子領域と無効領域とを切り離して半導体基板を個片化する第5工程とを含むものである。   In the method for manufacturing a semiconductor device according to the present invention, an adhesive layer made of a photosensitive material is formed on a first surface of a semiconductor substrate including an effective element region in which an element circuit is formed and an ineffective region surrounding the effective element region. A first step of removing the adhesive layer from the effective element region and a second step of exposing and developing the adhesive layer with the adhesive layer left in the ineffective region, and an adhesive layer on the first surface of the semiconductor substrate The third step of attaching the support substrate via the step, the fourth step of applying a predetermined process to the semiconductor substrate with the support substrate attached, and separating the semiconductor substrate by separating the effective element region and the invalid region Including a fifth step.

本発明に係る半導体装置の製造方法においては、半導体基板の第1面に感光性材料を用いて形成した接着剤層を露光・現像することにより、予め有効素子領域から接着剤層を除去しておき、支持基板の貼り付けは、無効領域に残した接着剤層を用いて行なうため、半導体基板に支持基板を貼り付けたまま、半導体基板を個片化することが可能となる。   In the method for manufacturing a semiconductor device according to the present invention, the adhesive layer formed using a photosensitive material on the first surface of the semiconductor substrate is exposed and developed to remove the adhesive layer from the effective element region in advance. In addition, since the support substrate is attached using the adhesive layer left in the ineffective region, the semiconductor substrate can be separated into pieces while the support substrate is attached to the semiconductor substrate.

本発明に係る半導体装置の製造方法によれば、半導体基板から支持基板を剥離する必要がなくなるため、接着剤の残渣による不具合を解消することができる。また、既存の支持基板を用いた手法では、半導体基板に接着剤で支持基板を貼り付けて、貫通電極や裏面配線、バンプなどを半導体基板に形成する場合に、プロセス温度が300℃程度の高温となると、接着剤の熱変性により半導体基板から支持基板を剥離できなくなる。結果、半導体基板を半導体装置として使用することが不可能になるが、本発明の手法を用いれば、半導体基板から支持基板を剥離する必要がないため、プロセス温度が300℃程度の高温となる貫通電極や裏面配線、バンプなどを半導体基板へ形成することが可能になる。   According to the method for manufacturing a semiconductor device according to the present invention, it is not necessary to peel the support substrate from the semiconductor substrate, so that it is possible to eliminate problems caused by adhesive residues. Further, in the method using the existing support substrate, when the support substrate is attached to the semiconductor substrate with an adhesive and the through electrode, the back surface wiring, the bump, and the like are formed on the semiconductor substrate, the process temperature is as high as about 300 ° C. Then, the support substrate cannot be peeled from the semiconductor substrate due to the thermal denaturation of the adhesive. As a result, it becomes impossible to use the semiconductor substrate as a semiconductor device. However, if the method of the present invention is used, there is no need to peel the support substrate from the semiconductor substrate, so that the process temperature becomes as high as about 300 ° C. Electrodes, backside wiring, bumps, and the like can be formed on the semiconductor substrate.

以下、本発明の具体的な実施の形態について図面を参照しつつ詳細に説明する。   Hereinafter, specific embodiments of the present invention will be described in detail with reference to the drawings.

[第1実施形態]
図1〜図6は本発明の第1実施形態に係る半導体装置の製造方法を示す工程図である。まず、LSIなどの素子回路や配線、突起電極となるバンプ(例えば、はんだバンプ)などを第1面(主面)に形成してなる半導体基板を用意する。半導体基板としては、例えばシリコンウエハを用いることができる。バンプは接続端子として半導体基板の第1面に形成されるものである。
[First Embodiment]
1 to 6 are process diagrams showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention. First, a semiconductor substrate is prepared in which element circuits such as LSI, wiring, bumps (for example, solder bumps) to be protruding electrodes are formed on the first surface (main surface). For example, a silicon wafer can be used as the semiconductor substrate. The bump is formed on the first surface of the semiconductor substrate as a connection terminal.

半導体基板1は、図1(A),(B)に示すように、最終的に切り出されるチップ(半導体素子)として切り出される複数の有効素子領域2を有している。有効素子領域2は、LSIなどの素子回路や配線、電極部などが形成される領域であって、チップのサイズに応じて格子状に区画されている。チップは、正方形又は長方形の平面形状で半導体基板から切り出される。このため、有効素子領域2は、チップの形状に合わせて正方形又は長方形に区画されている。   As shown in FIGS. 1A and 1B, the semiconductor substrate 1 has a plurality of effective element regions 2 cut out as chips (semiconductor elements) to be cut out finally. The effective element area 2 is an area in which element circuits such as LSI, wiring, electrode portions, and the like are formed, and is partitioned in a lattice shape according to the chip size. The chip is cut out from the semiconductor substrate in a square or rectangular planar shape. Therefore, the effective element region 2 is divided into a square or a rectangle according to the shape of the chip.

また、半導体基板1は、有効素子領域2の他に、無効領域3を有している。無効領域3は、素子回路などが形成されない領域であって、有効素子領域2を囲むように位置している。無効領域3は、後工程でチップを切り出すときに切除される領域である。また、有効素子領域2には複数のバンプ4が形成されているが、無効領域3にはバンプ4が形成されていない。有効素子領域2におけるバンプ4の個数や配置などは任意に変更可能である。例えば、有効素子領域2の外周部だけにバンプ4を配置してもよいし、有効素子領域2全体にバンプ4を配置してもよい。無効領域3は、半導体基板1の全領域の中で有効素子領域2を除く領域である。このため、無効領域3は、各々の有効素子領域2を取り囲む四角い枠状の部分だけでなく、半導体基板1の周縁部にも存在する。また、有効素子領域2を取り囲む部分(ストリートと呼ばれる部分)では、無効領域3が縦横に所定幅のライン状に区画されている。   The semiconductor substrate 1 has an ineffective region 3 in addition to the effective element region 2. The invalid region 3 is a region where an element circuit or the like is not formed, and is positioned so as to surround the effective element region 2. The invalid area 3 is an area that is excised when cutting a chip in a subsequent process. A plurality of bumps 4 are formed in the effective element region 2, but no bumps 4 are formed in the invalid region 3. The number and arrangement of the bumps 4 in the effective element region 2 can be arbitrarily changed. For example, the bumps 4 may be disposed only on the outer periphery of the effective element region 2, or the bumps 4 may be disposed on the entire effective element region 2. The invalid region 3 is a region excluding the effective element region 2 in the entire region of the semiconductor substrate 1. For this reason, the ineffective region 3 exists not only in the rectangular frame-shaped portion surrounding each effective element region 2 but also in the peripheral portion of the semiconductor substrate 1. In addition, in a portion surrounding the effective element region 2 (portion called a street), the ineffective region 3 is partitioned in a line shape having a predetermined width vertically and horizontally.

このようなバンプ付きの半導体基板1を用意したら、例えば図2(A)に示すように、スピンコータなどの塗布装置の基板保持部(例えば、スピンチャックなど)に半導体基板1を水平にセットして、モータ等の駆動により半導体基板1を回転させるとともに、回転中の半導体基板1の上方からノズル5により感光性のレジスト材料を滴下することにより、図2(B),(C)に示すように、半導体基板1の第1面にバンプ4を覆う状態で接着剤層6を形成する。   When the semiconductor substrate 1 with such bumps is prepared, as shown in FIG. 2A, for example, the semiconductor substrate 1 is set horizontally on a substrate holding part (for example, a spin chuck) of a coating apparatus such as a spin coater. As shown in FIGS. 2B and 2C, the semiconductor substrate 1 is rotated by driving a motor or the like, and a photosensitive resist material is dropped from above the rotating semiconductor substrate 1 by the nozzle 5. The adhesive layer 6 is formed on the first surface of the semiconductor substrate 1 so as to cover the bumps 4.

この場合、半導体基板1の第1面の全域を接着剤層6で覆うように、スピンコート法により一様な厚み寸法で接着剤層6を形成するとよい。また、半導体基板1に形成してある全てのバンプ4が接着剤層6で完全に覆われるように、接着剤層6の厚み寸法をバンプ4の高さ寸法よりも大きく設定する。感光性のレジスト材料としては、接着性が良好で、耐熱性、耐薬品性などにも優れるエポキシ樹脂やエポキシを主成分とする樹脂を用いることが好ましい。ただし、エポキシ系の樹脂以外でも、例えばポリイミド樹脂などを用いることができる。また、半導体基板1の外形に合わせて予め接着剤層6をシート状に形成しておき、この接着シートを半導体基板1の第1面に貼り付けることで、半導体基板1上に接着剤層6を形成してもよい。   In this case, the adhesive layer 6 may be formed with a uniform thickness by spin coating so as to cover the entire first surface of the semiconductor substrate 1 with the adhesive layer 6. Further, the thickness dimension of the adhesive layer 6 is set larger than the height dimension of the bump 4 so that all the bumps 4 formed on the semiconductor substrate 1 are completely covered with the adhesive layer 6. As the photosensitive resist material, it is preferable to use an epoxy resin having good adhesiveness and excellent heat resistance, chemical resistance, and the like, and a resin mainly composed of epoxy. However, other than epoxy resins, for example, polyimide resins can be used. Further, the adhesive layer 6 is formed in advance in a sheet shape according to the outer shape of the semiconductor substrate 1, and this adhesive sheet is attached to the first surface of the semiconductor substrate 1, whereby the adhesive layer 6 is formed on the semiconductor substrate 1. May be formed.

次に、接着剤層6の形成に用いた感光性材料がネガ型であれば、図3(A)に示すように、マスク7の開口を通して、半導体基板1の無効領域3に位置する接着剤層6Aに光を照射するとともに、有効素子領域2に位置する接着剤層6Bに光が照射されないようにマスク7で遮光することにより、後工程の現像処理で使用する現像液に対して接着剤層6の露光部分6Aを不溶化する。また、感光性材料がポジ型であれば、図3(B)に示すように、マスク7の開口を通して、半導体基板1の有効素子領域2に位置する接着剤層6Bに光を照射するとともに、無効領域3に位置する接着剤層6Aに光が照射されないようにマスク7で遮光することにより、後工程の現像処理で使用する現像液に対して接着剤層6の露光部分6Bを可溶化する。   Next, if the photosensitive material used for forming the adhesive layer 6 is a negative type, the adhesive located in the ineffective area 3 of the semiconductor substrate 1 through the opening of the mask 7 as shown in FIG. The layer 6A is irradiated with light and shielded with a mask 7 so that the adhesive layer 6B located in the effective element region 2 is not irradiated with light, whereby an adhesive is applied to the developer used in the subsequent development process. The exposed portion 6A of the layer 6 is insolubilized. If the photosensitive material is a positive type, as shown in FIG. 3B, the adhesive layer 6B located in the effective element region 2 of the semiconductor substrate 1 is irradiated with light through the opening of the mask 7, The exposed portion 6B of the adhesive layer 6 is solubilized in the developer used in the subsequent development process by shielding the adhesive layer 6A located in the ineffective area 3 with light so as not to be irradiated with light. .

次いで、マスク7による露光処理を終えた半導体基板1を現像液に浸漬させることにより、現像液に対して可溶性を示す接着剤層6を半導体基板1の第1面から取り除く。上記図3(A),(B)に示す露光処理では、半導体基板1の第1面を覆う接着剤層6の中で、有効素子領域2に位置する接着剤層6Bが現像液に対して可溶性を示し、有効領域3に位置する接着剤層6Aは現像液に対して不溶性を示すものとなる。このため、露光済みの接着剤層6を現像液で現像すると、図3(C)に示すように、有効素子領域2を覆っていた接着剤層6Bは除去され、無効領域3を覆っていた接着剤層6Aだけが除去されずに残る。   Next, the semiconductor substrate 1 that has been subjected to the exposure process using the mask 7 is immersed in a developer, thereby removing the adhesive layer 6 that is soluble in the developer from the first surface of the semiconductor substrate 1. 3A and 3B, in the adhesive layer 6 covering the first surface of the semiconductor substrate 1, the adhesive layer 6B located in the effective element region 2 is against the developer. The adhesive layer 6A that is soluble and is located in the effective area 3 is insoluble in the developer. For this reason, when the exposed adhesive layer 6 is developed with a developer, the adhesive layer 6B covering the effective element region 2 is removed and the ineffective region 3 is covered as shown in FIG. Only the adhesive layer 6A remains without being removed.

ここで、半導体基板1の全領域(平面領域)のうち、有効素子領域2については、そこを覆っている接着剤層6Bを露光・現像によって全て除去する必要がある。一方、無効領域3を覆っている接着剤層6Aについては、図4(A)に示すように無効領域3の全域に残してもよいし、図4(B)に示すように無効領域3の一部に残してもよい。また、有効素子領域2を囲むストリートの部分では、ストリートの幅よりも少し狭い幅で接着剤層6Aを残すことが望ましい。   Here, it is necessary to remove the adhesive layer 6B covering the effective element region 2 from the entire region (planar region) of the semiconductor substrate 1 by exposure and development. On the other hand, the adhesive layer 6A covering the invalid area 3 may be left over the entire invalid area 3 as shown in FIG. 4A, or the invalid area 3 as shown in FIG. 4B. You may leave some. Further, it is desirable to leave the adhesive layer 6 </ b> A with a width slightly narrower than the street width in the street portion surrounding the effective element region 2.

続いて、図5(A)に示すように、半導体基板1の第1面に接着剤層6Aを介して支持基板8を貼り付ける。接着剤層6を用いた半導体基板1と支持基板8の接着強度は、5MPa(メガパスカル)以上とすることが望ましい。支持基板8は、半導体基板1を薄肉化するための補強用として半導体基板1に張り合わせられる基板である。支持基板8としては、シリコンウエハ又はガラス基板などを用いることができる。   Subsequently, as shown in FIG. 5A, a support substrate 8 is attached to the first surface of the semiconductor substrate 1 via an adhesive layer 6A. The adhesive strength between the semiconductor substrate 1 and the support substrate 8 using the adhesive layer 6 is desirably 5 MPa (megapascal) or more. The support substrate 8 is a substrate that is bonded to the semiconductor substrate 1 for reinforcement for reducing the thickness of the semiconductor substrate 1. As the support substrate 8, a silicon wafer or a glass substrate can be used.

次に、図5(B)に示すように、支持基板8を貼り付けた状態で半導体基板1の第2面(裏面)を、例えば図示しないグラインダーを用いて研削することにより、例えば半導体基板1の厚みが50〜200μm程度まで薄くなるように、半導体基板1を薄肉化する。   Next, as shown in FIG. 5B, the second surface (back surface) of the semiconductor substrate 1 is ground with a support substrate 8 attached, for example, using a grinder (not shown), for example, the semiconductor substrate 1 The thickness of the semiconductor substrate 1 is reduced so that the thickness of the semiconductor substrate 1 is reduced to about 50 to 200 μm.

次いで、図5(C)に示すように、半導体基板1の第2面側から半導体基板1に貫通孔を形成するとともに、この貫通孔を金属等の導電性材料で埋め込むことにより、半導体基板1に貫通電極9を形成するとともに、半導体基板1の第2面に裏面配線10とバンプ11とを形成する。   Next, as shown in FIG. 5C, through holes are formed in the semiconductor substrate 1 from the second surface side of the semiconductor substrate 1, and the through holes are filled with a conductive material such as a metal, whereby the semiconductor substrate 1 A through electrode 9 is formed on the second surface, and a back surface wiring 10 and a bump 11 are formed on the second surface of the semiconductor substrate 1.

次に、図6(A)に示すように、半導体基板1の第2面にダイシングテープ(又はシート)12を貼り付けた状態で半導体装置1を図示しないダイシング装置にセットするとともに、半導体基板1とこれに貼り付けられた支持基板8に、ダイシング装置のブレードで同時に又は順に切り溝を入れることにより、ストリートに沿って有効素子領域2と無効領域3とを切り離して半導体基板1を個片化する。これにより、図6(B)に示すように、各々の有効素子領域2からチップ(半導体素子)1Aが1つずつ切り出される。   Next, as shown in FIG. 6A, the semiconductor device 1 is set in a dicing device (not shown) with the dicing tape (or sheet) 12 attached to the second surface of the semiconductor substrate 1, and the semiconductor substrate 1 In addition, the effective substrate region 2 and the ineffective region 3 are separated from each other along the street by cutting a groove into the support substrate 8 attached thereto simultaneously or sequentially with a blade of a dicing apparatus. To do. Thereby, as shown in FIG. 6B, one chip (semiconductor element) 1A is cut out from each effective element region 2 one by one.

ちなみに、半導体基板1をダイシング装置のブレードで切断する場合は、ブレードの切刃部分が接着剤層6Aに接触しないように、半導体基板1とブレードの位置出しを行なうことが望ましい。また、ストリート部分における無効領域3の幅(ストリート幅)も、基板の張り合わせに必要な接着面積を確保し、かつブレードと接着剤層6Aの接触を避け得る程度の寸法を確保することが望ましい。   Incidentally, when the semiconductor substrate 1 is cut with a blade of a dicing apparatus, it is desirable to position the semiconductor substrate 1 and the blade so that the cutting edge portion of the blade does not contact the adhesive layer 6A. In addition, it is desirable that the width of the invalid area 3 (street width) in the street portion also secures a dimension that can secure a bonding area necessary for bonding the substrates and avoid contact between the blade and the adhesive layer 6A.

[第2実施形態]
図7及び図8は本発明の第2実施形態に係る半導体装置の製造方法を示す工程図である。この第2実施形態においては、上記第1実施形態と同様の手順で、上記図5(C)に示すように、半導体基板1に貫通電極9、裏面配線10及びバンプ11を形成した後、図7(A)に示すように、半導体基板1の第2面(裏面)にバンプ11を介して半導体素子(チップ)13をフリップチップ方式で実装する。
[Second Embodiment]
7 and 8 are process diagrams showing a method of manufacturing a semiconductor device according to the second embodiment of the present invention. In the second embodiment, the through electrode 9, the back surface wiring 10, and the bump 11 are formed on the semiconductor substrate 1 as shown in FIG. 5C in the same procedure as the first embodiment. As shown in FIG. 7A, the semiconductor element (chip) 13 is mounted on the second surface (back surface) of the semiconductor substrate 1 via the bumps 11 by a flip chip method.

次いで、図7(B)に示すように、半導体基板1と半導体素子13との間(隙間部分)に例えば液状のエポキシ樹脂からなるアンダーフィル樹脂14を注入して、これを乾燥又は熱処理等で硬化させる。   Next, as shown in FIG. 7B, an underfill resin 14 made of, for example, a liquid epoxy resin is injected between the semiconductor substrate 1 and the semiconductor element 13 (gap portion), and this is dried or heat-treated. Harden.

続いて、図7(C)に示すように、半導体基板1の第2面にダイシングテープ(又はシート)15を貼り付ける。この場合、半導体基板1の第2面には半導体素子13が実装されているが、素子自体の厚みは非常に薄いため、素子による基板面の凹凸はダイシングテープ15の変形によって吸収される。   Subsequently, as shown in FIG. 7C, a dicing tape (or sheet) 15 is attached to the second surface of the semiconductor substrate 1. In this case, the semiconductor element 13 is mounted on the second surface of the semiconductor substrate 1, but since the thickness of the element itself is very thin, the unevenness of the substrate surface by the element is absorbed by the deformation of the dicing tape 15.

次に、図8(A)に示すように、半導体基板1にダイシングテープ15を貼り付けた状態で半導体基板1を図示しないダイシング装置にセットするとともに、半導体基板1とこれに貼り付けられた支持基板8に、ダイシング装置のブレードで同時に又は順に切り溝を入れることにより、ストリートに沿って有効素子領域2と無効領域3とを切り離して半導体基板1を個片化する。これにより、図8(B)に示すように、各々の有効素子領域2から、半導体素子13と積層構造をなすチップオンチップ構造の半導体素子1Aが1つずつ切り出される。   Next, as shown in FIG. 8A, the semiconductor substrate 1 is set in a dicing apparatus (not shown) with the dicing tape 15 attached to the semiconductor substrate 1, and the semiconductor substrate 1 and the support attached to the semiconductor substrate 1 are attached. The semiconductor substrate 1 is separated into pieces by cutting the effective element region 2 and the ineffective region 3 along the street by cutting grooves into the substrate 8 simultaneously or sequentially with a blade of a dicing apparatus. As a result, as shown in FIG. 8B, a semiconductor element 1A having a chip-on-chip structure having a stacked structure with the semiconductor element 13 is cut out one by one from each effective element region 2.

以上の製造方法においては、半導体基板1の第1面に感光性のレジスト材料を用いて形成した接着剤層6を露光・現像することにより、有効素子領域2から接着剤層6Bを除去し、支持基板8の貼り付けは、無効領域3に残した接着剤層6Aを用いて行なうため、半導体基板1を個片化する工程(ダイシング工程等)の前に、半導体基板1から支持基板8を剥離する必要がなくなる。このため、半導体基板1から切り出された半導体素子(チップ)1Aの第1面(主面)に接着剤の残渣が残ることがない。   In the above manufacturing method, the adhesive layer 6B formed from the photosensitive resist material on the first surface of the semiconductor substrate 1 is exposed and developed to remove the adhesive layer 6B from the effective element region 2, Since the support substrate 8 is attached using the adhesive layer 6A left in the ineffective region 3, the support substrate 8 is attached to the semiconductor substrate 1 from the semiconductor substrate 1 before the process of dicing the semiconductor substrate 1 (such as a dicing process). No need to peel. For this reason, an adhesive residue does not remain on the first surface (main surface) of the semiconductor element (chip) 1A cut out from the semiconductor substrate 1.

また、基板貼り付け用の接着剤に剥離性が要求されなくなるため、接着剤の材料として、耐熱性や耐薬品性などに優れた材料(例えば、エポキシ樹脂など)を利用することができる。このため、半導体基板1に支持基板8を貼り付けた状態で、例えば上述のように貫通電極9や裏面配線10、バンプ11などを半導体基板1に形成する場合に、プロセス温度が300℃程度の高温となっても、接着剤層6の変質や性能劣化を抑えて所望の接着強度(仮固定性)を維持することができる。このため、半導体基板1と支持基板8の剥離を確実に防止することが可能となる。   In addition, since peelability is not required for the adhesive for pasting the substrate, a material excellent in heat resistance, chemical resistance, etc. (for example, epoxy resin) can be used as the adhesive material. For this reason, when the through electrode 9, the back surface wiring 10, the bump 11, and the like are formed on the semiconductor substrate 1 with the support substrate 8 attached to the semiconductor substrate 1, for example, the process temperature is about 300 ° C. Even when the temperature is high, it is possible to maintain the desired adhesive strength (temporary fixability) while suppressing deterioration and performance deterioration of the adhesive layer 6. For this reason, it becomes possible to prevent peeling of the semiconductor substrate 1 and the support substrate 8 reliably.

また、半導体基板1に支持基板8を貼り付けた状態では、図9に示すように、接着剤層6の厚み寸法Tをバンプ4の高さ寸法Hよりも大としているため、例えば所望の接着強度や密着状態を得るために支持基板8を接着剤層6に押し付けても、バンプ4にダメージを与える恐れがない。このため、バンプ4のダメージによる接合不良を防止して歩留まりを向上させることができる。   Further, in the state where the support substrate 8 is attached to the semiconductor substrate 1, the thickness dimension T of the adhesive layer 6 is larger than the height dimension H of the bump 4 as shown in FIG. Even if the support substrate 8 is pressed against the adhesive layer 6 in order to obtain strength and adhesion, there is no possibility of damaging the bumps 4. For this reason, it is possible to prevent the bonding failure due to the damage of the bumps 4 and improve the yield.

本発明の第1実施形態に係る半導体装置の製造方法を示す工程図(その1)である。FIG. 6 is a process diagram (part 1) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention; 本発明の第1実施形態に係る半導体装置の製造方法を示す工程図(その2)である。FIG. 6 is a process diagram (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention; 本発明の第1実施形態に係る半導体装置の製造方法を示す工程図(その3)である。It is process drawing (the 3) which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. 本発明の第1実施形態に係る半導体装置の製造方法を示す工程図(その4)である。FIG. 8 is a process diagram (part 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention; 本発明の第1実施形態に係る半導体装置の製造方法を示す工程図(その5)である。It is process drawing (the 5) which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. 本発明の第1実施形態に係る半導体装置の製造方法を示す工程図(その6)である。It is process drawing (the 6) which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. 本発明の第2実施形態に係る半導体装置の製造方法を示す工程図(その1)である。It is process drawing (the 1) which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention. 本発明の第2実施形態に係る半導体装置の製造方法を示す工程図(その2)である。It is process drawing (the 2) which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention. 接着剤層の厚み寸法とバンプの高さ寸法の関係を示す図である。It is a figure which shows the relationship between the thickness dimension of an adhesive bond layer, and the height dimension of a bump. 従来の半導体装置の製造方法を説明する図である。It is a figure explaining the manufacturing method of the conventional semiconductor device.

符号の説明Explanation of symbols

1…半導体基板、2…有効素子領域、3…無効領域、4…バンプ、6…接着剤層、8…支持基板   DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Effective element area | region, 3 ... Invalid area | region, 4 ... Bump, 6 ... Adhesive layer, 8 ... Support substrate

Claims (2)

素子回路が形成される有効素子領域と前記有効素子領域を囲む無効領域とを含む半導体基板の第1面に、感光性材料からなる接着剤層を形成する第1工程と、
前記有効素子領域から前記接着剤層を除去しかつ前記無効領域に前記接着剤層を残す状態で前記接着剤層を露光・現像する第2工程と、
前記半導体基板の第1面に前記接着剤層を介して支持基板を貼り付ける第3工程と、
前記支持基板を貼り付けた状態で前記半導体基板に所定の処理を施す第4工程と、
前記有効素子領域と前記無効領域とを切り離して前記半導体基板を個片化する第5工程と
を含むことを特徴とする半導体装置の製造方法。
A first step of forming an adhesive layer made of a photosensitive material on a first surface of a semiconductor substrate including an effective element region in which an element circuit is formed and an ineffective region surrounding the effective element region;
A second step of exposing and developing the adhesive layer while removing the adhesive layer from the effective element region and leaving the adhesive layer in the ineffective region;
A third step of attaching a support substrate to the first surface of the semiconductor substrate via the adhesive layer;
A fourth step of applying a predetermined treatment to the semiconductor substrate with the support substrate attached thereto;
And a fifth step of separating the semiconductor substrate by separating the effective element region and the ineffective region from each other.
前記第1工程において、前記接着剤層の厚み寸法を、前記半導体基板の第1面に形成された突起電極の高さ寸法よりも大とする
ことを特徴とする請求項1記載の半導体装置の製造方法。
2. The semiconductor device according to claim 1, wherein in the first step, a thickness dimension of the adhesive layer is made larger than a height dimension of a protruding electrode formed on the first surface of the semiconductor substrate. Production method.
JP2006312389A 2006-11-20 2006-11-20 Method of manufacturing semiconductor device Pending JP2008130705A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011204858A (en) * 2010-03-25 2011-10-13 Nec Corp Method of manufacturing semiconductor device, and method of manufacturing laminated semiconductor device
JP2012146892A (en) * 2011-01-14 2012-08-02 Renesas Electronics Corp Method for manufacturing semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011204858A (en) * 2010-03-25 2011-10-13 Nec Corp Method of manufacturing semiconductor device, and method of manufacturing laminated semiconductor device
JP2012146892A (en) * 2011-01-14 2012-08-02 Renesas Electronics Corp Method for manufacturing semiconductor device

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