WO2020094095A1 - Ultra-thin incoming material packaging method and packaging structure - Google Patents
Ultra-thin incoming material packaging method and packaging structure Download PDFInfo
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- WO2020094095A1 WO2020094095A1 PCT/CN2019/116270 CN2019116270W WO2020094095A1 WO 2020094095 A1 WO2020094095 A1 WO 2020094095A1 CN 2019116270 W CN2019116270 W CN 2019116270W WO 2020094095 A1 WO2020094095 A1 WO 2020094095A1
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
- H01L2224/11002—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for supporting the semiconductor or solid-state body
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- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
- H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
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- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
Definitions
- the present application relates to the technical field of semiconductor device fabrication, for example, to an ultra-thin incoming packaging method and packaging structure.
- packaging technology is actually a technology for packaging chips. This packaging is necessary for chips. Because the chip must be isolated from the outside world to prevent the impurities in the air from corroding the chip circuit and causing electrical performance to deteriorate. On the other hand, the packaged chips are also easier to install and transport. Therefore, packaging technology is a very critical part of the integrated circuit industry.
- three-dimensional packaging technology 3D Package
- the advantage of three-dimensional packaging is that it can increase the density of interconnect lines and reduce the overall height of the device shape. Because it is possible to stack different types of chips together and have a high interconnect line density, the three-dimensional packaging technology has a good application prospect.
- connection path of through-silicon-via (TSV, Through-Silicon-Via) electrodes can be shortened to the thickness of only one chip, so the interconnection with the shortest path and the highest integration can be realized.
- a system-level integration solution for interconnection through TSVs can reduce the interconnect area delay while reducing chip area.
- the thickness of the wafer needs to be reduced to at least 70um, and when the wafer is reduced to less than 100um, the wafer will become extremely fragile.
- the edge of the wafer may be warped or even broken.
- the present application provides an ultra-thin incoming packaging method and packaging structure to solve the problem that wafers in the prior art are prone to warp or even break during the manufacturing process.
- An ultra-thin incoming packaging method including:
- the ultra-thin wafer includes a first surface and a second surface that are disposed oppositely.
- the first surface of the ultra-thin wafer has a plurality of functional regions arranged in an array, two adjacent There are cutting channels between the functional areas, and the first surface includes a plurality of bonding pads electrically connected to the functional areas;
- solder bumps are electrically connected to the solder pads
- the first tape is bonded to the top surface of the carrier board and the circuit board;
- This application provides a packaging structure, including:
- a circuit board the circuit board includes a plurality of circuit structures, and a cutting channel is provided between two adjacent circuit structures;
- one chip is electrically connected to one of the circuit structures;
- a bearing board located on each chip away from the circuit board
- FIG. 1 is a schematic flowchart of an ultra-thin incoming packaging method provided by an embodiment of the present application
- FIG. 2 is a schematic top view of an ultra-thin incoming material provided by an embodiment of the present application
- FIG. 3 is a schematic diagram of the cross-sectional structure along line AA 'in FIG. 2;
- FIG. 4 is a schematic diagram of a cross-sectional structure of an ultra-thin incoming material after bonding a carrier plate provided by an embodiment of the present application;
- FIG. 5 is a schematic diagram of a structure of an ultra-thin incoming material after cutting according to an embodiment of the present application
- 7 to 11 are process schematic diagrams of performing a TSV process on an ultra-thin wafer provided by an embodiment of this application;
- FIG. 12 is a schematic structural diagram of a single chip after cutting according to an embodiment of the present application.
- FIG. 13 is a schematic structural diagram of flipping a single chip onto a circuit board according to an embodiment of the application.
- FIG. 14 is a schematic diagram of a top structure corresponding to FIG. 13 provided by an embodiment of the present application.
- FIG. 15 is a schematic structural diagram of a circuit board after being covered with a first adhesive tape according to an embodiment of the present application
- 16 is a schematic structural diagram of a top view of a circuit board covered with a first adhesive tape provided by an embodiment of the present application;
- FIG. 17 is a schematic structural diagram of a first adhesive tape provided by an embodiment of the present application.
- FIG. 18 is a schematic cross-sectional structure diagram of a packaging structure provided by an embodiment of the present application.
- FIG. 1 is a schematic flowchart of an ultra-thin incoming packaging method provided in an embodiment of the present application.
- the ultra-thin incoming packaging method includes:
- the ultra-thin wafer includes a first surface and a second surface that are oppositely arranged.
- the first surface of the ultra-thin wafer is formed with a plurality of functional regions arranged in an array, adjacent to each other. There is a cutting channel between the two functional areas, and the first surface includes a plurality of bonding pads electrically connected to the functional areas;
- FIG. 2 is a schematic structural view of a top view of an ultra-thin incoming material provided by an embodiment of the present application
- FIG. 3 is a schematic cross-sectional structure diagram taken along line AA 'in FIG. Only two functional areas are exemplified in FIG. 3, which does not mean that only two functional areas are provided on the ultra-thin wafer; as shown in FIG.
- the ultra-thin wafer 100 includes a first surface 101 and a second surface that are oppositely arranged Surface 102; a plurality of functional regions 11 arranged in an array are formed on the first surface 101 of the ultra-thin wafer 100, and a cutting channel 10 is provided between two adjacent functional regions 11, and the cutting channel 10 is used for subsequent The wafer is cut into multiple chips.
- the first surface 101 further includes a plurality of bonding pads 12 electrically connected to the functional area 11.
- the pad 12 is used to electrically connect the functional area and the external circuit.
- the ultra-thin wafer may specifically include: providing an ultra-thin wafer with a second tape 200, the second tape 200 adheres to the second surface 102 of the ultra-thin wafer 100, and the edge of the second tape Provided with a metal ring 201. Referring to FIG. 3, the second surface 102 of the ultra-thin wafer 100 is adhered to the surface of the second tape 200, and the edge of the second tape 200 is provided with a metal ring 201.
- the ultra-thin wafer 100 with the second tape 200 and the metal ring 201 described in this embodiment is an ultra-thin incoming material, wherein the presence of the second tape 200 and the metal ring 201 can provide the ultra-thin wafer 100 Protection to prevent the wafer 100 from being broken due to large external forces during transportation.
- this embodiment also It includes the following step S102.
- the ultra-thin incoming material is actually a structure composed of an ultra-thin wafer, a second tape, and a metal ring. Therefore, after providing the ultra-thin wafer with the second tape, and before bonding the carrier board on the first surface of the ultra-thin wafer, the step of removing the metal ring and the second tape is further included, specifically including:
- the second adhesive tape, the ultra-thin wafer and the carrier board are cut out to obtain a temporary bonding structure, and the metal ring and the excess second adhesive tape are removed.
- the carrier board 300 is temporarily bonded to the first surface 101 of the ultra-thin wafer 100 with the second tape.
- the specific material of the carrier board 300 is not limited in this embodiment, as long as the carrier board 300 It is sufficient to provide supporting stress to the ultra-thin wafer 100 in the subsequent process to avoid the ultra-thin wafer 100 from cracking.
- the carrier board 300 may be transparent, that is, the carrier board is a transparent carrier board. It may also be opaque, which is not limited in this embodiment. In order to facilitate the subsequent process, in this embodiment, the carrier board 300 may be made of a transparent material, more optionally, made of glass material.
- the temporary bonding described here is not a real bonding process, but only the bonding of the carrier board 300 and the first surface 101 of the ultra-thin wafer 100, and there is a certain adhesion between the two. However, it cannot be used in other processes of ultra-thin wafers.
- the embodiment of the present application does not limit the specific process of temporarily bonding the first surface of the ultra-thin wafer with the second tape to the carrier board.
- the specific process may be:
- the carrier board is bonded to the first surface of the ultra-thin wafer with the second adhesive tape through the photo-curable adhesive.
- the photocurable adhesive may be UV Adhesive.
- the edge of the ultra-thin wafer 100 is used as a cutting line to remove the metal ring 201 and the excess second adhesive tape 200.
- the ultra-thin wafer 100 and the second tape 200 and the carrier board 300 having the same size and shape as the ultra-thin wafer 100 are obtained by cutting.
- this structure is called a temporary bonding structure.
- bonding the carrier board to the first surface of the ultra-thin wafer specifically includes:
- the second tape can be removed, and when the subsequent etching or other processes are performed on the ultra-thin wafer, the carrier plate 300 can be ultra-thin
- the thin wafer 100 provides the necessary stress support to avoid warping or cracking of the ultra-thin wafer during high temperature or etching processes.
- the specific process of real bonding between the ultra-thin wafer and the carrier board in the temporary bonding structure is not limited.
- the carrier board is a transparent carrier board
- the photocurable adhesive is In the case of UV adhesives, the bonding process of ultra-thin wafers and carrier boards can specifically include:
- the UV adhesive is cured so that the first surface of the ultra-thin wafer in the temporary bonding structure is bonded to the carrier board.
- FIG. 6 is a schematic cross-sectional structural view of the first surface of the ultra-thin wafer bonded to the carrier plate; the first surface 101 of the ultra-thin wafer 100 includes a plurality of functional areas 11, two adjacent There are cutting channels 10 between the functional areas 11 and a plurality of bonding pads 12 electrically connected to the functional areas 11.
- the PP ′ cross-sectional view in FIG. 2 is used as an example for description.
- the ultra-thin wafer 100 After the ultra-thin wafer 100 is bonded to the carrier plate 300, since the carrier plate 300 has a support and protection effect on the ultra-thin wafer 100, the ultra-thin wafer 100 can be appropriately punched, etched, etc. Process.
- FIG. 7 is a process of forming a through hole on the ultra-thin wafer 100 to expose the pad.
- the specific process of forming a plurality of through holes 103 on the second surface 102 of the ultra-thin wafer 100 to expose the bonding pad 12 is not limited in this embodiment. In an embodiment of the present application, it may be specific include:
- An etching treatment is performed on the position of the second surface of the ultra-thin wafer corresponding to the bonding pad to expose the bonding pad 12.
- an insulating layer is formed on the second surface of the ultra-thin wafer with a plurality of through holes.
- an insulating layer 400 covers the second surface 102 of the ultra-thin wafer 100 and the insulating layer 400 covers the The side wall of the through hole 103 exposes the bottom surface of the through hole 103; the pad 12 is located on the bottom surface of the through hole 103 so as to be exposed to the outside.
- a re-wiring layer 500 is formed on the insulating layer 400, and the re-wiring layer 500 is connected to the pad 12 at the bottom of the through hole 103; thereby, the pad 12 can be electrically connected to The second surface of the ultra-thin wafer 100.
- a solder resist layer 600 is formed, and the solder resist layer 600 covers the re-wiring layer 500 and the insulating layer 400; the solder resist layer 600 is used to protect the re-wiring layer 500 to avoid the re-wiring layer 500 There is a short circuit with other electrical components in the outside world, causing the device to fail.
- an opening 601 is formed on the solder resist layer 600.
- the opening 601 exposes part of the redistribution layer 500 for subsequent formation of solder bumps.
- solder bumps are electrically connected to the solder pads
- the plurality of solder bumps are used to electrically connect the pad 12 electrically connecting the first surface 101 of the ultra-thin wafer 100 and the functional area 11 to the second surface 102 of the ultra-thin wafer 100, and then It is used for electrical connection with external circuits. In this embodiment, it is formed by the TSV process. Therefore, referring to FIG. 11, in this embodiment, a plurality of solder bumps 700 are formed on the second surface of the ultra-thin wafer.
- the solder bump 700 is electrically connected to the solder pad 12 and may specifically include:
- the solder bump 700 is electrically connected to the rewiring layer 500, and is electrically connected to the pad 12 through the rewiring layer 500.
- the ultra-thin wafer 100 and the carrier board 300 are cut to form a plurality of single-chip chip packaging units.
- the specific cutting process is not limited, and the cutting process may be used, or the cutting process and the etching process layer may be used to complete the cutting.
- the cutting process can be performed by using a knife process. The knife process can be completed in one cut, or multiple cuts, each cutting to a certain depth, and finally the ultra-thin wafer and the carrier board can be cut through. This is not limited in this embodiment.
- the specific structure of the circuit board is not limited in this embodiment, and the circuit board is used to electrically connect the single-chip package unit with an external circuit.
- the specific material of the circuit board is not limited in this embodiment, and the circuit board may be a PCB ( The Printed Circuit Board (printed circuit) board may also be an FPC (Flexible Printed Circuit) board. In one embodiment of the present application, it is preferably a PCB board.
- a plurality of single-chip chips 1 are flip-chip mounted on a circuit board 800 by specifically connecting the solder bumps 700 on the single-chip chips and the circuits on the circuit board 800 by soldering or conductive glue, Thus, the functional area on the single chip is electrically connected with other external circuits.
- FIG. 14 it is a schematic plan view of a plurality of single-chip chips flip-chip mounted on a circuit board.
- the first adhesive tape is covered on the top surface of the carrier board. Please refer to FIG. 15, that is, after the single chip is flip-chip mounted on the circuit board 800, the first surface of the single chip is also bonded with the carrier board 300, and after the first tape 900 covers the chip array, it is adhered to the carrier board 300 Knot.
- the specific material of the first adhesive tape is not limited in this embodiment.
- the first adhesive tape may be a transparent adhesive tape.
- the material may be the same as or different from the material of the second tape, which is not limited in this embodiment.
- FIG. 16 it is a schematic view of the top structure of the circuit board after covering the first tape 900; since the first tape is a flexible material, the area between the two adjacent single-chip chips is also covered to form the first tape 900, that is An accommodating cavity is formed between the first tape 900 and the circuit board 800, thereby fixing and sealing the periphery of the single-chip chip, so as to prevent substances in the external environment from entering between the chip and the circuit board, causing pollution or damage to the chip surface .
- the debonding process is related to the bonding process between the ultra-thin wafer and the carrier board described above.
- the ultra-thin wafer and the carrier board are bonded using a light-curing adhesive.
- the unbonding the carrier board and the multiple single-chip chips may specifically include:
- the side of the carrier board is irradiated with laser, and the UV adhesive is unbonded between the carrier board and the chip through the first adhesive tape and the carrier board.
- the materials of the carrier board and the first adhesive tape are both transparent materials.
- the UV light can remove the tackiness of the UV adhesive between the carrier plate and the ultra-thin wafer through the first tape and the carrier plate, thereby removing the bonding force between the ultra-thin wafer and the first tape, which is convenient for subsequent use.
- the chip packaged by the ultra-thin incoming packaging method provided in the embodiment of the present application It also includes the carrier board, the first tape and the circuit board.
- the bonding force between the ultra-thin wafer of the chip and the carrier board has been removed, after transportation, when the subsequent process is required, it is only necessary to tear off the first tape, which bonds the carrier Board, separating the carrier board from the chip.
- the first adhesive tape 900 can be directly peeled off from the circuit board.
- the carrier board 300 is taped by the adhesion of the first adhesive tape 900 From the circuit board 800.
- the ultra-thin incoming packaging method includes: providing ultra-thin wafers, forming a carrier board by temporarily bonding on the ultra-thin wafers, and then flipping the ultra-thin wafers after bonding the carrier board on the circuit board On the last, cover with a first layer of adhesive tape for subsequent transportation.
- a single chip is formed in the ultra-thin wafer process, and then flipped onto the circuit board and covered with the first tape, then the carrier board and the ultra-thin wafer are unbonded, and the first tape and the circuit board are accommodated
- the cavity is used for accommodating single-chip chips, so as to provide protection for the single-chip chips during transportation.
- the carrier tape can be taken away from the circuit board while tearing off the first adhesive tape, so that the subsequent process can be conveniently performed. That is, the bonding carrier board reduces the risk of ultra-thin incoming materials being prone to warping or even breaking during the wafer manufacturing process. At the same time, it can protect the single chip during transportation, and subsequent use does not affect other processes. get on.
- FIG. 18 is a schematic diagram of a packaging structure provided by an embodiment of the present application; the packaging The structure includes:
- a circuit board 800 the circuit board 800 includes a plurality of circuit structures, and a cutting path 80 is provided between two adjacent circuit structures;
- one chip 1 is electrically connected to one of the circuit structures;
- a carrier board 300 located on each chip 1 facing away from the circuit board 800;
- a first adhesive tape 900 covering the carrier plate 300 and the cutting lane 80 is bonded to the carrier plate 300 and the cutting lane 80.
- the carrier board 300 and the chip 1 may also be unbonded or pass through.
- the debonding process is not limited in this embodiment. If there is no debonding process between the carrier board 300 and the chip 1, a debonding process can be performed at a downstream manufacturer, and then the first tape is peeled off for subsequent processes, such as high temperature deposition, etching, photolithography, curing, electroplating, and chemical Processes such as cleaning; if the debonding process has been performed between the carrier board 300 and the chip 1, the first tape can be directly torn off at the downstream manufacturer, and then the subsequent process can be performed.
- An embodiment of the present application provides an ultra-thin incoming packaging structure.
- the packaging structure includes a circuit board, a plurality of chips, a carrier board, and a first adhesive tape covering a cutting path between the carrier board and adjacent chips. Since the packaging structure forms a receiving cavity between the first adhesive tape and the circuit board, multiple chips are packaged together, and there is also a carrier board to protect the chips, which can avoid warping of ultra-thin incoming materials during transportation And rupture, protect the transportation of the chip. At the same time, in the subsequent use process, directly tearing off the first adhesive tape can take away from the carrier board, thereby directly performing subsequent processes on the chips on the circuit board, and finally cutting the circuit board into a single structure along the cutting path of the circuit board.
- the ultra-thin incoming packaging method provided by the embodiment of the present application, because in this packaging method, a single chip is formed in the ultra-thin wafer process, and then flipped onto the circuit board and covered with the first tape, then the carrier board and the ultra-thin are unbonded A receiving cavity is formed between the wafer, the first adhesive tape and the circuit board, and is used to receive a single chip, so as to provide protection for the single chip during transportation.
- the carrier tape can be taken away from the circuit board while tearing off the first adhesive tape, so that the subsequent process can be conveniently performed. That is, the bonding carrier board reduces the risk of ultra-thin incoming materials being prone to warping or even breaking during the wafer manufacturing process. At the same time, it can protect the single chip during transportation, and subsequent use does not affect other processes. get on.
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Abstract
Description
Claims (14)
- 一种超薄来料封装方法,包括:An ultra-thin incoming packaging method, including:提供超薄晶圆,所述超薄晶圆包括相对设置的第一表面和第二表面,所述超薄晶圆的第一表面形成有多个呈阵列排布的功能区,相邻两个功能区之间具有切割沟道,所述第一表面包括多个与所述功能区电性连接的焊垫;An ultra-thin wafer is provided. The ultra-thin wafer includes a first surface and a second surface that are disposed oppositely. The first surface of the ultra-thin wafer has a plurality of functional regions arranged in an array, two adjacent There are cutting channels between the functional areas, and the first surface includes a plurality of bonding pads electrically connected to the functional areas;在所述超薄晶圆的第一表面键合承载板;Bonding a carrier board on the first surface of the ultra-thin wafer;在所述超薄晶圆的第二表面上形成多个通孔,暴露出所述焊垫;Forming a plurality of through holes on the second surface of the ultra-thin wafer to expose the bonding pad;在所述超薄晶圆的第二表面上制作多个焊接凸起,所述焊接凸起与所述焊垫电性连接;Forming a plurality of solder bumps on the second surface of the ultra-thin wafer, the solder bumps are electrically connected to the solder pads;切割所述超薄晶圆以及承载板形成多个单粒芯片封装单元;Cutting the ultra-thin wafer and the carrier board to form a plurality of single-chip chip packaging units;提供电路板;Provide circuit board;将多个所述单粒芯片倒装至所述电路板上,使得所述单粒芯片上的焊接凸起与所述电路板电性连接;Flipping a plurality of the single-chip chips onto the circuit board so that the solder bumps on the single-chip chips are electrically connected to the circuit board;覆盖第一胶带,所述第一胶带与所述承载板的顶面和所述电路板之间均粘结;Covering the first tape, the first tape is bonded to the top surface of the carrier board and the circuit board;解键合所述承载板和多个所述单粒芯片。Unbonding the carrier board and the plurality of single-chip chips.
- 根据权利要求1所述的超薄来料封装方法,其中,所述提供超薄晶圆,具体包括:The ultra-thin incoming packaging method according to claim 1, wherein the providing of the ultra-thin wafer specifically includes:提供带有第二胶带的超薄晶圆,所述第二胶带粘结所述超薄晶圆的第二表面,且所述第二胶带的边缘还设置有金属环。An ultra-thin wafer with a second tape is provided, the second tape adheres to the second surface of the ultra-thin wafer, and a metal ring is further provided on the edge of the second tape.
- 根据权利要求2所述的超薄来料封装方法,其特征在于,在提供带有第二胶带的超薄晶圆之后,在所述超薄晶圆的第一表面键合承载板之前,还包括:The ultra-thin incoming packaging method according to claim 2, wherein after providing the ultra-thin wafer with the second tape, and before bonding the carrier board on the first surface of the ultra-thin wafer, include:在所述带有第二胶带的超薄晶圆的第一表面临时结合所述承载板;Temporarily bonding the carrier board on the first surface of the ultra-thin wafer with the second tape;以所述超薄晶圆的边缘为裁剪线,将所述第二胶带、超薄晶圆和承载板裁剪下来得到临时键合结构,去除所述金属环和多余的第二胶带。Using the edge of the ultra-thin wafer as a cutting line, the second adhesive tape, the ultra-thin wafer and the carrier board are cut out to obtain a temporary bonding structure, and the metal ring and the excess second adhesive tape are removed.
- 根据权利要求3所述的超薄来料封装方法,其特征在于,所述在所述超薄晶圆的第一表面键合承载板,具体包括:The ultra-thin incoming packaging method according to claim 3, wherein the bonding of the carrier board on the first surface of the ultra-thin wafer specifically includes:对所述临时键合结构中的超薄晶圆和承载板实现键合;Bonding the ultra-thin wafer and the carrier board in the temporary bonding structure;去除所述第二胶带。Remove the second tape.
- 根据权利要求4所述的超薄来料封装方法,其特征在于,所述承载板为透明承载板。The ultra-thin incoming packaging method according to claim 4, wherein the carrier board is a transparent carrier board.
- 根据权利要求5所述的超薄来料封装方法,其特征在于,所述在所述带有第二胶带的超薄晶圆的第一表面临时结合所述承载板,具体为:The ultra-thin incoming packaging method according to claim 5, wherein the temporarily bonding the carrier board to the first surface of the ultra-thin wafer with the second adhesive tape is specifically:在所述带有第二胶带的超薄晶圆的第一表面涂覆光固化胶黏剂;Applying a light-curing adhesive to the first surface of the ultra-thin wafer with the second tape;将所述承载板通过所述光固化胶黏剂粘接在所述带有第二胶带的超薄晶圆的第一表面。The carrier board is bonded to the first surface of the ultra-thin wafer with the second adhesive tape through the photo-curable adhesive.
- 根据权利要求6所述的超薄来料封装方法,其特征在于,所述光固化胶黏剂为UV胶黏剂。The ultra-thin incoming packaging method according to claim 6, wherein the light-curing adhesive is a UV adhesive.
- 根据权利要求7所述的超薄来料封装方法,其特征在于,所述对所述临时键合结构中的超薄晶圆和承载板实现键合,具体包括:The ultra-thin incoming packaging method according to claim 7, wherein the bonding of the ultra-thin wafer and the carrier board in the temporary bonding structure specifically includes:采用紫外光照射所述临时键合结构的承载板侧;Using ultraviolet light to irradiate the bearing plate side of the temporary bonding structure;将所述UV胶黏剂固化,使得所述临时键合结构中的超薄晶圆的第一表面和所述承载板实现键合。The UV adhesive is cured so that the first surface of the ultra-thin wafer in the temporary bonding structure is bonded to the carrier board.
- 根据权利要求8所述的超薄来料封装方法,其特征在于,所述第一胶带为透明胶带,所述解键合所述承载板和多个所述单粒芯片,具体包括:The ultra-thin incoming packaging method according to claim 8, wherein the first adhesive tape is a transparent adhesive tape, and the unbonding the carrier board and the plurality of single-chip chips specifically include:采用激光照射所述承载板侧,激光透过所述第一胶带和所述承载板将所述UV胶黏剂,解键合所述承载板与所述芯片。The side of the carrier board is irradiated with laser, and the UV adhesive is unbonded between the carrier board and the chip through the first adhesive tape and the carrier board.
- 根据权利要求1所述的超薄来料封装方法,其特征在于,所述在所述超薄晶圆的第二表面上形成多个通孔,暴露出所述焊垫,具体包括:The ultra-thin incoming package method according to claim 1, wherein the forming of a plurality of through holes on the second surface of the ultra-thin wafer to expose the solder pad specifically includes:对所述超薄晶圆的第二表面上对应所述焊垫的位置进行刻蚀处理,暴露出所述焊垫。Performing etching treatment on the position of the second surface of the ultra-thin wafer corresponding to the bonding pad to expose the bonding pad.
- 根据权利要求10所述的超薄来料封装方法,其特征在于,在所述对所述超薄晶圆的第二表面上对应所述焊垫的位置进行刻蚀处理,暴露出所述焊垫之后还包括:The ultra-thin incoming package method according to claim 10, characterized in that an etching process is performed on the second surface of the ultra-thin wafer corresponding to the pad to expose the solder After the mat also includes:形成绝缘层,所述绝缘层覆盖所述超薄晶圆的第二表面且所述绝缘层覆盖 所述通孔的侧壁,并暴露所述通孔的底面;Forming an insulating layer, the insulating layer covering the second surface of the ultra-thin wafer and the insulating layer covering the sidewall of the through hole, and exposing the bottom surface of the through hole;在所述绝缘层上形成再布线层,所述再布线层在所述通孔的底部与所述焊垫连接;Forming a rewiring layer on the insulating layer, the rewiring layer is connected to the pad at the bottom of the through hole;形成阻焊层,所述阻焊层覆盖所述再布线层和所述绝缘层;Forming a solder resist layer covering the rewiring layer and the insulating layer;在所述阻焊层上形成开口。An opening is formed on the solder resist layer.
- 根据权利要求11所述的超薄来料封装方法,其特征在于,所述在所述超薄晶圆的第二表面上制作多个焊接凸起,所述焊接凸起与所述焊垫电性连接,具体包括:The ultra-thin incoming packaging method according to claim 11, wherein the plurality of solder bumps are formed on the second surface of the ultra-thin wafer, and the solder bumps are electrically connected to the solder pads. Sexual connection, including:在所述开口内形成焊接凸起;Forming a welding protrusion in the opening;所述焊接凸起与所述再布线层电性连接,并通过所述再布线层与所述焊垫电性连接。The solder bump is electrically connected to the rewiring layer, and is electrically connected to the pad through the rewiring layer.
- 根据权利要求1所述的超薄来料封装方法,其特征在于,还包括:The ultra-thin incoming packaging method according to claim 1, further comprising:撕离所述第一胶带,所述第一胶带粘结所述承载板,将所述承载板与所述芯片分离。The first adhesive tape is torn away, the first adhesive tape bonds the carrier board, and the carrier board is separated from the chip.
- 一种封装结构,采用权利要求1-13任意一项所述的超薄来料封装方法形成,所述封装结构包括:A packaging structure is formed by the ultra-thin incoming packaging method according to any one of claims 1-13, and the packaging structure includes:电路板,所述电路板上包括多个电路结构,相邻两个电路结构之间设置有切割道;A circuit board, the circuit board includes a plurality of circuit structures, and a cutting channel is provided between two adjacent circuit structures;多个芯片,一个芯片与一个所述电路结构电性连接;Multiple chips, one chip is electrically connected to one of the circuit structures;位于每个所述芯片背离所述电路板的承载板;A bearing board located on each chip away from the circuit board;覆盖所述承载板和所述切割道的第一胶带,所述第一胶带与所述承载板和所述切割道粘结。A first adhesive tape covering the carrier board and the cutting lane, the first adhesive tape being bonded to the carrier board and the cutting lane.
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