WO2020094095A1 - Ultra-thin incoming material packaging method and packaging structure - Google Patents

Ultra-thin incoming material packaging method and packaging structure Download PDF

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Publication number
WO2020094095A1
WO2020094095A1 PCT/CN2019/116270 CN2019116270W WO2020094095A1 WO 2020094095 A1 WO2020094095 A1 WO 2020094095A1 CN 2019116270 W CN2019116270 W CN 2019116270W WO 2020094095 A1 WO2020094095 A1 WO 2020094095A1
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Prior art keywords
ultra
thin
thin wafer
carrier board
tape
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PCT/CN2019/116270
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French (fr)
Chinese (zh)
Inventor
王之奇
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苏州晶方半导体科技股份有限公司
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Publication of WO2020094095A1 publication Critical patent/WO2020094095A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836Wafer tapes, e.g. grinding or dicing support tapes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/11001Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/11002Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for supporting the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

Definitions

  • the present application relates to the technical field of semiconductor device fabrication, for example, to an ultra-thin incoming packaging method and packaging structure.
  • packaging technology is actually a technology for packaging chips. This packaging is necessary for chips. Because the chip must be isolated from the outside world to prevent the impurities in the air from corroding the chip circuit and causing electrical performance to deteriorate. On the other hand, the packaged chips are also easier to install and transport. Therefore, packaging technology is a very critical part of the integrated circuit industry.
  • three-dimensional packaging technology 3D Package
  • the advantage of three-dimensional packaging is that it can increase the density of interconnect lines and reduce the overall height of the device shape. Because it is possible to stack different types of chips together and have a high interconnect line density, the three-dimensional packaging technology has a good application prospect.
  • connection path of through-silicon-via (TSV, Through-Silicon-Via) electrodes can be shortened to the thickness of only one chip, so the interconnection with the shortest path and the highest integration can be realized.
  • a system-level integration solution for interconnection through TSVs can reduce the interconnect area delay while reducing chip area.
  • the thickness of the wafer needs to be reduced to at least 70um, and when the wafer is reduced to less than 100um, the wafer will become extremely fragile.
  • the edge of the wafer may be warped or even broken.
  • the present application provides an ultra-thin incoming packaging method and packaging structure to solve the problem that wafers in the prior art are prone to warp or even break during the manufacturing process.
  • An ultra-thin incoming packaging method including:
  • the ultra-thin wafer includes a first surface and a second surface that are disposed oppositely.
  • the first surface of the ultra-thin wafer has a plurality of functional regions arranged in an array, two adjacent There are cutting channels between the functional areas, and the first surface includes a plurality of bonding pads electrically connected to the functional areas;
  • solder bumps are electrically connected to the solder pads
  • the first tape is bonded to the top surface of the carrier board and the circuit board;
  • This application provides a packaging structure, including:
  • a circuit board the circuit board includes a plurality of circuit structures, and a cutting channel is provided between two adjacent circuit structures;
  • one chip is electrically connected to one of the circuit structures;
  • a bearing board located on each chip away from the circuit board
  • FIG. 1 is a schematic flowchart of an ultra-thin incoming packaging method provided by an embodiment of the present application
  • FIG. 2 is a schematic top view of an ultra-thin incoming material provided by an embodiment of the present application
  • FIG. 3 is a schematic diagram of the cross-sectional structure along line AA 'in FIG. 2;
  • FIG. 4 is a schematic diagram of a cross-sectional structure of an ultra-thin incoming material after bonding a carrier plate provided by an embodiment of the present application;
  • FIG. 5 is a schematic diagram of a structure of an ultra-thin incoming material after cutting according to an embodiment of the present application
  • 7 to 11 are process schematic diagrams of performing a TSV process on an ultra-thin wafer provided by an embodiment of this application;
  • FIG. 12 is a schematic structural diagram of a single chip after cutting according to an embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of flipping a single chip onto a circuit board according to an embodiment of the application.
  • FIG. 14 is a schematic diagram of a top structure corresponding to FIG. 13 provided by an embodiment of the present application.
  • FIG. 15 is a schematic structural diagram of a circuit board after being covered with a first adhesive tape according to an embodiment of the present application
  • 16 is a schematic structural diagram of a top view of a circuit board covered with a first adhesive tape provided by an embodiment of the present application;
  • FIG. 17 is a schematic structural diagram of a first adhesive tape provided by an embodiment of the present application.
  • FIG. 18 is a schematic cross-sectional structure diagram of a packaging structure provided by an embodiment of the present application.
  • FIG. 1 is a schematic flowchart of an ultra-thin incoming packaging method provided in an embodiment of the present application.
  • the ultra-thin incoming packaging method includes:
  • the ultra-thin wafer includes a first surface and a second surface that are oppositely arranged.
  • the first surface of the ultra-thin wafer is formed with a plurality of functional regions arranged in an array, adjacent to each other. There is a cutting channel between the two functional areas, and the first surface includes a plurality of bonding pads electrically connected to the functional areas;
  • FIG. 2 is a schematic structural view of a top view of an ultra-thin incoming material provided by an embodiment of the present application
  • FIG. 3 is a schematic cross-sectional structure diagram taken along line AA 'in FIG. Only two functional areas are exemplified in FIG. 3, which does not mean that only two functional areas are provided on the ultra-thin wafer; as shown in FIG.
  • the ultra-thin wafer 100 includes a first surface 101 and a second surface that are oppositely arranged Surface 102; a plurality of functional regions 11 arranged in an array are formed on the first surface 101 of the ultra-thin wafer 100, and a cutting channel 10 is provided between two adjacent functional regions 11, and the cutting channel 10 is used for subsequent The wafer is cut into multiple chips.
  • the first surface 101 further includes a plurality of bonding pads 12 electrically connected to the functional area 11.
  • the pad 12 is used to electrically connect the functional area and the external circuit.
  • the ultra-thin wafer may specifically include: providing an ultra-thin wafer with a second tape 200, the second tape 200 adheres to the second surface 102 of the ultra-thin wafer 100, and the edge of the second tape Provided with a metal ring 201. Referring to FIG. 3, the second surface 102 of the ultra-thin wafer 100 is adhered to the surface of the second tape 200, and the edge of the second tape 200 is provided with a metal ring 201.
  • the ultra-thin wafer 100 with the second tape 200 and the metal ring 201 described in this embodiment is an ultra-thin incoming material, wherein the presence of the second tape 200 and the metal ring 201 can provide the ultra-thin wafer 100 Protection to prevent the wafer 100 from being broken due to large external forces during transportation.
  • this embodiment also It includes the following step S102.
  • the ultra-thin incoming material is actually a structure composed of an ultra-thin wafer, a second tape, and a metal ring. Therefore, after providing the ultra-thin wafer with the second tape, and before bonding the carrier board on the first surface of the ultra-thin wafer, the step of removing the metal ring and the second tape is further included, specifically including:
  • the second adhesive tape, the ultra-thin wafer and the carrier board are cut out to obtain a temporary bonding structure, and the metal ring and the excess second adhesive tape are removed.
  • the carrier board 300 is temporarily bonded to the first surface 101 of the ultra-thin wafer 100 with the second tape.
  • the specific material of the carrier board 300 is not limited in this embodiment, as long as the carrier board 300 It is sufficient to provide supporting stress to the ultra-thin wafer 100 in the subsequent process to avoid the ultra-thin wafer 100 from cracking.
  • the carrier board 300 may be transparent, that is, the carrier board is a transparent carrier board. It may also be opaque, which is not limited in this embodiment. In order to facilitate the subsequent process, in this embodiment, the carrier board 300 may be made of a transparent material, more optionally, made of glass material.
  • the temporary bonding described here is not a real bonding process, but only the bonding of the carrier board 300 and the first surface 101 of the ultra-thin wafer 100, and there is a certain adhesion between the two. However, it cannot be used in other processes of ultra-thin wafers.
  • the embodiment of the present application does not limit the specific process of temporarily bonding the first surface of the ultra-thin wafer with the second tape to the carrier board.
  • the specific process may be:
  • the carrier board is bonded to the first surface of the ultra-thin wafer with the second adhesive tape through the photo-curable adhesive.
  • the photocurable adhesive may be UV Adhesive.
  • the edge of the ultra-thin wafer 100 is used as a cutting line to remove the metal ring 201 and the excess second adhesive tape 200.
  • the ultra-thin wafer 100 and the second tape 200 and the carrier board 300 having the same size and shape as the ultra-thin wafer 100 are obtained by cutting.
  • this structure is called a temporary bonding structure.
  • bonding the carrier board to the first surface of the ultra-thin wafer specifically includes:
  • the second tape can be removed, and when the subsequent etching or other processes are performed on the ultra-thin wafer, the carrier plate 300 can be ultra-thin
  • the thin wafer 100 provides the necessary stress support to avoid warping or cracking of the ultra-thin wafer during high temperature or etching processes.
  • the specific process of real bonding between the ultra-thin wafer and the carrier board in the temporary bonding structure is not limited.
  • the carrier board is a transparent carrier board
  • the photocurable adhesive is In the case of UV adhesives, the bonding process of ultra-thin wafers and carrier boards can specifically include:
  • the UV adhesive is cured so that the first surface of the ultra-thin wafer in the temporary bonding structure is bonded to the carrier board.
  • FIG. 6 is a schematic cross-sectional structural view of the first surface of the ultra-thin wafer bonded to the carrier plate; the first surface 101 of the ultra-thin wafer 100 includes a plurality of functional areas 11, two adjacent There are cutting channels 10 between the functional areas 11 and a plurality of bonding pads 12 electrically connected to the functional areas 11.
  • the PP ′ cross-sectional view in FIG. 2 is used as an example for description.
  • the ultra-thin wafer 100 After the ultra-thin wafer 100 is bonded to the carrier plate 300, since the carrier plate 300 has a support and protection effect on the ultra-thin wafer 100, the ultra-thin wafer 100 can be appropriately punched, etched, etc. Process.
  • FIG. 7 is a process of forming a through hole on the ultra-thin wafer 100 to expose the pad.
  • the specific process of forming a plurality of through holes 103 on the second surface 102 of the ultra-thin wafer 100 to expose the bonding pad 12 is not limited in this embodiment. In an embodiment of the present application, it may be specific include:
  • An etching treatment is performed on the position of the second surface of the ultra-thin wafer corresponding to the bonding pad to expose the bonding pad 12.
  • an insulating layer is formed on the second surface of the ultra-thin wafer with a plurality of through holes.
  • an insulating layer 400 covers the second surface 102 of the ultra-thin wafer 100 and the insulating layer 400 covers the The side wall of the through hole 103 exposes the bottom surface of the through hole 103; the pad 12 is located on the bottom surface of the through hole 103 so as to be exposed to the outside.
  • a re-wiring layer 500 is formed on the insulating layer 400, and the re-wiring layer 500 is connected to the pad 12 at the bottom of the through hole 103; thereby, the pad 12 can be electrically connected to The second surface of the ultra-thin wafer 100.
  • a solder resist layer 600 is formed, and the solder resist layer 600 covers the re-wiring layer 500 and the insulating layer 400; the solder resist layer 600 is used to protect the re-wiring layer 500 to avoid the re-wiring layer 500 There is a short circuit with other electrical components in the outside world, causing the device to fail.
  • an opening 601 is formed on the solder resist layer 600.
  • the opening 601 exposes part of the redistribution layer 500 for subsequent formation of solder bumps.
  • solder bumps are electrically connected to the solder pads
  • the plurality of solder bumps are used to electrically connect the pad 12 electrically connecting the first surface 101 of the ultra-thin wafer 100 and the functional area 11 to the second surface 102 of the ultra-thin wafer 100, and then It is used for electrical connection with external circuits. In this embodiment, it is formed by the TSV process. Therefore, referring to FIG. 11, in this embodiment, a plurality of solder bumps 700 are formed on the second surface of the ultra-thin wafer.
  • the solder bump 700 is electrically connected to the solder pad 12 and may specifically include:
  • the solder bump 700 is electrically connected to the rewiring layer 500, and is electrically connected to the pad 12 through the rewiring layer 500.
  • the ultra-thin wafer 100 and the carrier board 300 are cut to form a plurality of single-chip chip packaging units.
  • the specific cutting process is not limited, and the cutting process may be used, or the cutting process and the etching process layer may be used to complete the cutting.
  • the cutting process can be performed by using a knife process. The knife process can be completed in one cut, or multiple cuts, each cutting to a certain depth, and finally the ultra-thin wafer and the carrier board can be cut through. This is not limited in this embodiment.
  • the specific structure of the circuit board is not limited in this embodiment, and the circuit board is used to electrically connect the single-chip package unit with an external circuit.
  • the specific material of the circuit board is not limited in this embodiment, and the circuit board may be a PCB ( The Printed Circuit Board (printed circuit) board may also be an FPC (Flexible Printed Circuit) board. In one embodiment of the present application, it is preferably a PCB board.
  • a plurality of single-chip chips 1 are flip-chip mounted on a circuit board 800 by specifically connecting the solder bumps 700 on the single-chip chips and the circuits on the circuit board 800 by soldering or conductive glue, Thus, the functional area on the single chip is electrically connected with other external circuits.
  • FIG. 14 it is a schematic plan view of a plurality of single-chip chips flip-chip mounted on a circuit board.
  • the first adhesive tape is covered on the top surface of the carrier board. Please refer to FIG. 15, that is, after the single chip is flip-chip mounted on the circuit board 800, the first surface of the single chip is also bonded with the carrier board 300, and after the first tape 900 covers the chip array, it is adhered to the carrier board 300 Knot.
  • the specific material of the first adhesive tape is not limited in this embodiment.
  • the first adhesive tape may be a transparent adhesive tape.
  • the material may be the same as or different from the material of the second tape, which is not limited in this embodiment.
  • FIG. 16 it is a schematic view of the top structure of the circuit board after covering the first tape 900; since the first tape is a flexible material, the area between the two adjacent single-chip chips is also covered to form the first tape 900, that is An accommodating cavity is formed between the first tape 900 and the circuit board 800, thereby fixing and sealing the periphery of the single-chip chip, so as to prevent substances in the external environment from entering between the chip and the circuit board, causing pollution or damage to the chip surface .
  • the debonding process is related to the bonding process between the ultra-thin wafer and the carrier board described above.
  • the ultra-thin wafer and the carrier board are bonded using a light-curing adhesive.
  • the unbonding the carrier board and the multiple single-chip chips may specifically include:
  • the side of the carrier board is irradiated with laser, and the UV adhesive is unbonded between the carrier board and the chip through the first adhesive tape and the carrier board.
  • the materials of the carrier board and the first adhesive tape are both transparent materials.
  • the UV light can remove the tackiness of the UV adhesive between the carrier plate and the ultra-thin wafer through the first tape and the carrier plate, thereby removing the bonding force between the ultra-thin wafer and the first tape, which is convenient for subsequent use.
  • the chip packaged by the ultra-thin incoming packaging method provided in the embodiment of the present application It also includes the carrier board, the first tape and the circuit board.
  • the bonding force between the ultra-thin wafer of the chip and the carrier board has been removed, after transportation, when the subsequent process is required, it is only necessary to tear off the first tape, which bonds the carrier Board, separating the carrier board from the chip.
  • the first adhesive tape 900 can be directly peeled off from the circuit board.
  • the carrier board 300 is taped by the adhesion of the first adhesive tape 900 From the circuit board 800.
  • the ultra-thin incoming packaging method includes: providing ultra-thin wafers, forming a carrier board by temporarily bonding on the ultra-thin wafers, and then flipping the ultra-thin wafers after bonding the carrier board on the circuit board On the last, cover with a first layer of adhesive tape for subsequent transportation.
  • a single chip is formed in the ultra-thin wafer process, and then flipped onto the circuit board and covered with the first tape, then the carrier board and the ultra-thin wafer are unbonded, and the first tape and the circuit board are accommodated
  • the cavity is used for accommodating single-chip chips, so as to provide protection for the single-chip chips during transportation.
  • the carrier tape can be taken away from the circuit board while tearing off the first adhesive tape, so that the subsequent process can be conveniently performed. That is, the bonding carrier board reduces the risk of ultra-thin incoming materials being prone to warping or even breaking during the wafer manufacturing process. At the same time, it can protect the single chip during transportation, and subsequent use does not affect other processes. get on.
  • FIG. 18 is a schematic diagram of a packaging structure provided by an embodiment of the present application; the packaging The structure includes:
  • a circuit board 800 the circuit board 800 includes a plurality of circuit structures, and a cutting path 80 is provided between two adjacent circuit structures;
  • one chip 1 is electrically connected to one of the circuit structures;
  • a carrier board 300 located on each chip 1 facing away from the circuit board 800;
  • a first adhesive tape 900 covering the carrier plate 300 and the cutting lane 80 is bonded to the carrier plate 300 and the cutting lane 80.
  • the carrier board 300 and the chip 1 may also be unbonded or pass through.
  • the debonding process is not limited in this embodiment. If there is no debonding process between the carrier board 300 and the chip 1, a debonding process can be performed at a downstream manufacturer, and then the first tape is peeled off for subsequent processes, such as high temperature deposition, etching, photolithography, curing, electroplating, and chemical Processes such as cleaning; if the debonding process has been performed between the carrier board 300 and the chip 1, the first tape can be directly torn off at the downstream manufacturer, and then the subsequent process can be performed.
  • An embodiment of the present application provides an ultra-thin incoming packaging structure.
  • the packaging structure includes a circuit board, a plurality of chips, a carrier board, and a first adhesive tape covering a cutting path between the carrier board and adjacent chips. Since the packaging structure forms a receiving cavity between the first adhesive tape and the circuit board, multiple chips are packaged together, and there is also a carrier board to protect the chips, which can avoid warping of ultra-thin incoming materials during transportation And rupture, protect the transportation of the chip. At the same time, in the subsequent use process, directly tearing off the first adhesive tape can take away from the carrier board, thereby directly performing subsequent processes on the chips on the circuit board, and finally cutting the circuit board into a single structure along the cutting path of the circuit board.
  • the ultra-thin incoming packaging method provided by the embodiment of the present application, because in this packaging method, a single chip is formed in the ultra-thin wafer process, and then flipped onto the circuit board and covered with the first tape, then the carrier board and the ultra-thin are unbonded A receiving cavity is formed between the wafer, the first adhesive tape and the circuit board, and is used to receive a single chip, so as to provide protection for the single chip during transportation.
  • the carrier tape can be taken away from the circuit board while tearing off the first adhesive tape, so that the subsequent process can be conveniently performed. That is, the bonding carrier board reduces the risk of ultra-thin incoming materials being prone to warping or even breaking during the wafer manufacturing process. At the same time, it can protect the single chip during transportation, and subsequent use does not affect other processes. get on.

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Abstract

An ultra-thin incoming material packaging method and a packaging structure. In the packaging method, a single chip (1) is formed in the manufacturing process of an ultra-thin wafer (100), and then is inverted to a circuit board (800) and then covered with a first adhesive tape (900); and next, a bearing plate (300) and the ultra-thin wafer (100) are subjected to de-bonding, and an accommodating chamber is formed between the first adhesive tape (900) and the circuit board (800) for accommodating the single chip (1), so that a protection effect may be provided for the single chip (1) in a transportation process. During subsequent use, the bearing plate (300) may be brought away from the circuit board (800) while the first adhesive tape (900) is torn off, so that a follow-up process may be carried out conveniently. The risk that the ultra-thin incoming material is easy to warp and even break in a wafer process is reduced by bonding the bearing plate (300); and meanwhile, the single chip (1) may be protected in the transportation process, and the follow-up use does not influence other processes.

Description

超薄来料封装方法及封装结构Ultra-thin incoming packaging method and packaging structure
本公开要求在2018年11月07日提交中国专利局、申请号为201811316986.8的中国专利申请的优先权,以上申请的全部内容通过引用结合在本公开中。This disclosure requires the priority of a Chinese patent application filed with the Chinese Patent Office on November 07, 2018, with application number 201811316986.8. The entire contents of the above applications are incorporated by reference in this disclosure.
技术领域Technical field
本申请涉及半导体器件制作技术领域,例如涉及一种超薄来料封装方法及封装结构。The present application relates to the technical field of semiconductor device fabrication, for example, to an ultra-thin incoming packaging method and packaging structure.
背景技术Background technique
众所周知,封装技术其实就是一种将芯片打包的技术,这种打包对于芯片来说是必须的。因为芯片必须与外界隔离,以防止空气中的杂质对芯片电路的腐蚀而造成电气性能下降。另一方面,封装后的芯片也更便于安装和运输。因此,封装技术是集成电路产业中非常关键的一环。As we all know, packaging technology is actually a technology for packaging chips. This packaging is necessary for chips. Because the chip must be isolated from the outside world to prevent the impurities in the air from corroding the chip circuit and causing electrical performance to deteriorate. On the other hand, the packaged chips are also easier to install and transport. Therefore, packaging technology is a very critical part of the integrated circuit industry.
随着芯片集成度越来越高,封装技术目前的主流发展为三维封装技术(3D Package)。其中,三维封装的优点在于可以提高互连线的密度,降低器件外形的总体高度。由于有可能将不同类型的芯片层叠在一起,而又具有较高的互连线密度,因此三维封装技术具有很好的应用前景。With the increasing integration of chips, the current mainstream of packaging technology has developed into three-dimensional packaging technology (3D Package). Among them, the advantage of three-dimensional packaging is that it can increase the density of interconnect lines and reduce the overall height of the device shape. Because it is possible to stack different types of chips together and have a high interconnect line density, the three-dimensional packaging technology has a good application prospect.
在三维系统级封装技术中,硅通孔(TSV,Through-Silicon-Via)电极的连接路径可以缩短至只有一个芯片的厚度,所以能够实现路径最短和集成度最高的互连。通过硅通孔实现互连的系统级集成方案,能够在减少芯片面积的同时缓解互连延迟问题。In the three-dimensional system-in-package technology, the connection path of through-silicon-via (TSV, Through-Silicon-Via) electrodes can be shortened to the thickness of only one chip, so the interconnection with the shortest path and the highest integration can be realized. A system-level integration solution for interconnection through TSVs can reduce the interconnect area delay while reducing chip area.
但是,在三维封装工艺中,晶圆的厚度至少需要减薄到70um以下,而当晶圆减薄到100um以下时,晶圆就会变得极其易碎,在对晶圆的研磨过程中就可能使得晶圆的边缘发生翘曲甚至断裂。However, in the three-dimensional packaging process, the thickness of the wafer needs to be reduced to at least 70um, and when the wafer is reduced to less than 100um, the wafer will become extremely fragile. During the grinding process of the wafer The edge of the wafer may be warped or even broken.
发明内容Summary of the invention
本申请提供一种超薄来料封装方法及封装结构,以解决现有技术中晶圆在制程中容易出现翘曲甚至断裂的问题。The present application provides an ultra-thin incoming packaging method and packaging structure to solve the problem that wafers in the prior art are prone to warp or even break during the manufacturing process.
本申请提供如下技术方案:。This application provides the following technical solutions:
一种超薄来料封装方法,包括:An ultra-thin incoming packaging method, including:
提供超薄晶圆,所述超薄晶圆包括相对设置的第一表面和第二表面,所述超薄晶圆的第一表面形成有多个呈阵列排布的功能区,相邻两个功能区之间具有切割沟道,所述第一表面包括多个与所述功能区电性连接的焊垫;An ultra-thin wafer is provided. The ultra-thin wafer includes a first surface and a second surface that are disposed oppositely. The first surface of the ultra-thin wafer has a plurality of functional regions arranged in an array, two adjacent There are cutting channels between the functional areas, and the first surface includes a plurality of bonding pads electrically connected to the functional areas;
在所述超薄晶圆的第一表面键合承载板;Bonding a carrier board on the first surface of the ultra-thin wafer;
在所述超薄晶圆的第二表面上形成多个通孔,暴露出所述焊垫;Forming a plurality of through holes on the second surface of the ultra-thin wafer to expose the bonding pad;
在所述超薄晶圆的第二表面上制作多个焊接凸起,所述焊接凸起与所述焊垫电性连接;Forming a plurality of solder bumps on the second surface of the ultra-thin wafer, the solder bumps are electrically connected to the solder pads;
切割所述超薄晶圆以及承载板形成多个单粒芯片封装单元;Cutting the ultra-thin wafer and the carrier board to form a plurality of single-chip chip packaging units;
提供电路板;Provide circuit board;
将多个所述单粒芯片倒装至所述电路板上,使得所述单粒芯片上的焊接凸起与所述电路板电性连接;Flipping a plurality of the single-chip chips onto the circuit board so that the solder bumps on the single-chip chips are electrically connected to the circuit board;
覆盖第一胶带,所述第一胶带与所述承载板的顶面和所述电路板之间均粘结;Covering the first tape, the first tape is bonded to the top surface of the carrier board and the circuit board;
解键合所述承载板和多个所述单粒芯片。Unbonding the carrier board and the plurality of single-chip chips.
本申请提供一种封装结构,包括:This application provides a packaging structure, including:
电路板,所述电路板上包括多个电路结构,相邻两个电路结构之间设置有切割道;A circuit board, the circuit board includes a plurality of circuit structures, and a cutting channel is provided between two adjacent circuit structures;
多个芯片,一个芯片与一个所述电路结构电性连接;Multiple chips, one chip is electrically connected to one of the circuit structures;
位于每个所述芯片背离所述电路板的承载板;A bearing board located on each chip away from the circuit board;
覆盖所述承载板和所述切割道的第一胶带,所述第一胶带与所述承载板和所述切割道粘结。A first adhesive tape covering the carrier board and the cutting lane, the first adhesive tape being bonded to the carrier board and the cutting lane.
附图说明BRIEF DESCRIPTION
图1为本申请一实施例提供的一种超薄来料封装方法的流程示意图;1 is a schematic flowchart of an ultra-thin incoming packaging method provided by an embodiment of the present application;
图2为本申请一实施例提供的一种超薄来料的俯视结构示意图;2 is a schematic top view of an ultra-thin incoming material provided by an embodiment of the present application;
图3为图2中沿AA’线的剖面结构示意图;3 is a schematic diagram of the cross-sectional structure along line AA 'in FIG. 2;
图4为本申请一实施例提供的键合承载板后的超薄来料剖面结构示意图;4 is a schematic diagram of a cross-sectional structure of an ultra-thin incoming material after bonding a carrier plate provided by an embodiment of the present application;
图5为本申请一实施例提供的裁剪后的超薄来料结构示意图;5 is a schematic diagram of a structure of an ultra-thin incoming material after cutting according to an embodiment of the present application;
图6为本申请一实施例提供的去除第二胶带后的临时键合结构;6 is a temporary bonding structure after removing the second tape provided by an embodiment of the present application;
图7-图11为本申请一实施例提供的在超薄晶圆上进行TSV工艺制程的工艺示意图;7 to 11 are process schematic diagrams of performing a TSV process on an ultra-thin wafer provided by an embodiment of this application;
图12为本申请一实施例提供的切割后的单粒芯片结构示意图;12 is a schematic structural diagram of a single chip after cutting according to an embodiment of the present application;
图13为本申请一实施例提供的将单粒芯片倒装到电路板上的结构示意图;13 is a schematic structural diagram of flipping a single chip onto a circuit board according to an embodiment of the application;
图14为本申请一实施例提供的图13对应的俯视结构示意图;14 is a schematic diagram of a top structure corresponding to FIG. 13 provided by an embodiment of the present application;
图15为本申请一实施例提供的覆盖第一胶带后的电路板结构示意图;15 is a schematic structural diagram of a circuit board after being covered with a first adhesive tape according to an embodiment of the present application;
图16为本申请一实施例提供的覆盖第一胶带后的电路板俯视结构示意图;16 is a schematic structural diagram of a top view of a circuit board covered with a first adhesive tape provided by an embodiment of the present application;
图17为本申请一实施例提供的撕离第一胶带的结构示意图;FIG. 17 is a schematic structural diagram of a first adhesive tape provided by an embodiment of the present application;
图18为本申请一实施例提供的一种封装结构剖面结构示意图。18 is a schematic cross-sectional structure diagram of a packaging structure provided by an embodiment of the present application.
具体实施方式detailed description
下面将结合本申请实施例中的附图,对本申请实施例中的技术方案进行清楚、完整地描述。The technical solutions in the embodiments of the present application will be described clearly and completely in conjunction with the drawings in the embodiments of the present application.
请参见图1,图1为本申请实施例中提供的一种超薄来料封装方法的流程示意图,所述超薄来料封装方法包括:Please refer to FIG. 1. FIG. 1 is a schematic flowchart of an ultra-thin incoming packaging method provided in an embodiment of the present application. The ultra-thin incoming packaging method includes:
S101:提供超薄晶圆,所述超薄晶圆包括相对设置的第一表面和第二表面,所述超薄晶圆的第一表面形成有多个呈阵列排布的功能区,相邻两个功能区之间具有切割沟道,所述第一表面包括多个与所述功能区电性连接的焊垫;S101: Provide an ultra-thin wafer. The ultra-thin wafer includes a first surface and a second surface that are oppositely arranged. The first surface of the ultra-thin wafer is formed with a plurality of functional regions arranged in an array, adjacent to each other. There is a cutting channel between the two functional areas, and the first surface includes a plurality of bonding pads electrically connected to the functional areas;
请参见图2和图3,图2为本申请实施例提供的一种超薄来料的俯视结构示意图,图3为图2中沿AA’线的剖面结构示意图,需要说明的是,图3中仅示例了两个功能区,并不代表超薄晶圆上仅设置有两个功能区;如图3中所示,所述超薄晶圆100包括相对设置的第一表面101和第二表面102;在超薄晶圆100的第一表面101上形成有多个呈阵列排布的功能区11,相邻两个功能区11之间具有切割沟道10,切割沟道10用于后续将晶圆切割形成多个芯片。第一表面101上还包括多个与功能区11电性链接的焊垫12。焊垫12用于将功能区与外部电路电性连接在一起。Please refer to FIG. 2 and FIG. 3, FIG. 2 is a schematic structural view of a top view of an ultra-thin incoming material provided by an embodiment of the present application, and FIG. 3 is a schematic cross-sectional structure diagram taken along line AA 'in FIG. Only two functional areas are exemplified in FIG. 3, which does not mean that only two functional areas are provided on the ultra-thin wafer; as shown in FIG. 3, the ultra-thin wafer 100 includes a first surface 101 and a second surface that are oppositely arranged Surface 102; a plurality of functional regions 11 arranged in an array are formed on the first surface 101 of the ultra-thin wafer 100, and a cutting channel 10 is provided between two adjacent functional regions 11, and the cutting channel 10 is used for subsequent The wafer is cut into multiple chips. The first surface 101 further includes a plurality of bonding pads 12 electrically connected to the functional area 11. The pad 12 is used to electrically connect the functional area and the external circuit.
本申请实施例中不限定超薄晶圆的具体结构,由于超薄晶圆100的厚度较小,避免在运输过程中出现弯曲和破裂,在本申请的一个实施例中,所述提供超薄晶圆,具体可以包括:提供带有第二胶带200的超薄晶圆,所述第二胶带200粘结所述超薄晶圆100的第二表面102,且所述第二胶带的边缘还设置有金属环201。请参见图3,超薄晶圆100的第二表面102粘结在第二胶带200的表面,第二胶带200的边缘设置有金属环201。本实施例中所述的带有第二胶带200和金属环201的超薄晶圆100即为超薄来料,其中,第二胶带200和金属环201的存在能够为超薄晶圆100提供保护,避免在运输过程中晶圆100受到较大的外力而造成破裂。The specific structure of the ultra-thin wafer is not limited in the embodiments of the present application. Since the thickness of the ultra-thin wafer 100 is small, bending and cracking during transportation are avoided. In an embodiment of the present application, the ultra-thin wafer The wafer may specifically include: providing an ultra-thin wafer with a second tape 200, the second tape 200 adheres to the second surface 102 of the ultra-thin wafer 100, and the edge of the second tape Provided with a metal ring 201. Referring to FIG. 3, the second surface 102 of the ultra-thin wafer 100 is adhered to the surface of the second tape 200, and the edge of the second tape 200 is provided with a metal ring 201. The ultra-thin wafer 100 with the second tape 200 and the metal ring 201 described in this embodiment is an ultra-thin incoming material, wherein the presence of the second tape 200 and the metal ring 201 can provide the ultra-thin wafer 100 Protection to prevent the wafer 100 from being broken due to large external forces during transportation.
由于超薄来料还包括第二胶带200和金属环201,而超薄晶圆为单独的一个晶圆,为了避免超薄晶圆在后续制作工艺中造成翘曲或破裂,本实施例中还包括如下步骤S102。Since the ultra-thin incoming material also includes the second tape 200 and the metal ring 201, and the ultra-thin wafer is a single wafer, in order to avoid the warping or cracking of the ultra-thin wafer in the subsequent manufacturing process, this embodiment also It includes the following step S102.
S102:在所述超薄晶圆的第一表面键合承载板;S102: bonding a carrier board on the first surface of the ultra-thin wafer;
需要说明的是,如上面所述,超薄来料实际上是超薄晶圆和第二胶带以及金属环组成的结构。因此,在提供带有第二胶带的超薄晶圆之后,在所述超薄晶圆的第一表面键合承载板之前,还包括将金属环和第二胶带去除的步骤,具体包括:It should be noted that, as described above, the ultra-thin incoming material is actually a structure composed of an ultra-thin wafer, a second tape, and a metal ring. Therefore, after providing the ultra-thin wafer with the second tape, and before bonding the carrier board on the first surface of the ultra-thin wafer, the step of removing the metal ring and the second tape is further included, specifically including:
在所述带有第二胶带的超薄晶圆的第一表面临时结合所述承载板;Temporarily bonding the carrier board on the first surface of the ultra-thin wafer with the second tape;
以所述超薄晶圆的边缘为裁剪线,将所述第二胶带、超薄晶圆和承载板裁剪下来得到临时键合结构,去除所述金属环和多余的第二胶带。Using the edge of the ultra-thin wafer as a cutting line, the second adhesive tape, the ultra-thin wafer and the carrier board are cut out to obtain a temporary bonding structure, and the metal ring and the excess second adhesive tape are removed.
请参见图4,在带有第二胶带的超薄晶圆100的第一表面101临时结合承载板300,需要说明的是,本实施例中不限定承载板300的具体材质,只要承载板300能够在后续工艺中对超薄晶圆100提供支撑应力,避免超薄晶圆100破裂即可。承载板300可以是透明的,即所述承载板为透明承载板。也可以是不透明的,本实施例中对此不作限定。为了方便后续工艺,本实施例中,承载板300可以为透明材质,更加可选的,由玻璃材质制作形成。Referring to FIG. 4, the carrier board 300 is temporarily bonded to the first surface 101 of the ultra-thin wafer 100 with the second tape. It should be noted that the specific material of the carrier board 300 is not limited in this embodiment, as long as the carrier board 300 It is sufficient to provide supporting stress to the ultra-thin wafer 100 in the subsequent process to avoid the ultra-thin wafer 100 from cracking. The carrier board 300 may be transparent, that is, the carrier board is a transparent carrier board. It may also be opaque, which is not limited in this embodiment. In order to facilitate the subsequent process, in this embodiment, the carrier board 300 may be made of a transparent material, more optionally, made of glass material.
另外,此处所述的临时结合,并不是真正的键合工艺,而仅仅是将承载板300与超薄晶圆100的第一表面101进行结合,两者之间具有一定的粘附作用,但是并不能用于超薄晶圆的其他工艺使用。本申请实施例中不限定将带有第二胶带的超薄晶圆的第一表面临时结合所述承载板的具体工艺,在本申请的一个实施例中,具体可以为:In addition, the temporary bonding described here is not a real bonding process, but only the bonding of the carrier board 300 and the first surface 101 of the ultra-thin wafer 100, and there is a certain adhesion between the two. However, it cannot be used in other processes of ultra-thin wafers. The embodiment of the present application does not limit the specific process of temporarily bonding the first surface of the ultra-thin wafer with the second tape to the carrier board. In an embodiment of the present application, the specific process may be:
在所述带有第二胶带的超薄晶圆的第一表面涂覆光固化胶黏剂;Applying a light-curing adhesive to the first surface of the ultra-thin wafer with the second tape;
将所述承载板通过所述光固化胶黏剂粘接在所述带有第二胶带的超薄晶圆的第一表面。The carrier board is bonded to the first surface of the ultra-thin wafer with the second adhesive tape through the photo-curable adhesive.
由于后续在完成超薄晶圆的相应工艺后,还需要将承载板与超薄晶圆第一表面进行解键合,为了方便后续解键合,本实施例中,所述光固化胶黏剂可以为UV胶黏剂。Since the corresponding process of the ultra-thin wafer is subsequently completed, the carrier plate and the first surface of the ultra-thin wafer need to be unbonded. In order to facilitate subsequent debonding, in this embodiment, the photocurable adhesive may be UV Adhesive.
在承载板与超薄晶圆的第一表面暂时结合后,请参见图5,以超薄晶圆100的边缘为裁剪线,去除金属环201和多余的第二胶带200。裁剪得到超薄晶圆100、以及与超薄晶圆100尺寸大小以及形状相同的第二胶带200和承载板300,本实施 例中为了方便后续描述,将该结构称为临时键合结构。After the carrier plate is temporarily combined with the first surface of the ultra-thin wafer, please refer to FIG. 5, the edge of the ultra-thin wafer 100 is used as a cutting line to remove the metal ring 201 and the excess second adhesive tape 200. The ultra-thin wafer 100 and the second tape 200 and the carrier board 300 having the same size and shape as the ultra-thin wafer 100 are obtained by cutting. In this embodiment, for convenience of subsequent description, this structure is called a temporary bonding structure.
最后,得到临时键合结构后,将超薄晶圆和承载板之间实现正式键合后,并去掉超薄晶圆第二表面的第二胶带,得到承载板与超薄晶圆的第一表面与承载板键合的结构。也即在所述超薄晶圆的第一表面键合承载板,具体包括:Finally, after obtaining the temporary bonding structure, after officially bonding the ultra-thin wafer and the carrier board, and removing the second tape on the second surface of the ultra-thin wafer, the first carrier board and the ultra-thin wafer are obtained The structure where the surface is bonded to the bearing plate. That is, bonding the carrier board to the first surface of the ultra-thin wafer specifically includes:
对所述临时键合结构中的超薄晶圆和承载板实现键合;Bonding the ultra-thin wafer and the carrier board in the temporary bonding structure;
去除所述第二胶带。Remove the second tape.
在超薄晶圆100的第一表面101和承载板300进行真正的键合后,可以将第二胶带去除,后续在超薄晶圆上进行刻蚀或其他工艺时,承载板300能够为超薄晶圆100提供必要的应力支撑,避免超薄晶圆在高温或刻蚀工艺中出现翘曲或开裂。After the first surface 101 of the ultra-thin wafer 100 and the carrier plate 300 are truly bonded, the second tape can be removed, and when the subsequent etching or other processes are performed on the ultra-thin wafer, the carrier plate 300 can be ultra-thin The thin wafer 100 provides the necessary stress support to avoid warping or cracking of the ultra-thin wafer during high temperature or etching processes.
本实施例中不限定临时键合结构中超薄晶圆与承载板实现真正键合的具体工艺,在本申请的一个实施例中,在承载板为透明承载板,且光固化胶黏剂为UV胶黏剂的情况下,超薄晶圆与承载板的键合工艺具体可以包括:In this embodiment, the specific process of real bonding between the ultra-thin wafer and the carrier board in the temporary bonding structure is not limited. In one embodiment of the present application, the carrier board is a transparent carrier board, and the photocurable adhesive is In the case of UV adhesives, the bonding process of ultra-thin wafers and carrier boards can specifically include:
采用紫外光照射所述临时键合结构的承载板侧;Using ultraviolet light to irradiate the bearing plate side of the temporary bonding structure;
将所述UV胶黏剂固化,使得所述临时键合结构中的超薄晶圆的第一表面和所述承载板实现键合。The UV adhesive is cured so that the first surface of the ultra-thin wafer in the temporary bonding structure is bonded to the carrier board.
请参见图6,图6为将超薄晶圆的第一表面与承载板键合后的剖面结构示意图;超薄晶圆100的第一表面101上包括多个功能区11,相邻两个功能区11之间具有切割沟道10,还包括多个与功能区11电性连接的焊垫12,本实施例中以图2中的PP’线剖面图为例进行说明。Please refer to FIG. 6. FIG. 6 is a schematic cross-sectional structural view of the first surface of the ultra-thin wafer bonded to the carrier plate; the first surface 101 of the ultra-thin wafer 100 includes a plurality of functional areas 11, two adjacent There are cutting channels 10 between the functional areas 11 and a plurality of bonding pads 12 electrically connected to the functional areas 11. In this embodiment, the PP ′ cross-sectional view in FIG. 2 is used as an example for description.
S103:在所述超薄晶圆的第二表面上形成多个通孔,暴露出所述焊垫;S103: forming a plurality of through holes on the second surface of the ultra-thin wafer to expose the bonding pad;
在将超薄晶圆100与承载板300键合后,由于承载板300对超薄晶圆100具有支撑和保护作用,可以对超薄晶圆100进行相应打孔、刻蚀等常规的晶圆制程。After the ultra-thin wafer 100 is bonded to the carrier plate 300, since the carrier plate 300 has a support and protection effect on the ultra-thin wafer 100, the ultra-thin wafer 100 can be appropriately punched, etched, etc. Process.
本实施例中不限定晶圆制程的具体工艺,本实施例中以在晶圆上进行TSV(Through Silicon Vias,穿过硅片通道)工艺为例进行说明。请参见图7,图7为在超薄晶圆100上形成暴露焊垫的通孔的工艺。The specific process of the wafer manufacturing process is not limited in this embodiment. In this embodiment, the TSV (Through Silicon Vias) process is performed on the wafer as an example for description. Please refer to FIG. 7. FIG. 7 is a process of forming a through hole on the ultra-thin wafer 100 to expose the pad.
需要说明的是,本实施例中不限定在超薄晶圆100的第二表面102上形成多个通孔103,暴露出焊垫12的具体工艺,在本申请的一个实施例中,可以具体包括:It should be noted that the specific process of forming a plurality of through holes 103 on the second surface 102 of the ultra-thin wafer 100 to expose the bonding pad 12 is not limited in this embodiment. In an embodiment of the present application, it may be specific include:
对所述超薄晶圆的第二表面上对应所述焊垫的位置进行刻蚀处理,暴露出所述焊垫12。An etching treatment is performed on the position of the second surface of the ultra-thin wafer corresponding to the bonding pad to expose the bonding pad 12.
然后,在超薄晶圆形成多个通孔的第二表面形成绝缘层,请参见图8,绝缘 层400覆盖所述超薄晶圆100的第二表面102且所述绝缘层400覆盖所述通孔103的侧壁,并暴露所述通孔103的底面;焊垫12位于通孔103的底面,从而暴露在外面。Then, an insulating layer is formed on the second surface of the ultra-thin wafer with a plurality of through holes. Referring to FIG. 8, an insulating layer 400 covers the second surface 102 of the ultra-thin wafer 100 and the insulating layer 400 covers the The side wall of the through hole 103 exposes the bottom surface of the through hole 103; the pad 12 is located on the bottom surface of the through hole 103 so as to be exposed to the outside.
请参见图9,在所述绝缘层400上形成再布线层500,所述再布线层500在所述通孔103的底部与所述焊垫12连接;从而能够将焊垫12电性连接至超薄晶圆100的第二表面。Referring to FIG. 9, a re-wiring layer 500 is formed on the insulating layer 400, and the re-wiring layer 500 is connected to the pad 12 at the bottom of the through hole 103; thereby, the pad 12 can be electrically connected to The second surface of the ultra-thin wafer 100.
请参见图10,形成阻焊层600,所述阻焊层600覆盖所述再布线层500和所述绝缘层400;阻焊层600用于对再布线层500进行保护,避免再布线层500与外界的其他电性元件之间出现短路,造成器件失效。10, a solder resist layer 600 is formed, and the solder resist layer 600 covers the re-wiring layer 500 and the insulating layer 400; the solder resist layer 600 is used to protect the re-wiring layer 500 to avoid the re-wiring layer 500 There is a short circuit with other electrical components in the outside world, causing the device to fail.
请继续参见图10,在所述阻焊层600上形成开口601。开口601暴露出部分再布线层500,用于后续形成焊接凸起。Please continue to refer to FIG. 10, an opening 601 is formed on the solder resist layer 600. The opening 601 exposes part of the redistribution layer 500 for subsequent formation of solder bumps.
S104:在所述超薄晶圆的第二表面上制作多个焊接凸起,所述焊接凸起与所述焊垫电性连接;S104: Making a plurality of solder bumps on the second surface of the ultra-thin wafer, the solder bumps are electrically connected to the solder pads;
需要说明的是,所述多个焊接凸起用于将超薄晶圆100第一表面101与功能区11电性连接的焊垫12电性连接至超薄晶圆100的第二表面102,再用于与外部电路进行电性连接,本实施例中采用TSV工艺形成,因此,请参见图11,本实施例中在所述超薄晶圆的第二表面上制作多个焊接凸起700,所述焊接凸起700与所述焊垫12电性连接,具体可以包括:It should be noted that the plurality of solder bumps are used to electrically connect the pad 12 electrically connecting the first surface 101 of the ultra-thin wafer 100 and the functional area 11 to the second surface 102 of the ultra-thin wafer 100, and then It is used for electrical connection with external circuits. In this embodiment, it is formed by the TSV process. Therefore, referring to FIG. 11, in this embodiment, a plurality of solder bumps 700 are formed on the second surface of the ultra-thin wafer. The solder bump 700 is electrically connected to the solder pad 12 and may specifically include:
在所述开口601内形成焊接凸起700;Forming a welding protrusion 700 in the opening 601;
所述焊接凸起700与所述再布线层500电性连接,并通过所述再布线层500与所述焊垫12电性连接。The solder bump 700 is electrically connected to the rewiring layer 500, and is electrically connected to the pad 12 through the rewiring layer 500.
S105:切割所述超薄晶圆以及承载板形成多个单粒芯片封装单元;S105: cutting the ultra-thin wafer and the carrier board to form a plurality of single-chip chip packaging units;
请参见图12,沿超薄晶圆100上的切割沟道10,切割所述超薄晶圆100以及承载板300形成多个单粒芯片封装单元。本实施例中不限定具体的切割工艺,可以采用刀划工艺,也可以采用刀划工艺结合刻蚀工艺层完成切割。本实施例中,可以采用刀划工艺进行切割,刀划工艺可以一次切割完成,也可以采用多次切割,每次切割一定深度,最终将超薄晶圆和承载板均切割透即可。本实施例中对此不作限定。Referring to FIG. 12, along the cutting trench 10 on the ultra-thin wafer 100, the ultra-thin wafer 100 and the carrier board 300 are cut to form a plurality of single-chip chip packaging units. In this embodiment, the specific cutting process is not limited, and the cutting process may be used, or the cutting process and the etching process layer may be used to complete the cutting. In this embodiment, the cutting process can be performed by using a knife process. The knife process can be completed in one cut, or multiple cuts, each cutting to a certain depth, and finally the ultra-thin wafer and the carrier board can be cut through. This is not limited in this embodiment.
S106:提供电路板;S106: Provide a circuit board;
本实施例中不限定电路板的具体结构,所述电路板用于将单粒芯片封装单元与外部电路电性连接起来,本实施例中不限定电路板的具体材质,电路板可 以是PCB(Printed Circuit Board,印制电路)板,也可以是FPC(Flexible Printed Circuit,可挠性印刷电路)板,在本申请的一个实施例中,优选为PCB板。The specific structure of the circuit board is not limited in this embodiment, and the circuit board is used to electrically connect the single-chip package unit with an external circuit. The specific material of the circuit board is not limited in this embodiment, and the circuit board may be a PCB ( The Printed Circuit Board (printed circuit) board may also be an FPC (Flexible Printed Circuit) board. In one embodiment of the present application, it is preferably a PCB board.
S107:将多个所述单粒芯片倒装至所述电路板上,使得所述芯片上的焊接凸起与所述电路板电性连接;S107: flip a plurality of the single-chip chips onto the circuit board, so that the solder bumps on the chip are electrically connected to the circuit board;
请参见图13,将多个单粒芯片1倒装至电路板800上,具体通过将单粒芯片上的焊接凸起700与电路板800上的电路通过焊接或导电胶电性连接在一起,从而将单粒芯片上的功能区与外部其他电路电性连接。如图14所示,为多个单粒芯片倒装至电路板上后的俯视结构示意图。Referring to FIG. 13, a plurality of single-chip chips 1 are flip-chip mounted on a circuit board 800 by specifically connecting the solder bumps 700 on the single-chip chips and the circuits on the circuit board 800 by soldering or conductive glue, Thus, the functional area on the single chip is electrically connected with other external circuits. As shown in FIG. 14, it is a schematic plan view of a plurality of single-chip chips flip-chip mounted on a circuit board.
S108:覆盖第一胶带,所述第一胶带与所述承载板的顶面和所述电路板之间均粘结;S108: covering a first adhesive tape, the first adhesive tape is bonded to the top surface of the carrier board and the circuit board;
在多个单粒芯片均倒装至电路板上后,在承载板的顶面覆盖第一胶带。请参见图15,也即在单粒芯片倒装至电路板800上后,单粒芯片的第一表面上还键合有承载板300,第一胶带900覆盖芯片阵列后,与承载板300粘结。After all the single-chip chips are flip-chip mounted on the circuit board, the first adhesive tape is covered on the top surface of the carrier board. Please refer to FIG. 15, that is, after the single chip is flip-chip mounted on the circuit board 800, the first surface of the single chip is also bonded with the carrier board 300, and after the first tape 900 covers the chip array, it is adhered to the carrier board 300 Knot.
需要说明的是,本实施例中不限定第一胶带的具体材质,为了方便后续采用光照对承载板300和超薄晶圆100的解键合,本实施例中,第一胶带可以为透明胶带。其材质可以与第二胶带的材质相同,也可以不相同,本实施例中对此不作限定。It should be noted that the specific material of the first adhesive tape is not limited in this embodiment. In order to facilitate subsequent debonding of the carrier board 300 and the ultra-thin wafer 100 using light, in this embodiment, the first adhesive tape may be a transparent adhesive tape. The material may be the same as or different from the material of the second tape, which is not limited in this embodiment.
如图16,为覆盖第一胶带900后的电路板俯视结构示意图;由于第一胶带为柔性的材质,在相邻的两个单粒芯片之间的区域也覆盖形成第一胶带900,也即第一胶带900和电路板800之间形成一个容纳腔,从而将单粒芯片的四周均固定并封住,避免外界环境中的物质进入到芯片与电路板之间,对芯片表面造成污染或损坏。As shown in FIG. 16, it is a schematic view of the top structure of the circuit board after covering the first tape 900; since the first tape is a flexible material, the area between the two adjacent single-chip chips is also covered to form the first tape 900, that is An accommodating cavity is formed between the first tape 900 and the circuit board 800, thereby fixing and sealing the periphery of the single-chip chip, so as to prevent substances in the external environment from entering between the chip and the circuit board, causing pollution or damage to the chip surface .
S109:解键合所述承载板和多个所述单粒芯片。S109: Unbond the carrier board and the multiple single-chip chips.
需要说明的是,解键合工艺与上面所述的超薄晶圆与承载板之间的键合工艺相关,本实施例中超薄晶圆和承载板之间采用光固化粘合剂进行键合,对应的,所述解键合所述承载板和多个所述单粒芯片,具体可以包括:It should be noted that the debonding process is related to the bonding process between the ultra-thin wafer and the carrier board described above. In this embodiment, the ultra-thin wafer and the carrier board are bonded using a light-curing adhesive. Correspondingly, the unbonding the carrier board and the multiple single-chip chips may specifically include:
采用激光照射所述承载板侧,激光透过所述第一胶带和所述承载板将所述UV胶黏剂,解键合所述承载板与所述芯片。The side of the carrier board is irradiated with laser, and the UV adhesive is unbonded between the carrier board and the chip through the first adhesive tape and the carrier board.
也即,由于承载板和第一胶带的材质均为透明材质。UV光能够通过第一胶带和承载板将承载板和超薄晶圆之间的UV胶黏剂去除粘性,从而将超薄晶圆和第一胶带之间的键合力去除,便于后续使用。That is, since the materials of the carrier board and the first adhesive tape are both transparent materials. The UV light can remove the tackiness of the UV adhesive between the carrier plate and the ultra-thin wafer through the first tape and the carrier plate, thereby removing the bonding force between the ultra-thin wafer and the first tape, which is convenient for subsequent use.
需要说明的是,本实施例中在超薄晶圆的TSV晶圆制程之后,需要外部运输至后续厂家进行后续的工艺,采用本申请实施例中提供的超薄来料封装方法封装后的芯片还包括承载板、第一胶带和电路板。但是由于芯片的超薄晶圆与承载板之间的键合力已经去除,在运输之后,需要进行后续工艺时,只需要,撕离所述第一胶带,所述第一胶带粘结所述承载板,将所述承载板与所述芯片分离。It should be noted that in this embodiment, after the TSV wafer manufacturing process of the ultra-thin wafer, it needs to be externally transported to a subsequent manufacturer for subsequent processes, and the chip packaged by the ultra-thin incoming packaging method provided in the embodiment of the present application It also includes the carrier board, the first tape and the circuit board. However, since the bonding force between the ultra-thin wafer of the chip and the carrier board has been removed, after transportation, when the subsequent process is required, it is only necessary to tear off the first tape, which bonds the carrier Board, separating the carrier board from the chip.
请参见图17,直接将第一胶带900从电路板上撕离即可。在第一胶带900撕离的过程中,由于承载板300与电路板800上电性连接的芯片之间的键合力已经去除,承载板300在第一胶带900的粘附性作用下,被带离电路板800。Referring to FIG. 17, the first adhesive tape 900 can be directly peeled off from the circuit board. In the process of tearing off the first adhesive tape 900, since the bonding force between the chip electrically connected to the carrier board 300 and the circuit board 800 has been removed, the carrier board 300 is taped by the adhesion of the first adhesive tape 900 From the circuit board 800.
本申请提供的超薄来料封装方法,包括:提供超薄晶圆,在超薄晶圆上通过临时键合形成承载板,然后将键合承载板后的超薄晶圆倒装在电路板上,最后再覆盖一层第一胶带,用于后续运输。由于该封装方法中在超薄晶圆制程工艺形成单粒芯片,然后倒装到电路板再覆盖第一胶带后,再解键合承载板和超薄晶圆,第一胶带和电路板之间形容纳腔,用于容纳单粒芯片,从而能够为运输过程中的单粒芯片提供保护作用。而后续使用时,撕离第一胶带的同时能够将承载板带离电路板,使得进行后续工艺时能够方便进行。也即通过键合承载板降低了出现超薄来料在晶圆制程中容易出现翘曲甚至断裂的风险,同时还能够在运输过程中对单粒芯片进行保护,而且后续使用不影响其他工艺的进行。The ultra-thin incoming packaging method provided by the present application includes: providing ultra-thin wafers, forming a carrier board by temporarily bonding on the ultra-thin wafers, and then flipping the ultra-thin wafers after bonding the carrier board on the circuit board On the last, cover with a first layer of adhesive tape for subsequent transportation. In this packaging method, a single chip is formed in the ultra-thin wafer process, and then flipped onto the circuit board and covered with the first tape, then the carrier board and the ultra-thin wafer are unbonded, and the first tape and the circuit board are accommodated The cavity is used for accommodating single-chip chips, so as to provide protection for the single-chip chips during transportation. In subsequent use, the carrier tape can be taken away from the circuit board while tearing off the first adhesive tape, so that the subsequent process can be conveniently performed. That is, the bonding carrier board reduces the risk of ultra-thin incoming materials being prone to warping or even breaking during the wafer manufacturing process. At the same time, it can protect the single chip during transportation, and subsequent use does not affect other processes. get on.
本申请实施例还提供一种封装结构,采用上面实施例中所述的超薄来料封装方法形成,请参见图18,图18为本申请实施例提供的一种封装结构示意图;所述封装结构包括:An embodiment of the present application also provides a packaging structure, which is formed using the ultra-thin incoming packaging method described in the above embodiment, please refer to FIG. 18, which is a schematic diagram of a packaging structure provided by an embodiment of the present application; the packaging The structure includes:
电路板800,所述电路板800上包括多个电路结构,相邻两个电路结构之间设置有切割道80;A circuit board 800, the circuit board 800 includes a plurality of circuit structures, and a cutting path 80 is provided between two adjacent circuit structures;
多个芯片1,一个芯片1与一个所述电路结构电性连接; Multiple chips 1, one chip 1 is electrically connected to one of the circuit structures;
位于每个所述芯片1背离所述电路板800的承载板300;A carrier board 300 located on each chip 1 facing away from the circuit board 800;
覆盖所述承载板300和所述切割道80的第一胶带900,所述第一胶带900与所述承载板300和所述切割道80粘结。A first adhesive tape 900 covering the carrier plate 300 and the cutting lane 80 is bonded to the carrier plate 300 and the cutting lane 80.
需要说明的是,本实施例中提供的封装结构中,不限定承载板300和芯片1之间的键合力是否已经被去除,也即承载板300和芯片1还可以未经解键合,也可以经过解键合处理,本实施例中对此不作限定。若承载板300和芯片1之间未经解键合处理,可以在下游厂商处再进行一次解键合工艺,然后再撕离第一胶 带进行后续工艺,例如高温沉积、蚀刻、光刻、固化、电镀及化学清洗等工艺;若承载板300与芯片1之间已经经过解键合处理,可以在下游厂商处直接撕离第一胶带,然后进行后续工艺。It should be noted that, in the packaging structure provided in this embodiment, it is not limited whether the bonding force between the carrier board 300 and the chip 1 has been removed, that is, the carrier board 300 and the chip 1 may also be unbonded or pass through. The debonding process is not limited in this embodiment. If there is no debonding process between the carrier board 300 and the chip 1, a debonding process can be performed at a downstream manufacturer, and then the first tape is peeled off for subsequent processes, such as high temperature deposition, etching, photolithography, curing, electroplating, and chemical Processes such as cleaning; if the debonding process has been performed between the carrier board 300 and the chip 1, the first tape can be directly torn off at the downstream manufacturer, and then the subsequent process can be performed.
本申请实施例中提供一种超薄来料封装结构,所述封装结构包括电路板、多个芯片、承载板和覆盖承载板及相邻芯片之间的切割道的第一胶带。由于所述封装结构通过第一胶带与电路板之间形成容纳腔,将多个芯片封装在一起,而且还有承载板对芯片进行保护,在运输过程中,能够避免超薄来料的翘曲和破裂,对芯片的运输起到保护作用。同时,在后续使用过程中,直接撕离第一胶带能够带离承载板,从而直接对电路板上的芯片进行后续工艺,最后再沿电路板的切割道将电路板切割成单个结构即可。An embodiment of the present application provides an ultra-thin incoming packaging structure. The packaging structure includes a circuit board, a plurality of chips, a carrier board, and a first adhesive tape covering a cutting path between the carrier board and adjacent chips. Since the packaging structure forms a receiving cavity between the first adhesive tape and the circuit board, multiple chips are packaged together, and there is also a carrier board to protect the chips, which can avoid warping of ultra-thin incoming materials during transportation And rupture, protect the transportation of the chip. At the same time, in the subsequent use process, directly tearing off the first adhesive tape can take away from the carrier board, thereby directly performing subsequent processes on the chips on the circuit board, and finally cutting the circuit board into a single structure along the cutting path of the circuit board.
本申请实施例提供的超薄来料封装方法,由于该封装方法中在超薄晶圆制程工艺形成单粒芯片,然后倒装到电路板再覆盖第一胶带后,再解键合承载板和超薄晶圆,第一胶带和电路板之间形容纳腔,用于容纳单粒芯片,从而能够为运输过程中的单粒芯片提供保护作用。而后续使用时,撕离第一胶带的同时能够将承载板带离电路板,使得进行后续工艺时能够方便进行。也即通过键合承载板降低了出现超薄来料在晶圆制程中容易出现翘曲甚至断裂的风险,同时还能够在运输过程中对单粒芯片进行保护,而且后续使用不影响其他工艺的进行。The ultra-thin incoming packaging method provided by the embodiment of the present application, because in this packaging method, a single chip is formed in the ultra-thin wafer process, and then flipped onto the circuit board and covered with the first tape, then the carrier board and the ultra-thin are unbonded A receiving cavity is formed between the wafer, the first adhesive tape and the circuit board, and is used to receive a single chip, so as to provide protection for the single chip during transportation. In subsequent use, the carrier tape can be taken away from the circuit board while tearing off the first adhesive tape, so that the subsequent process can be conveniently performed. That is, the bonding carrier board reduces the risk of ultra-thin incoming materials being prone to warping or even breaking during the wafer manufacturing process. At the same time, it can protect the single chip during transportation, and subsequent use does not affect other processes. get on.
需要说明的是,本说明书中的各个实施例均采用递进的方式描述,每个实施例重点说明的都是与其他实施例的不同之处,各个实施例之间相同相似的部分互相参见即可。It should be noted that the embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same and similar parts between the embodiments refer to each other. can.
还需要说明的是,在本文中,诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来,而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且,术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含,从而使得包括一系列要素的物品或者设备不仅包括那些要素,而且还包括没有明确列出的其他要素,或者是还包括为这种物品或者设备所固有的要素。在没有更多限制的情况下,由语句“包括一个……”限定的要素,并不排除在包括上述要素的物品或者设备中还存在另外的相同要素。It should also be noted that in this article, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply these entities or operations There is any such actual relationship or order. Moreover, the terms "including", "comprising" or any other variant thereof are intended to cover non-exclusive inclusions, such that an article or device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, Or it also includes elements inherent to such articles or equipment. Without more restrictions, the element defined by the sentence "include one ..." does not exclude that there are other identical elements in the article or device that includes the above elements.

Claims (14)

  1. 一种超薄来料封装方法,包括:An ultra-thin incoming packaging method, including:
    提供超薄晶圆,所述超薄晶圆包括相对设置的第一表面和第二表面,所述超薄晶圆的第一表面形成有多个呈阵列排布的功能区,相邻两个功能区之间具有切割沟道,所述第一表面包括多个与所述功能区电性连接的焊垫;An ultra-thin wafer is provided. The ultra-thin wafer includes a first surface and a second surface that are disposed oppositely. The first surface of the ultra-thin wafer has a plurality of functional regions arranged in an array, two adjacent There are cutting channels between the functional areas, and the first surface includes a plurality of bonding pads electrically connected to the functional areas;
    在所述超薄晶圆的第一表面键合承载板;Bonding a carrier board on the first surface of the ultra-thin wafer;
    在所述超薄晶圆的第二表面上形成多个通孔,暴露出所述焊垫;Forming a plurality of through holes on the second surface of the ultra-thin wafer to expose the bonding pad;
    在所述超薄晶圆的第二表面上制作多个焊接凸起,所述焊接凸起与所述焊垫电性连接;Forming a plurality of solder bumps on the second surface of the ultra-thin wafer, the solder bumps are electrically connected to the solder pads;
    切割所述超薄晶圆以及承载板形成多个单粒芯片封装单元;Cutting the ultra-thin wafer and the carrier board to form a plurality of single-chip chip packaging units;
    提供电路板;Provide circuit board;
    将多个所述单粒芯片倒装至所述电路板上,使得所述单粒芯片上的焊接凸起与所述电路板电性连接;Flipping a plurality of the single-chip chips onto the circuit board so that the solder bumps on the single-chip chips are electrically connected to the circuit board;
    覆盖第一胶带,所述第一胶带与所述承载板的顶面和所述电路板之间均粘结;Covering the first tape, the first tape is bonded to the top surface of the carrier board and the circuit board;
    解键合所述承载板和多个所述单粒芯片。Unbonding the carrier board and the plurality of single-chip chips.
  2. 根据权利要求1所述的超薄来料封装方法,其中,所述提供超薄晶圆,具体包括:The ultra-thin incoming packaging method according to claim 1, wherein the providing of the ultra-thin wafer specifically includes:
    提供带有第二胶带的超薄晶圆,所述第二胶带粘结所述超薄晶圆的第二表面,且所述第二胶带的边缘还设置有金属环。An ultra-thin wafer with a second tape is provided, the second tape adheres to the second surface of the ultra-thin wafer, and a metal ring is further provided on the edge of the second tape.
  3. 根据权利要求2所述的超薄来料封装方法,其特征在于,在提供带有第二胶带的超薄晶圆之后,在所述超薄晶圆的第一表面键合承载板之前,还包括:The ultra-thin incoming packaging method according to claim 2, wherein after providing the ultra-thin wafer with the second tape, and before bonding the carrier board on the first surface of the ultra-thin wafer, include:
    在所述带有第二胶带的超薄晶圆的第一表面临时结合所述承载板;Temporarily bonding the carrier board on the first surface of the ultra-thin wafer with the second tape;
    以所述超薄晶圆的边缘为裁剪线,将所述第二胶带、超薄晶圆和承载板裁剪下来得到临时键合结构,去除所述金属环和多余的第二胶带。Using the edge of the ultra-thin wafer as a cutting line, the second adhesive tape, the ultra-thin wafer and the carrier board are cut out to obtain a temporary bonding structure, and the metal ring and the excess second adhesive tape are removed.
  4. 根据权利要求3所述的超薄来料封装方法,其特征在于,所述在所述超薄晶圆的第一表面键合承载板,具体包括:The ultra-thin incoming packaging method according to claim 3, wherein the bonding of the carrier board on the first surface of the ultra-thin wafer specifically includes:
    对所述临时键合结构中的超薄晶圆和承载板实现键合;Bonding the ultra-thin wafer and the carrier board in the temporary bonding structure;
    去除所述第二胶带。Remove the second tape.
  5. 根据权利要求4所述的超薄来料封装方法,其特征在于,所述承载板为透明承载板。The ultra-thin incoming packaging method according to claim 4, wherein the carrier board is a transparent carrier board.
  6. 根据权利要求5所述的超薄来料封装方法,其特征在于,所述在所述带有第二胶带的超薄晶圆的第一表面临时结合所述承载板,具体为:The ultra-thin incoming packaging method according to claim 5, wherein the temporarily bonding the carrier board to the first surface of the ultra-thin wafer with the second adhesive tape is specifically:
    在所述带有第二胶带的超薄晶圆的第一表面涂覆光固化胶黏剂;Applying a light-curing adhesive to the first surface of the ultra-thin wafer with the second tape;
    将所述承载板通过所述光固化胶黏剂粘接在所述带有第二胶带的超薄晶圆的第一表面。The carrier board is bonded to the first surface of the ultra-thin wafer with the second adhesive tape through the photo-curable adhesive.
  7. 根据权利要求6所述的超薄来料封装方法,其特征在于,所述光固化胶黏剂为UV胶黏剂。The ultra-thin incoming packaging method according to claim 6, wherein the light-curing adhesive is a UV adhesive.
  8. 根据权利要求7所述的超薄来料封装方法,其特征在于,所述对所述临时键合结构中的超薄晶圆和承载板实现键合,具体包括:The ultra-thin incoming packaging method according to claim 7, wherein the bonding of the ultra-thin wafer and the carrier board in the temporary bonding structure specifically includes:
    采用紫外光照射所述临时键合结构的承载板侧;Using ultraviolet light to irradiate the bearing plate side of the temporary bonding structure;
    将所述UV胶黏剂固化,使得所述临时键合结构中的超薄晶圆的第一表面和所述承载板实现键合。The UV adhesive is cured so that the first surface of the ultra-thin wafer in the temporary bonding structure is bonded to the carrier board.
  9. 根据权利要求8所述的超薄来料封装方法,其特征在于,所述第一胶带为透明胶带,所述解键合所述承载板和多个所述单粒芯片,具体包括:The ultra-thin incoming packaging method according to claim 8, wherein the first adhesive tape is a transparent adhesive tape, and the unbonding the carrier board and the plurality of single-chip chips specifically include:
    采用激光照射所述承载板侧,激光透过所述第一胶带和所述承载板将所述UV胶黏剂,解键合所述承载板与所述芯片。The side of the carrier board is irradiated with laser, and the UV adhesive is unbonded between the carrier board and the chip through the first adhesive tape and the carrier board.
  10. 根据权利要求1所述的超薄来料封装方法,其特征在于,所述在所述超薄晶圆的第二表面上形成多个通孔,暴露出所述焊垫,具体包括:The ultra-thin incoming package method according to claim 1, wherein the forming of a plurality of through holes on the second surface of the ultra-thin wafer to expose the solder pad specifically includes:
    对所述超薄晶圆的第二表面上对应所述焊垫的位置进行刻蚀处理,暴露出所述焊垫。Performing etching treatment on the position of the second surface of the ultra-thin wafer corresponding to the bonding pad to expose the bonding pad.
  11. 根据权利要求10所述的超薄来料封装方法,其特征在于,在所述对所述超薄晶圆的第二表面上对应所述焊垫的位置进行刻蚀处理,暴露出所述焊垫之后还包括:The ultra-thin incoming package method according to claim 10, characterized in that an etching process is performed on the second surface of the ultra-thin wafer corresponding to the pad to expose the solder After the mat also includes:
    形成绝缘层,所述绝缘层覆盖所述超薄晶圆的第二表面且所述绝缘层覆盖 所述通孔的侧壁,并暴露所述通孔的底面;Forming an insulating layer, the insulating layer covering the second surface of the ultra-thin wafer and the insulating layer covering the sidewall of the through hole, and exposing the bottom surface of the through hole;
    在所述绝缘层上形成再布线层,所述再布线层在所述通孔的底部与所述焊垫连接;Forming a rewiring layer on the insulating layer, the rewiring layer is connected to the pad at the bottom of the through hole;
    形成阻焊层,所述阻焊层覆盖所述再布线层和所述绝缘层;Forming a solder resist layer covering the rewiring layer and the insulating layer;
    在所述阻焊层上形成开口。An opening is formed on the solder resist layer.
  12. 根据权利要求11所述的超薄来料封装方法,其特征在于,所述在所述超薄晶圆的第二表面上制作多个焊接凸起,所述焊接凸起与所述焊垫电性连接,具体包括:The ultra-thin incoming packaging method according to claim 11, wherein the plurality of solder bumps are formed on the second surface of the ultra-thin wafer, and the solder bumps are electrically connected to the solder pads. Sexual connection, including:
    在所述开口内形成焊接凸起;Forming a welding protrusion in the opening;
    所述焊接凸起与所述再布线层电性连接,并通过所述再布线层与所述焊垫电性连接。The solder bump is electrically connected to the rewiring layer, and is electrically connected to the pad through the rewiring layer.
  13. 根据权利要求1所述的超薄来料封装方法,其特征在于,还包括:The ultra-thin incoming packaging method according to claim 1, further comprising:
    撕离所述第一胶带,所述第一胶带粘结所述承载板,将所述承载板与所述芯片分离。The first adhesive tape is torn away, the first adhesive tape bonds the carrier board, and the carrier board is separated from the chip.
  14. 一种封装结构,采用权利要求1-13任意一项所述的超薄来料封装方法形成,所述封装结构包括:A packaging structure is formed by the ultra-thin incoming packaging method according to any one of claims 1-13, and the packaging structure includes:
    电路板,所述电路板上包括多个电路结构,相邻两个电路结构之间设置有切割道;A circuit board, the circuit board includes a plurality of circuit structures, and a cutting channel is provided between two adjacent circuit structures;
    多个芯片,一个芯片与一个所述电路结构电性连接;Multiple chips, one chip is electrically connected to one of the circuit structures;
    位于每个所述芯片背离所述电路板的承载板;A bearing board located on each chip away from the circuit board;
    覆盖所述承载板和所述切割道的第一胶带,所述第一胶带与所述承载板和所述切割道粘结。A first adhesive tape covering the carrier board and the cutting lane, the first adhesive tape being bonded to the carrier board and the cutting lane.
PCT/CN2019/116270 2018-11-07 2019-11-07 Ultra-thin incoming material packaging method and packaging structure WO2020094095A1 (en)

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